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Hello, I am intersted in putting designing FFT and DCT on FPGA. The same I want to implement just like Higher languages.Please help me how can I represent Floating point on FPGA. Thankyou for your valuable response -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 9676
> Not to mention the growing tendency to incorporate a time-lock in the >dongle (or its software). Many CAE packages are now sold for, say $9K, >with a $1500 annual maintenance fee (real figures, from one major >vendor). The dongle disables itself on a set date, & I have to >purchase a new licence to re-activate it. This *may* be illegal, in some countries at least. Here in the UK, a long time ago, Xilinx used to have a "magic number" which one had to enter into one's PC to make the software run. Every 12 months this would expire, and one had to phone Xilinx for a new number. They had to supply this free of charge, according to their then engineers. Eventually, they got fed up with all the phone calls, and issued a non-expiring number. The simple way to defeat that expiring magic number was to set the PC clock back, but then all one's project files ended up with the wrong date stamps. > Also the (all too common) license clause that prohibits transferring >the license to any other person. I am not a lawyer, but again here in the UK this sort of thing borders on being unenforceable - it is against the principles of fair trading. The fact that the software is licensed and not sold outright is hardly relevant; you can sublet a lease on a property, etc. > A further gripe is the replacement policy. The vendors blandly state >they will replace a damaged (& returned) dongle, but not a lost or >stolen one. Good firms will replace a broken dongle, but with the best will in the world they cannot do this if they no longer have them around. Which is what happens if you are one of those people who like to stick with old and trusted (=="obsolete") tools. My general observation, and to be fair to Xilinx on this point, is that for years they were stuck with expensive tools (like Viewlogic) which they were powerless to give away even if they wanted to. (Viewlogic had perfected the art of ripping off most people most of the time). What I could never understand is why a) a firm with such massive revenues as Xilinx could not have written its own *decent* equivalents (and I don't mean Foundation) and b) why they had to charge so much for their P&R tools which - let's face it - were useless except for Xilinx chips! Many, many small firm design-ins were lost to other FPGA vendors as a result of this idiocy. Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 9677
David Pashley <david@fpga.demon.co.uk> wrote: > I don't have a problem with that. I was following up on what Don Husby > wrote: > > "Viewlogic please!! > "As someone mentioned earlier, the Viewlogic licensing scheme is a pain > "in the > "ass, and often makes it impossible to use their software even with a > "valid license. > > And that's what my "nonsense" as you call it was referring to. Does it > sound like he's looking to remove the protection from a "no longer > supported" product? Do you have a problem with this? I have a valid license. It's the knuckleheads at Viewlogic that fail to live up to their end of the agreement. I have no problem with breaking the dongle under these circumstances. Imagine how annoying it would be if all software was licenesed like Viewlogic's: Not only does it require a dongle, it must be the first dongle on the parallel port else it won't work. It expires every two years giving you the "opportunity" to call the sales people and bitch at them. If you booted your PC this morning and got the message "Your windows 95 license expires in 30 days, please call Microsoft sales for more information." wouldn't you be pissed? What makes Viewlogic think they can get away with it? The funny thing is, I was just getting to the point where I was kind of liking Viewdraw again. We are curently looking for a new VHDL/Verilog system, and probably would have considered Viewlogic. Now it's at the bottom of the list. -- Don Husby <husby@fnal.gov> Phone: 630-840-3668 Fermi National Accelerator Lab Fax: 630-840-5406 Batavia, IL 60510Article: 9678
IMO, the removal of the dongle license is irrelevant. What can you use the Xilinx s/w for other than developing Xilinx FPGAs ? Xilinx can make good revenues from the silicon itself. I have always mentioned to the EDA companies this fact. What are they selling, Silicon or Software ? I'm not against using dongles, but I do disagree with the maintainence deals that go along with them. You are tied in forever to buying their "Upgrades" (especially when they re-release new silicon!). You also get stuck when you want to maintain old designs as they obselete the parts in the upgrades. I thought this was a maintenance deal where you would be able to maintain older designs as well. Its not fun having to re-install older s/w so that you can re-work an old design. The way I do this is to have 2 computers (older s/w on one and newer s/w on the other) - Not Ideal but it works. I move the dongle between them. --------------- Gareth Baron Peter wrote: > >There you go again. Where did I talk about "promoting illegal use"? > > Here's your text: > > How can you justify promoting the removal of security devices? Surely > the resulting illegal copying of software (the use to which many would > inevitably put this information) is against the interest of both the > paying customers and those who make a living from providing and > supporting the software? > > Peter. > > Return address is invalid to help stop junk mail. > E-mail replies to zX80@digiYserve.com but > remove the X and the Y.Article: 9679
rk: <snip wonderful stuff about dongles and parallel ports> ray: : I ran into the printer driver problem. My solution was to get one of : those parallel port ISA cards. NOw I've got 3 parallel ports, one of : which is dedicated to the keys. I've seen others use a port switch. : Neither is elegant but they work. rk: screwed again. new motherboard doesn't have very many isa slots. i'm out. unless i pay to upgrade another card. and, i got a laptop and want to move to that. sort of might work there, if i print via the network and not the parallel port and decide to never again do cae on desktop. wonderful choices. ray: : I'm not sure the new xilinx security (using the serial number of the : Cdrive) is any better. One one hand, you don't tie up the parallel port : and don't have keys to loose. On the other hand, I can't load the SW : onto my laptop and take it with me anymore. Also, what happens when my : drive gives up the ghost or I decide to trade up? rk: it's a pita [guess the acronym, win a prize], of course. -- -------------------------------------------------------------- rk "there's nothing like real data to screw up a great theory" - me (modified from original, slightly more colorful version) --------------------------------------------------------------Article: 9680
gareth: : The way I do this is to have 2 computers (older s/w on one and newer s/w : on the other) - Not Ideal but it works. I move the dongle between them. rk: yup, another user who not only archives the design, but archives hardware as well. can't read the dongles with old software on a new machine with a fast processor; MARVELOUS!!!!!!!!! so, i have one machine with the motherboard in the case along with the hard drive with old os and cae software. balanced somewhat carefully on top of the case is the new mother board and new hard disk. this way, i can maintain old stuff. of course, i have to be careful when the cleaning people come in with their mops, but that's another story. -- -------------------------------------------------------------- rk "there's nothing like real data to screw up a great theory" - me (modified from original, slightly more colorful version) --------------------------------------------------------------Article: 9681
: David Pashley <david@fpga.demon.co.uk> wrote: : > I don't have a problem with that. I was following up on what Don Husby : > wrote: : > : > "Viewlogic please!! : > "As someone mentioned earlier, the Viewlogic licensing scheme is a pain : > "in the : > "ass, and often makes it impossible to use their software even with a : > "valid license. : > : > And that's what my "nonsense" as you call it was referring to. Does it : > sound like he's looking to remove the protection from a "no longer : > supported" product? don: : Do you have a problem with this? : I have a valid license. It's the knuckleheads at Viewlogic that : fail to live up to their end of the agreement. I have no problem : with breaking the dongle under these circumstances. rk: of course, while we're all in b*tch mode, a certain company producing CAE software, say Brand 'V', has a marvelous policy with the dongle which creates the following, beautiful situation. let's say you have two machines, hypothetically speaking, both running software constrained to run the package for Brand 'X' (pun intended, of course). Now, let's say, you invest extra $ to have machine 2 run software for all brands, cause you want to do one or two designs using brand 'A' fpga. now machine 2, gloating with it's capability, does it thing, perhaps doing some work on a brand 'X' fpga, helping out designer 1, and then sends the files back to machine 1 and designer 1. the design, all for brand 'X', can no longer be read on machine 1 with the brand 'X' constrained licence. why, because the more powerful license on machine 2 'touched' the files. i'd say this qualifies as a pita, [ok, pain in the *ss], since after investing dollars to upgrade one piece of software, two designers, both licensed for Brand 'X', can no longer work on the same project, unless they spend more $. now what to do with those useless dongles sitting in my desk draw ... get out the hockey stick? -- -------------------------------------------------------------- rk "there's nothing like real data to screw up a great theory" - me (modified from original, slightly more colorful version) --------------------------------------------------------------Article: 9682
I'm a professor at Auburn University, and we have a bunch of Xilinx demo boards with XC4003A chips that we've used in various classes. While obsolete, they are fine for students' first exposure to FGPA's. We have Mentor Graphics Design Manager, Design Architect, etc. Now, it's been about 2 years since I last used any of these, but it appears that the current version of Design Manager supports only the Spartan, 4000E, 4000X, 4000XL, and 4000XV families. Xilinx advocates using 4003E to replace 4003A since it is pin-compatible. However, the A and E series are not bitstream compatible. Is there any way to generate .bit files for the 4000A series with Mentor or Xilinx's current tools?Article: 9683
In article <01bd5c1a$51e1cea0$7684accf@homepc>,
rk <stellare@erols.comNOSPAM> wrote:
>screwed again. new motherboard doesn't have very many isa slots. i'm out.
>unless i pay to upgrade another card.
You're screwed anyway since the ISA card is not necessarily enough. For
example, APR version 3.3 does not work on a PPRO-200, even if you have put
the dongle on an ISA card printer port.
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 9684
We are in a monolopy situation. The dongles will not go away until the
companies have real non-dongled competition and realize that fact, as
happended with copy-protection for office software. Remember Lotus 123
version 2? You got two installs before you were screwed. You could
uninstall back to the floppies, but not if your hard drive croaked. Once
Excel started to eat into their profits, the copy protection disappeared.
The fact is that Xilinx offers the most diverse line of easily obtainable
FPGAs, which makes them enough of monopoly to keep the copy protection on
their software. The situation was worse 8 years ago, when they were the
only manufacture of FPGAs. They do have competition these days, and the
copy protection has consequently eased with the M1 software: the C: drive
serial number is a far better situation than the hardware dongle, since it's
easily changeable. Basically they have no real copy protection since this
is so easily defeated.
Then there's Viewlogic: crummy software with lots of non-dongled
competition. They don't seem to be aware of the situation, which can be
readily observed by checking their stock price :-)
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 9685joe: : Then there's Viewlogic: crummy software with lots of non-dongled : competition. They don't seem to be aware of the situation, which can be : readily observed by checking their stock price :-) rk: <official disclaimer - any comments appearing below may or may not relate to the above post - YOU be the judge - end official disclaimer> anyways, some have talked about the great maintenance fees along with dongles. yes, isn't it wonderful to get your new release of brand "V" software, see that a few bugs were fixed, problems with license files, some new user interfaces to learn, some good features disappeared, and the very exciting game of playing "massachusettes roullette [too cranky to spell, no flames, look it up yourself], wondering what previously working s/w and features are now bug-ridden and need work-a-rounds. like, for example, hypothetically, of course, just netlisting a board becomes an advanture. and i upgraded just to use the new "NC" feature on unused pins. MARVELOUS!!!!!!!!!!!!!!!!!!! this just says there needs to be standards for file formats so we don't get locked into cae vendors specific platforms. this will encourage COMPETITION and GREED - and somebody can come in and take the market away if they can build to a standard, do it better and cheaper. sometimes greed is good. but not when you're locked in. then you have to pay and pay and have no leverage other than chucking everything, which often is practical. -------------------------------------------------------------- rk "there's nothing like real data to screw up a great theory" - me (modified from original, slightly more colorful version) --------------------------------------------------------------Article: 9686
David Pashley <david@fpga.demon.co.uk> writes: > How can you justify promoting the removal of security devices? Surely > the resulting illegal copying of software (the use to which many would > inevitably put this information) is against the interest of both the > paying customers and those who make a living from providing and > supporting the software? Hm, AFAIK Windows is not really protected against copying. Did that make Microsoft broke ? Doesn't seem to (unfortunately). By the way, I don't really see any relation between cracking and support revenues. If someone uses pirated SW it's because he doesn't want to buy it, he wouldn't generate a cent in your support business anyway. Did it occur to you that if the SW was more realisticly priced your customer base would increase by a high factor ? In addition, highly priced EDA SW is mostly used by corporations who can and do pay for it. Small businesses and private persons who may use pirated copies would not generate SW revenue at all but they may generate silicon revenues with the pirated copy. In addition, though the price is much less ridiculous, take a look at the compiler market. You can have gcc for almost any decent CPU under the Sun for free. Still, people go and buy compilers/debuggers from various companies and fork out the few thousand dollars for it, even if the quality of and support for the pay-for stuff is often way below what the free thing can offer. (The reason ? Beats me :-) Also, you can have the RTEMS real time kernel for free. You may choose to go on your own or you can buy support for it (you get the source either way for free). You will be surprised: people go and actually buy support for the product. One should not assume that the majority of the *engineers* are direct descendants of pirates, robbers or thiefs. Marketing managers probably are, but most engineers ain't. Approaching them with a little hint of assuming some sort of decency in their low-life existence may reveal that they can act sorta human-like and don't jump on you searching for your wallet while smashing your head with their stone axes or oscilloscope probes. Protecting yourself against a nonexistent enemy while making your friends suffer is a Very Bad Thing, IMHO. Trying to rip off those who are actually in your camp with forced upgrades, forced useless maintenance contracts and so on is an Even Worse Thing. In addition, but this is an other thread, witholding technical information to generate unrealistic revenues and create a monopolistic situation is The Worst Thing. (If Microsoft got sued for bundling IE with Win, why chip manufacturers aren't sued for bundling the chips with *their* P&R SW ? :-) Zoltan #include <std.disclaimer> -- +------------------------------------------------------------------+ | Reply address antispammed. Use ZOLTAN-at-BENDOR-dot-COM-dot-AU | +--------------------------------+---------------------------------+ | Zoltan Kocsi | I don't believe in miracles | | Bendor Research Pty. Ltd. | but I rely on them. | +--------------------------------+---------------------------------+Article: 9687
In article <351FF25A.BBC9DBE0@eng.efi.com>, Gareth Baron <gareth.baron@eng.efi.com> writes >IMO, the removal of the dongle license is irrelevant. What can you use >the Xilinx s/w for other than developing Xilinx FPGAs ? Xilinx can make >good revenues from the silicon itself. I have always mentioned to the EDA >companies this fact. What are they selling, Silicon or Software ? They are selling software that enables you to use their silicon, which "incidentally" raises a significant barrier to switching to, or even just trying out, someone else's devices. Shame that Neocad went away. With that s/w you didn't need any vendor tools at all. But the veondors didn't like the way you could switch target at a whim. So, you've got a point against the silicon vendors, but not against the EDA vendors who have to make a living only from s/w. DavidArticle: 9688
If I understand the Xilinx Data Book 1998 correctly, both families
(the XC4000XL and the XC4000XLT) have clamp diodes from all IO pins
to a common internal metal wire called Vtt.
For the XC4000XL this wire is not bonded to any device pin,
versus for XC4000XLT some of the IO pins are lost and used to connect the
internal Vtt to the outside.
This Vtt clamp scheme is used for PCI bus applications, as a diode
termination for the PCI bus.
I fear there might be a problem with the floating Vtt net for the
XC4000XL devices.
I suppose this Vtt net has a comparably large capacity:
Vtt floating
|----------------------------
| |
--- --- unknown capacity of
/ \ --- internal Vtt net
--- |
| ------- |
|pin>-----------+------| IOB | gnd
| -------
---
/ \
---
|
|
gnd
Does anybody know whether the XC4000XL does some trick to avoid
that a single rising input might have to charge this capacity ?
(in case all IO pads were low for some time)
I see three possible problems:
1) it might sometimes happen that input transitions are hindered/delayed
2) it might sometimes happen that output transitions are slowed down
3) the behaviour of the IO pins cannot easily modelled (IBIS ??)
thus making it difficult to predict signal waveforms of PCB traces.
Has anybody some idea ?
Does anybody have already experienced some troubles ?
Article: 9689David Pashley wrote: > If you're uncomfortable about licensing and support issues, go to a VAR, > who will be geared up to provide the sort of customer care you (rightly) > expect. I've got to admit, life's better now that I buy my tools from someone who gives a damn, rather than from a silicon shifter. Live and learn... SteveArticle: 9690
In article <6foe42$30c$1@info1.fnal.gov>, Don Husby <husby@fnal.gov> writes > >Do you have a problem with this? >I have a valid license. It's the knuckleheads at Viewlogic that >fail to live up to their end of the agreement. I have no problem >with breaking the dongle under these circumstances. > >Imagine how annoying it would be if all software was licenesed like >Viewlogic's: Not only does it require a dongle, it must be the first dongle >on the parallel port else it won't work. That may be true for you, but it's not true in general. Viewlogic dongles are not position-sensitive. Occasionally you get combinations of dongles that don't work, and experimenting with the order can fix things. My guess would be that this is what you are experiencing. It beats me if you have problems like this why you don't just bring them to the group, rather than complain here after the event. Sorting out tech. problems is something that this group always does very well. >It expires every two years giving >you the "opportunity" to call the sales people and bitch at them. > > If you booted your PC this morning and got the message "Your >windows 95 license expires in 30 days, please call Microsoft sales >for more information." wouldn't you be pissed? What makes Viewlogic >think they can get away with it? I agree with you. The other "big" EDA companies also do this, but that's hardly an excuse. > > The funny thing is, I was just getting to the point where I was kind of >liking Viewdraw again. We are curently looking for a new VHDL/Verilog >system, and probably would have considered Viewlogic. Now it's at the >bottom of the list. I should take a look anyway. FPGA Express is excellent, and there are a lot of other recent improvements to the VHDL/Verilog verification environment. If you're uncomfortable about licensing and support issues, go to a VAR, who will be geared up to provide the sort of customer care you (rightly) expect. -- David Pashley < ------------------------ < < < ---------- Email: david@fpga.demon.co.uk | Direct Insight Ltd < < < < > Tel: +44 1280 700262 | | * The EDA Source * < < < Fax: +44 1280 700577 | --------------------------- < ------------------------------------------Article: 9691
Hi, Gareth Baron wrote: > > I'm looking for a shareware/freeware Verilog to VHDL translation tool. > It must run under DOS/WINTEL Machines. > I know of only one free Verilog -> VHDL translator: ftp://ic.berkeley.edu/pub/Tools/verilog2vhdl.tar.Z For further (commercial) translators take a look at the comp.lang.vhdl FAQ (Part 3, Section 4) located at http://vhdl.org/comp.lang.vhdl/ Bye,... Edwin -- ----------------------------------------------------------- Edwin Naroska Computer Engineering Institute (Lehrstuhl fuer Datenverarbeitungssysteme) University of Dortmund, 44221 Dortmund, Germany phone: ++49 231 7552406, fax: ++49 231 7553251 -----------------------------------------------------------Article: 9692
Hi everyone, I have a need to implement a Digital Phase Locked Loop on and FPGA using V-System as the VHDL compiler and Xilinx as the synthesis software. If it is not possible, I will need to look at other ways to determine a suitable clock for an incoming serial stream of data (of undetermined frequency) and keep this clock in sync. However, in order to do this the second way (without a DPLL) I would require a quartz clock crystal running at preferably greater than 80 MHz. Does such a thing exist? If not, is there a way of creating a faster clock using some clever coding from a slower quartz crystal? eg, using a 20 MHz quartz crystal and creating a 40 Mhz clock from it? I have a feeling this might be possible but has anyone else done it? Any suggestions or help is greatly appreciated! Kind Regards, Steve Phillipson - A confused undergraduate engineer!Article: 9693
Martin Neilan wrote: > > Hi everyone, > > I have a need to implement a Digital Phase Locked Loop on and FPGA using > V-System as the VHDL compiler and Xilinx as the synthesis software. If > it is not possible, I will need to look at other ways to determine a > suitable clock for an incoming serial stream of data (of undetermined > frequency) and keep this clock in sync. > > However, in order to do this the second way (without a DPLL) I would > require a quartz clock crystal running at preferably greater than 80 > MHz. Does such a thing exist? If not, is there a way of creating a > faster clock using some clever coding from a slower quartz crystal? > eg, using a 20 MHz quartz crystal and creating a 40 Mhz clock from it? I > have a feeling this might be possible but has anyone else done it? > > Any suggestions or help is greatly appreciated! > > Kind Regards, > Steve Phillipson > - A confused undergraduate engineer! Oopps! Had my details set wrong in Netscape :( Correct details: Stephen Phillipson (hslcomp@iinet.net.au) Sorry!Article: 9694
Andrew V. Nesterov wrote: > > In article <351813B4.9DE25395@computer.org>, Vitit Kantabutra <vkantabu@computer.org> wrote: > > Thanks. Yes, I've written a paper about it and submitted it to ICCD '98 a few > > days ago. I'll send you a copy via email. I just didn't want to send a paper > > to a newsgroup. > > > I'd also like to take a look at it. Please send it to me too. > Thanks, > > --Andrew Please send me a version of your paper too.Article: 9695
Vitit Kantabutra <vkantabu@computer.org> a écrit dans l'article <351813B4.9DE25395@computer.org>... > Thanks. Yes, I've written a paper about it and submitted it to ICCD '98 a few > days ago. I'll send you a copy via email. I just didn't want to send a paper > to a newsgroup. Please send me a version of your paper too. Jean-Louis VERN jlvern@writeme.comArticle: 9696
Hi In article <34d7bdd5.9940944@news.connect.com.au>, Stuart Summerville <stuart.summerville@surv.practel.com.au> writes >Hi, > >I am after any experience you have in ways that any of the above >packages are better than each other. I haven't used any of the other two packages, but can answer a few of your questions on WVO. > >I'm currently using WVO (schem only, not VHDL - yet!), but due to >Xilinx' apparent reduction in support for this package, I am >considering the other two packages as I need to (for my own reasons) >move to (purchase) any one of them now. > The apparent reduction in support for WVO from Xilinx is because Viewlogic are now handling all support issues for the WVO portion of the tools. If you require any tech. support for WVO, your local Viewlogic offices will be able to help. They'll also be able to upgrade to an unrestricted version which will allow you to design FPGAs from other vendors and give you access to Intelliflow, and Speedwave( their VHDL simulator). >Both OE & Fd seem to be more user friendly in several ways (compared >to WVO 7.2), eg. the simulation tools. They also seem to have much >tighter integration of features than WVO, particularly in interfacing >to M1 core tools. WVO7.4 now incorporates a FPGA flow management tool called Intelliflow. This facilty seamlessly integrates all the Viewlogic FPGA design tools with your FPGA vendors place and route tools. You can perform all the tasks associated with your design - simulation, synthesis, implementation, etc. in one environment. > >Apart from Foundations lack of VHDL simulation support (standard >version), they seem on a par, both with their pros & cons. > >Obviously these packages are at the lower end of the EDA tools market >- I just want an idea of your opinion of where these products stand - >past, present, & future. Any past reviews of the low end EDA tools >would also be of interest. > As you already have an version of WVO it is worthwhile evaluating the latest version. The upgrade may be more cost effective than buying a completely new system. >Regards, > >Stu. >--------------------------------------------- >Stuart Summerville >Project Engineer >Practel Surveillance Systems >650 Burwood Road, Hawthorn, Victoria 3122. >Tel: (61.3) 9813 3636 Fax: (61.3) 9813 3733 >Email: stuart.summerville@surv.practel.com.au >--------------------------------------------- Regards ChrisArticle: 9697
Hi Stephen, 1. For digital PLL, you can see http://www.xilinx.com/xapp/xapp028.pdf and use a VCO ( 74S128 ) to generate the clock.( Higher than 100MHz can achieve ) 2. You can find a 80MHz OSC easy, higher frequency......I don't know. :) 3. You can design your circuit for bi-phase clocking, then you may half the clock rate. ____________________________________ Roger Yau Electronic Engineer ( ASIC and DSP Dept. ) CASIL R & D Co., Ltd.Article: 9698
Hi Stephen, 1. For digital PLL, you can see http://www.xilinx.com/xapp/xapp028.pdf and use a VCO ( 74S128 ) to generate the clock.( Higher than 100MHz can achieve ) 2. You can find a 80MHz OSC easy, higher frequency......I don't know. :) 3. You can design your circuit for bi-phase clocking, then you may half the clock rate. ____________________________________ Roger Yau Electronic Engineer ( ASIC and DSP Dept. ) CASIL R & D Co., Ltd.Article: 9699
As far as I remember, No. You have to use the older s/w to support the older chipsets. It was the same problem when the move between the 3000's and the 3000A's. This is why people have been griping about the s/w maintenance. You have to archive the designs and the EDA s/w. The bitstreams are upward compatible but definitely not downward compatible. If you don't have the old s/w it may be just as well to re-compile your designs with the new s/w and hope that the critical nets timings don't change on you. I would strongly advise asking Xilinx themselves about these issues as a lot of people have gone through this. They are usually very helpful. ---------------- Gareth Baron Richard Chapman wrote: > I'm a professor at Auburn University, and we have a bunch of Xilinx > demo boards with XC4003A chips that we've used in various > classes. While obsolete, they are fine for students' first exposure to > FGPA's. We have Mentor Graphics Design Manager, Design Architect, > etc. Now, it's been about 2 years since I last used any of these, but > it appears that the current version of Design Manager supports only > the Spartan, 4000E, 4000X, 4000XL, and 4000XV families. Xilinx > advocates using 4003E to replace 4003A since it is pin-compatible. > However, the A and E series are not bitstream compatible. Is there > any way to generate .bit files for the 4000A series with Mentor or > Xilinx's current tools?
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