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David Pashley wrote: > They are selling software that enables you to use their silicon, which > "incidentally" raises a significant barrier to switching to, or even > just trying out, someone else's devices. Shame that Neocad went away. > With that s/w you didn't need any vendor tools at all. But the veondors > didn't like the way you could switch target at a whim. > > So, you've got a point against the silicon vendors, but not against the > EDA vendors who have to make a living only from s/w. > > David Neocad was not a perfect solution. I seem to remember that you still used vendor specific libraries and had to buy the vendor specific (or even family specific) back end tools separately. So if you bought the software to develop Xilinx 3000 series chips, you had to pay more to develop Lucent, or even XC4000 series chips. But then you could buy a full licence (for about the cost of 3 or 4 different vendor backend parts) and get everything Neocad supported. Rick Collins redsp@*remove*writeme.com Remove the *remove* to email me.Article: 9726
Hi all! I have to design a Reed-Solomon encoder in VHDL for a graduate university project. The semester is ending soon and I think I took a bigger bite than I can chew! So I'm looking for practical implementation of the Reed-Solomon algorithm. Can anyone give me a hint? Thanks in advance! SLYArticle: 9727
Ho Voon Yee wrote in message <6fv19l$lun$1@nuscc.nus.edu.sg>... >In article <35215640.5CE9757B@eug.upv.es> you wrote: >: I'm working in Altera FPGA's.I'm want to make a board configurable from >: the computer, but I need the bitblaster or byteblaster. Somebody knows >: how this devices are make?? > > >: Felip Vicedo Roman >: feviro@eug.upv.es > >Check out the site > >http://www.acte.no/freecore/didnt.htm > >Regards, >Ho Voon Yee > > Check on site www.altera.com there is file in .pdf format description and schematic of byte blaster Regards LevArticle: 9728
>Neocad was not a perfect solution. I seem to remember that you still used >vendor specific libraries and had to buy the vendor specific (or even family >specific) back end tools separately. So if you bought the software to develop >Xilinx 3000 series chips, you had to pay more to develop Lucent, or even XC4000 >series chips. > >But then you could buy a full licence (for about the cost of 3 or 4 different >vendor backend parts) and get everything Neocad supported. Without trying to develop a "why did Neocad disappear" thread, I recall looking very closely at Neocad around 1993-94. Their pricing was so close to everything else then on the market that there was no advantage, unless you desperately wanted to be able to bet on their promise to be able to change the P&R back-end stuff to another vendor. And the otherwise-impressive software was quite buggy, crashing during the demo. Which is the last thing you want because if they had such obvious bugs, they probably had lots of subtle ones too. There may be no way to find a subtle bug in a P&R tool - the device will just not work in funny ways. And which probably explains why it took Xilinx a few years to "integrate" the stuff into their product range. Dropping the rather good XACT6 was a stupid idea, but that's another matter. IMHO, Neocad got their market positioning wrong. They tried to do what the other well-established vendors have always been doing: screwing all of the people all of the time. This is fine if you have a superior product, but that is hard to advertise in a market where everybody else is already charging prices inflated in the standard way to create the perception of high quality. Neocad should have gone in at < $2000 for the lot. They should also have sold the product directly to users instead of via the very same types of dealers who like to sell expensive EDA software and who don't want to handle anything whose price tag contains less than a certain # of zeroes. In the end, presumably Xilinx made the owners an offer they could not refuse. Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 9729
Bill Seiler <ccwest@ix.netcom.com> wrote in article <6fu6bu$jhf@sjx-ixn7.ix.netcom.com>... : April 1, 1998 : : Are you tired of fighting with Xilinx, Actel, Altera, or : some other FPGA tools : : I have an idea for a new technology. : : I call it HSI (Huge Scale Integration). : : HSI is based on TI's latest advance in Logic devices, : PicoGate Logic. You can now get a single NAND gate in : a SOT5 package that is about 3 X 3 mm in size. : See http://www.ti.com/sc/docs/asl/sin_gate.htm : I figure you could make an array of 100 X 100 of these : PicoGate NAND gates on a board. The board would be about : 1 square foot in area. This would give you 10,000 gates. : You could could use a dependable PCB layout tool such as : PADS to route the board to implement your logic. : Every gate in the array could be probed for debuging. : : What do you think? rk: in the spirit of april 1, i will add why not put them on the board and connect them up with the FPIC technology (aptix?), perhaps on the back side of the board, so as not to mess up your b-u-t-full array. -- -------------------------------------------------------------- rk "there's nothing like real data to screw up a great theory" - me (modified from original, slightly more colorful version) --------------------------------------------------------------Article: 9730
Hi, We're looking for a 'right' FPGA tools (near up to 8k gates) and i wonder what kind of FPGA would i use...Xilinx and their Foundation software (along with VHDL) or buying tools from other company...? Any clue ? François. -- ------------------------------------------------------------- THIEBOLT Francois \ You think your computer run too slow ? UPS Toulouse III \ - Check nobody's asked for tea ! thiebolt@irit.fr \ "The Hitchikers Guide to the Galaxy" D.Adams -------------------------------------------------------------Article: 9731
In article <35235253.40734923@news.netcomuk.co.uk>, Peter <z80@ds2.com> writes > > >Without trying to develop a "why did Neocad disappear" thread, I >recall looking very closely at Neocad around 1993-94. > >Their pricing was so close to everything else then on the market that >there was no advantage, unless you desperately wanted to be able to >bet on their promise to be able to change the P&R back-end stuff to >another vendor. The reason why NeoCAD became popular was superior quality of results when compared with XACT. You could 95% utilize a 3090 and get 20% to 30% better performance than XACT. The vendor-independence was not why people bought it, although they did have one eye to the future potential. The vendor-independence was more promise than reality until just before the end. The FPGA Evaluator product, allowing you to compare *place-and-routed* results for Xilinx, Actel, ALtera, Quicklogic and Lucent after an overnight run was scary for the vendors, and a breath of fresh air for FPGA users. NeoCAD was acquired within weeks of that product announcement. > >And the otherwise-impressive software was quite buggy, crashing during >the demo. Which is the last thing you want because if they had such >obvious bugs, they probably had lots of subtle ones too. There may be >no way to find a subtle bug in a P&R tool - the device will just not >work in funny ways. NeoCAD FPGA Foundry was extraordinarily bug-free. We had dozens of users in the UK, and problems were rare. You must have been unlucky. I can't comment on the circumstances, since you do not tell us who you are. > >And which probably explains why it took Xilinx a few years to >"integrate" the stuff into their product range. Dropping the rather >good XACT6 was a stupid idea, but that's another matter. > >IMHO, Neocad got their market positioning wrong. They tried to do what >the other well-established vendors have always been doing: screwing >all of the people all of the time. This is fine if you have a superior >product, but that is hard to advertise in a market where everybody >else is already charging prices inflated in the standard way to create >the perception of high quality. Neocad should have gone in at < $2000 >for the lot. > > You're entitled to your opinion. Mine is that you shouldn't compare the pricing of an EDA company with that of a silicon vendor. The EDA company has to make money from software, the silicon vendor doesn't. >They should also have sold the product directly to users instead of >via the very same types of dealers who like to sell expensive EDA >software and who don't want to handle anything whose price tag >contains less than a certain # of zeroes. That's untrue. We sell and support tools for under $500 for people who want them. We also provide tools which are much much more expensive - and people buy them too, because the gains in productivity see them way ahead overall. When you take into account the cost of employing high quality EEs, the costs associated with losing a week when under time-to- market pressure, and the saving from using a slightly smaller device, surley you see that tool price is not the biggest issue for everyone. Many people value the excellent tech. support that we and VARs in general provide. Your anonymity does not lend credibility to your attack. -- David Pashley < ------------------------ < < < ---------- Email: david@fpga.demon.co.uk | Direct Insight Ltd < < < < > Tel: +44 1280 700262 | | * The EDA Source * < < < Fax: +44 1280 700577 | --------------------------- < ------------------------------------------Article: 9732
On Tue, 31 Mar 1998 22:46:56 +0200, Felip Vicedo Roman <fvicedo@eug.upv.es> wrote: >I'm working in Altera FPGA's.I'm want to make a board configurable from >the computer, but I need the bitblaster or byteblaster. Somebody knows >how this devices are make?? > > >Felip Vicedo Roman >feviro@eug.upv.es Follow this link: http://193.215.128.3/freecore/didnt.htm Regards - Adam Biniszkiewicz Adam Biniszkiewicz Technical University of Zielona Gora ul. Podgorna 50, Zielona Gora, POLAND e-mail: A.Biniszkiewicz@pz.zgora.plArticle: 9733
> Then there's Viewlogic: crummy software with lots of non-dongled > competition. They don't seem to be aware of the situation, which can be > readily observed by checking their stock price :-) Their stock went from $10 to almost $30 over the past year. Certainly no incentive for them to change... Sorry, I don't get your point... AustinArticle: 9734
> >Anyway, it has been proven beyond the shadow of a doubt that companies are > >NOT 'deprived' of their income by pirated software, as %99 of pirated > >software is used by someone who would not have bought it in the first > >place, also a good number of them, if they are using the software > >regularly, eventually do buy it. It's the best marketing tool the software > >industry has to offer. > > Nonsense. If that's true, tell me why nearly every EDA company continues > to protect its software in this way? Don't tell me! they're all wrong, > and you are right? It's not nonsense. Not meaning to sound rude, but you don't have to believe it (or like it) for it to be true. Most all EDA companies have always been greedy, actually, very greedy. Funny how Lotus profits soared when they removed their protection schemes! Microsoft never had any....and it has certainly aided and abeded in their marketplace dominance. The (greedy) EDA companies marketing have this perception that the hardware key actually does some good. If these gumps got a clue, they would use address node locks (hard coded usually in a ROM, or in the actual Ethernet controller chip), like Unix software does. So what if a PC doesn't have a NIC (network interface card) in it, just give them one (they only cost $10...that is LESS than the price of a hardware key from the (greedy) hardware key vendors!). > In over 12 years in the EDA industry, I've seen a number of cases where > logic such as that you present has been used to justify the removal of a > hardware lock. In every case, revenue dropped sharply without any > corresponding evidence of a decrease in product usage. That's why the > locks are there - experience shows they are needed. Please cite one and provide a source for corroboration. I can not recall (in my 22 years in the industry) this phenomenon occurring. I believe as (you are) a VAR, I would understand you could be nervous about loosing some income if CAE vendors removed their 'protection'. I'm not saying you are nervous about loosing income, but that I would understand IF you were. Oh, and by the way, in the US, it is NOT illegal for me to do 'something' to remove the hardware key. It would be illegal if I was using a pirated copy, or sold a pirated copy for $$$. Legally, I can disassemble, reverse engineer and/or modify any software (or hardware) as I see fit (despite what the supposed licenses claim). That was made clear in Sega v Accolade. Austin Franklin darkroom@ix.netcom.comArticle: 9735
In article <01bd5e54$fa2aba90$2df65ecf@drt3>, Austin Franklin <d9arkroom@ix.netcom.com> writes > >It's not nonsense. Not meaning to sound rude, but you don't have to >believe it (or like it) for it to be true. Most all EDA companies have >always been greedy, actually, very greedy. Funny how Lotus profits soared >when they removed their protection schemes! Microsoft never had any....and >it has certainly aided and abeded in their marketplace dominance. I think EDA companies range from the very greedy to those who are in it just for the love of it. I wish I could name names :-) Your analogy between Microsoft/Lotus and EDA companies raises interesting questions. With those products, there is no 15% per year maintenance (and no support) - when an upgrade happens, you repurchase the product - albeit at a slightly discounted rate for existing users. If a single purchase entitled you to all future releases, the attitude to protection might be different. > >The (greedy) EDA companies marketing have this perception that the hardware >key actually does some good. If these gumps got a clue, they would use >address node locks (hard coded usually in a ROM, or in the actual Ethernet >controller chip), like Unix software does. So what if a PC doesn't have a >NIC (network interface card) in it, just give them one (they only cost >$10...that is LESS than the price of a hardware key from the (greedy) >hardware key vendors!). I agree. However, it's not greed that delays the implementation of IP address locking so much as the need for someone to provide (commercially) such a scheme. When the dongle-free FlexLM floating licence scheme became available on PC last year, forward thinking EDA vendors like Viewlogic and Chronology implemented it. > >> In over 12 years in the EDA industry, I've seen a number of cases where >> logic such as that you present has been used to justify the removal of a >> hardware lock. In every case, revenue dropped sharply without any >> corresponding evidence of a decrease in product usage. That's why the >> locks are there - experience shows they are needed. > >Please cite one and provide a source for corroboration. I can not recall >(in my 22 years in the industry) this phenomenon occurring. I'd like to do so, but confidentiality prevents the disclosure of sales data for products with which I have worked. I'll work on it. I'm surprised that you'd wanted to stay in the industry for 22 years if you really believe most everyone in it is greedy ;-) > >I believe as (you are) a VAR, I would understand you could be nervous about >loosing some income if CAE vendors removed their 'protection'. I'm not >saying you are nervous about loosing income, but that I would understand IF >you were. We're less nervous than the vendors themselves, because the "Added Value" part of "VAR" is all about building relationships and giving good support. In other words, our support is part of the product which people pay for, and so they want the paid-for product. > >Oh, and by the way, in the US, it is NOT illegal for me to do 'something' >to remove the hardware key. It would be illegal if I was using a pirated >copy, or sold a pirated copy for $$$. Legally, I can disassemble, reverse >engineer and/or modify any software (or hardware) as I see fit (despite >what the supposed licenses claim). That was made clear in Sega v Accolade. Similar here in UK, although you'd be in breach of some license agreements if you disassembled, but that's a contractual, not criminal issue. However, pirating is illegal, and so is supplying the information to help someone else to do this. -- David Pashley < ------------------------ < < < ---------- Email: david@fpga.demon.co.uk | Direct Insight Ltd < < < < > Tel: +44 1280 700262 | | < < < Fax: +44 1280 700577 | --------------------------- < ------------------------------------------Article: 9736
>The reason why NeoCAD became popular was superior quality of results >when compared with XACT. You could 95% utilize a 3090 and get 20% to 30% >better performance than XACT. You are right there, but then you are comparing Neocad (1993) with XACT (1993) and XACT back then was nowhere near as good as later versions. APR often could not fill more than about 60% of a 3064. >The FPGA Evaluator product, allowing you to compare *place-and-routed* >results for Xilinx, Actel, ALtera, Quicklogic and Lucent after an >overnight run was scary for the vendors, and a breath of fresh air for >FPGA users. NeoCAD was acquired within weeks of that product >announcement. Well, yes, this is what lots of people think, and doubtless it is true. Xilinx won't put it quite that way though, I am sure :) >Many people value the excellent tech. support that we and VARs in >general provide. Your anonymity does not lend credibility to your >attack. An observation, no attack. Also, all but two of your posts in this thread (based on my 10-day expiry setting) are anonymous too, in that they don't advertise who you work for. If I had noticed that you work for Direct Insight (a firm selling mainly pricey EDA s/w, IIRC) I would have put it differently, since I don't intend to wind someone up unless they deserve it. The argument comes down to the business model one wants to run. Having myself paid over $10k for my Xilinx-only FPGA kit, I too wish that Neocad had carried on. Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 9737
First off, one time programmables can stay 1 technology generation behind and still compete with the SRAM or Flash based solutions. The 32000 is a .6um technology and your comparing against a .5um 10k40. Second, from a performance perspective the SRAM based device cannot compete with an anti-fuse. It's much slower. Additionally a anti-fuse based part can use >95% of the logic and still route. This keeps a designer from buying more gates than he really needs. Third, Actel introducted a new product line last October that competes very well with the 6K and the Spartan. The problem with the 6K family is that only one member exists today. With Spartan, if you need a config prom, then you have to buy the expensive version with clock generation on board. Add the larger density, plus config prom, and Actel has a very attractive solution. And it's only one chip. Above and beyond that, we have a product called Silicon Explorer. This gives you the capability of looking at any two nets internally in real time. If those we not the nets causing the problem, within 5 seconds you can look at any other two nets in real time. This is like cutting off the top of the case, and being able to probe around the chip with a scope. There is no way this is not a cool feature to any deigner whose had to wait for a place and route to complete where he could look at nets he thinks are causing problems. Hope you choose the correct nets, or have plenty of pins. Yes, from a density point of view, we don't (today) have large (> 36K gates) density parts. There are many reasons to use Actel for a design. They are: 1) Speed. If you need high performance, we can do it. 2) Low power. Anti-fuses are passive components that disipate little power. 3) Tight integration. The only single chip solution to compete with Altera and Xilinx. Many, many more. Will Torgerson Actel CorporationArticle: 9738
sylvain dery wrote: > > Hi all! > > I have to design a Reed-Solomon encoder in VHDL for > a graduate university project. The semester is ending soon and > I think I took a bigger bite than I can chew! > So I'm looking for practical implementation of the Reed-Solomon > algorithm. > > Can anyone give me a hint? > > Thanks in advance! > SLY I have seen in the Xilinx Cores Solutions databook that there is a 3rd party that has developed a Reed-Soloman encoder. You might want to check that out.Article: 9739
You may want to look up the Xilinx web site ( www.xilinx.com ) and click on the application note: Synchronous and Asynchronous FIFOs, XAPP051. I wrote that 2 years ago, and it describes the fastest possible designs. If you are serious, I can also e-mail you an improvement that has not yet been published. The important question is: What speed, and are read and write asynchronous or do they have a common clock? At low speed ( below 30 MHz and with a common clock, the design becomes very simple and does not even need the dual-port RAM. At 70 MHz with asynchronous read and write, the design is more challenging, and generating appropriate FULL and EMPTY signals is tricky. That's what this app note is about. Peter Alfke, Xilinx Applications SAMIR KHERICHA wrote: > I was trying to build a fifo 512X8 on XC4020E and i have a macro of > 16X8 > fifo which has push and pop alongwith full, empty and last logic. I > have > thinking of different ways to cascade it. I would appreciate if > someone > could show me a smart idea to cascade it. > > samir > ------------------------------------------------------ > Samir Khericha > Graduate Research Assistant > Department Of Computer Engineering > Residence: > 2383 duncan drive > apt #8 > fairborn OH 45324 > PH No: 937-426-8076 > _______________________________________________________Article: 9740
You have have very good products for particular applications. But computing and HDLs are playing a big part in reconfigurable computing. ASIC/FPGAs are becoming soft and this is why SRAM based FPGAs are popular. It becomes very easy to re-itterate a design without having to replace the silicon. My personal opinion (and $.02 worth). -------------- Gareth Baron WTorger wrote: > First off, one time programmables can stay 1 technology generation behind and > still compete with the SRAM or Flash based solutions. The 32000 is a .6um > technology and your comparing against a .5um 10k40. > Second, from a performance perspective the SRAM based device cannot compete > with an anti-fuse. It's much slower. Additionally a anti-fuse based part can > use >95% of the logic and still route. This keeps a designer from buying more > gates than he really needs. > Third, Actel introducted a new product line last October that competes very > well with the 6K and the Spartan. The problem with the 6K family is that only > one member exists today. With Spartan, if you need a config prom, then you > have to buy the expensive version with clock generation on board. Add the > larger density, plus config prom, and Actel has a very attractive solution. > And it's only one chip. > Above and beyond that, we have a product called Silicon Explorer. This gives > you the capability of looking at any two nets internally in real time. If > those we not the nets causing the problem, within 5 seconds you can look at any > other two nets in real time. This is like cutting off the top of the case, and > being able to probe around the chip with a scope. There is no way this is not > a cool feature to any deigner whose had to wait for a place and route to > complete where he could look at nets he thinks are causing problems. Hope you > choose the correct nets, or have plenty of pins. > > Yes, from a density point of view, we don't (today) have large (> 36K gates) > density parts. > There are many reasons to use Actel for a design. > They are: > 1) Speed. If you need high performance, we can do it. > 2) Low power. Anti-fuses are passive components that disipate little power. > 3) Tight integration. The only single chip solution to compete with Altera and > Xilinx. > > Many, many more. > > Will Torgerson > Actel CorporationArticle: 9741
>I am doing a design I would like to keep in a 5K gate device. The >highest clock is 2Mhz, and I wil be wiggling maybe 70 lines. The device >will be burst processing and only will be on for perhaps 25% of the >time. There are perhaps 10 16 bit counters internal to the device. The >design will all be 3.3V > >What kind of power numbers can I expect from > >>>>ACTEL: 16.3 mW This is completly an estimate. If you use gated clocks it will be less. Understand, everyone will now come back with lower numbers, but Actel was the first to respond. We have also added a power calculator in our tool. If you have the Designer Software you can use the command line "c:\actel\bin\designer report_power:1" and get a good power consumption report of you design. We are that confident in out ability to win with low power. Phillips is the only competition, but they are no where near 5K gates. Will Torgerson Actel CorporationArticle: 9742
Joshua Schwartz wrote: > Hi Everyone, > I have two questions concerning one time programmables such as > Quicklogic and Actel. > > 1) Why do they seem to be lagging behind the SRAM based FPGAs so far > in > the number of available FLIP-FLOPs? Not counting using logic resources > as > latches the biggest of them seem only to have ~2500 flip-flops or so > in their > logic elements. Large antifuse devices have a very large number ( millions ) of antifuses, since abundant connectivity is one of the hallmarks of antifuse FPGAs. Each of these untestable antifuse sites must have a very controlled breakdown voltage, low enough so it can be programmed by the available voltage, and high enough so that it does not get programmed accidentally by the normal operating voltage across it. Guaranteeing that for millions of fuses is non-trivial.If only one fuse shorts accidentally, or if one fuse needed to program doesn't program, the device is worthless. This puts an upper limit on the realistic size of antifuse-based FPGAs. > 2) It also seems that they don't have the claimed savings in price. > I think an Altera 10k40 is around $90 or so (maybe even cheaper by > now). > > where as Actel had the following price which I grabbed from their web > site. > > Device Time Frame 100 pc Percent High Percent > Resale Reduction Volume Reduction > A32200DX-FPQ208C March 1 $176.00 48% $97.00 54% > 4Q97 $87.50 74% $47.60 77% > > It seems to me that $87.00 verses $90.00 is not much of a savings when > > you consider that the Altera > device is reprogrammable. And both Altera and Xilinx have very low > cost > FPGAs (spartan and flex6k) > that are around $10.00 - $20.00 for a 36k gate device. I'm I missing > something? Since they use so much > less silicon I would think the one time programmable would be much > less > expensive. So why aren't they? The area saving has often been overstated by not mentioning the overhead transistors required for doing the programming. Also, because of the need for relatively high programming voltages, the antifuse process is always some generations behind the more conventional logic process used for "SRAM-base" FPGAs. Especially the last year has seen Xilinx and Altera migrating very rapidly to smaller geometries. Xilinx now is in volume production with 0.25 micron, which makes the chips much smaller and cheaper. > > > I would go with the one time programmables only if I needed their > speed. I am not so sure about the speed advantage. I just finished the design of a frequency counter with 6-digit LCD display in an XC4002XL-09. It works at any frequency up to 421 MHz. I don't think antifuse devices are any faster. > But it suprises me that they are > so far behind in every other way it seems. If anyone can comment I'd > like to get a thread going to expose > the issues here a little more. Sorry if this is a rehash of something > that appears here a lot. It seems that it > is the kind of thing that would be talk about to the point of > annoyance > like "which is better VHDL or Verilog". > I hope I did not sound too commercial. But we at Xilinx have some hard-earned experience with antifuse technolgy. We developed a product family to the point of product introduction, then cancelled it because we found that our manufacturing energy was better spent on other things. Peter Alfke, Xilinx ApplicationsArticle: 9743
I have the Foundation Student Edition and I like it. I have not used any other vendors tools. It costs ~$65 at alt.bookstore Simon -------------------------------------------------------------------------------------------------------------- THIEBOLT Francois <thiebolt@irit.fr> wrote: >Hi, > >We're looking for a 'right' FPGA tools (near up to 8k gates) and i >wonder >what kind of FPGA would i use...Xilinx and their Foundation software >(along with VHDL) or buying tools from other company...? > >Any clue ? > >François. > >-- >------------------------------------------------------------- >THIEBOLT Francois \ You think your computer run too slow ? >UPS Toulouse III \ - Check nobody's asked for tea ! >thiebolt@irit.fr \ "The Hitchikers Guide to the Galaxy" D.Adams >------------------------------------------------------------- Opinions expressed herein are solely my own and may or may not reflect my opinion at this particular time or any other.Article: 9744
> > I'm surprised that you'd wanted to stay in the industry for 22 years if > you really believe most everyone in it is greedy ;-) I'm an eternal optimist ;-) I only use them as tools...and there are some really good tools out there...the product can be good, and the company greedy at the same time, right? > >Oh, and by the way, in the US, it is NOT illegal for me to do 'something' > >to remove the hardware key. It would be illegal if I was using a pirated > >copy, or sold a pirated copy for $$$. Legally, I can disassemble, reverse > >engineer and/or modify any software (or hardware) as I see fit (despite > >what the supposed licenses claim). That was made clear in Sega v Accolade. > > Similar here in UK, although you'd be in breach of some license > agreements if you disassembled, but that's a contractual, not criminal > issue. Just because someone has it in a license agreement, and you agree to it, doesn't mean it's enforceable. That, too, has been tried and tried here in the US... Again, it is what you do with the information (ie, disassembled code) that makes it legal or illegal. It is illegal to publish it, as that would be copyright infringement, it is illegal to copy it (use it in your own code) as that, too, would be copyright infringement...etc. BUT you CAN modify YOUR copy of the code until your little heart is content! > However, pirating is illegal, and so is supplying the information to > help someone else to do this. No, supplying the information for someone to do this is NOT illegal. If that were true, guns would be illegal, as well as all hand tools, as hand tools (as well as rocks) are used in breaking into houses, which is illegal.Article: 9745
Check out IBM's patent #4,486,739 on the 8B/10B code at their patent server. This should give you enough detail to implement it in the HDL of your choice. http://www.patents.ibm.com/cgi-bin/viewpat.cmd/4486739 Can anyone tell me what designs can use this without having to license the technology from IBM? I don't really want to get the lawyers involved! Patrick Mueller wrote: > > I am searching for a synthesizable 8B/10B Encoder/Decoder for a > FibreChannel Project. > Has anybody VHDL or AHDL code for that? > > Thanks > > Patrick Mueller > > email: no_spam_pbmuelle@stud.ee.ethz.ch ( remove no_spam_ )Article: 9746
rk wrote: > don: > : Do you have a problem with this? > : I have a valid license. It's the knuckleheads at Viewlogic that > : fail to live up to their end of the agreement. I have no problem > : with breaking the dongle under these circumstances. > > rk: > of course, while we're all in b*tch mode, a certain company producing CAE > software, say Brand 'V', has a marvelous policy with the dongle which > creates the following, beautiful situation. let's say you have two > machines, hypothetically speaking, both running software constrained to run > the package for Brand 'X' (pun intended, of course). Now, let's say, you > invest extra $ to have machine 2 run software for all brands, cause you > want to do one or two designs using brand 'A' fpga. now machine 2, > gloating with it's capability, does it thing, perhaps doing some work on a > brand 'X' fpga, helping out designer 1, and then sends the files back to > machine 1 and designer 1. the design, all for brand 'X', can no longer be > read on machine 1 with the brand 'X' constrained licence. why, because the > more powerful license on machine 2 'touched' the files. > > i'd say this qualifies as a pita, [ok, pain in the *ss], since after > investing dollars to upgrade one piece of software, two designers, both > licensed for Brand 'X', can no longer work on the same project, unless they > spend more $. now what to do with those useless dongles sitting in my desk > draw ... get out the hockey stick? > -- > -------------------------------------------------------------- > rk I had exactly this problem using Viewlogic in my last job. When it came time to buy FPGA design tools for my current posistion, I didn't even consider Viewlogic. I was also very negatively impressed with their tech support. Now that I am using the Orcad product, I feel that I made the right decision. Rick Collins redsp@writeme.comArticle: 9747
hi guys, here's a few comments, CONSTRUCTIVE & TECHNICAL comments. that means no flame wars, religious arguments, etc. GOT IT!?!?!?!?!?!?!?!?!?! :) ok, now back to our regularly scheduled program. i had a few things i was going to post anyways, i'll try to work them in here, keep a technical track (i hope). Rich K. _____________________________________________________ joshua: : > Hi Everyone, : > I have two questions concerning one time programmables such as Quicklogic and Actel. : > : > 1) Why do they seem to be lagging behind the SRAM based FPGAs so far in : > the number of available FLIP-FLOPs? Not counting using logic resources as : > latches the biggest of them seem only to have ~2500 flip-flops or so in their : > logic elements. peter: : Large antifuse devices have a very large number ( millions ) of : antifuses, since abundant connectivity is one of the hallmarks of : antifuse FPGAs. Each of these untestable antifuse sites must have a very : controlled breakdown voltage, low enough so it can be programmed by the : available voltage, and high enough so that it does not get programmed : accidentally by the normal operating voltage across it. Guaranteeing : that for millions of fuses is non-trivial.If only one fuse shorts : accidentally, or if one fuse needed to program doesn't program, the : device is worthless. This puts an upper limit on the realistic size of : antifuse-based FPGAs. rich k. i don't think that the manufacturers actually "guarantee" both sides of the equation. they MUST guarantee that there will be no conduction through normally unprogrammed, biased antifuses; if they don't, their field reliability will be poor and the product line will be worthless. my personal experience is that FPGA antifuse failure (their are other device types that use antifuses and that's a separate discussion), either opens or shorts, is not a major hazard. this is from programming lots of devices, running them in systems, investigating "field failures," and running numerous burn-ins and some accelerated life tests. also, the devices have undergone reliability tests and, for some device types, been qualified to QML standards produced on a hi-rel fab line. devices from some commercial fab lines have also been qualified to "Class S" [actually not full class s, but close enough for government work]. this is, by the nature of my job, based on experience with the actel ONO antifuse devices. i agree, pete, that this is not easy and some other manufacturers have not got the "recipe" quite right. published reliability data states that all ONO antifuses on a device is less than 10 FITs, not a bad number. personal experience is not inconsistent with that. btw, pete, what technology was the xilinx antifuse? as for antifuse count, published data indicates 112,000 antifuses for the 1010 [2,000 gate array gates] to 940,000 for the 14100 [10,000 gate array gates]. again, no gate counting wars, let's just say multiply by 2 to be more or less equivalent to xilinx/altera. note new gate counting on the 42mx line. [and if i use them, i get to tell my boss i doubled my design gate/hour rate]. based on reliability data and antifuse counts, increasing the size of the fpga, and assuming that antifuse count increases linearly with gate count, an "industry standard" 100,000 gate device would still yield decent field reliability numbers, a factor of 5 higher than what has been measured. this should not be a problem and currently high-rel, critical systems are built using many of these devices, forming the equivalent of a high gate count device. as an example, if i remember correctly, the mars pathfinder computer [remember the rover?] used 19 8,000 gate devices. the critical issue here for antifuse reliability was radiation, not electric stress, but that too is another story. now, they DO NOT have to guarantee that all devices pass the programming stage. we all know that [well, the elderly anyways] that programming bipolar and cmos fuse proms had less than 100% yield yet were qualified to high reliability. and fuses had their own set of problems but that, too, is another post. of course, if the yield is low, then you have to get a whole pile of those rma numbers and have lots of extra parts on hand. for production devices, my experience has been a programming yield of slightly over 98% [the word production is not a "weasle word" but i want to ensure accuracy and i do work with some experimental and prototypes]. failures are actually fairly rare on the programmer. but, as you state, the device manufacturer has to line things up to meet the following conditions: 1. they can program all antifuses that they want to (breakdown voltage not too high); 2. they don't program any antifuses inadvertently (breakdown voltage not too low and quality high); 3. they don't destroy anything else on chip, throwing high voltage around, say 20 volts or so for ONO (actel) and about 10 volts for M2M (utmc). just as an aside, the pico systems amorhphous silicon antifuses program at around 28 volts or so and are derated for 12 volt analog applications in their programmable substrate. meeting one and two is, where i would expect, the process engineers earn their bucks. personal observations and discussions with other engineers indicate that this is not a problem. as stated above, programming yield in the field is quite high, consistent with manufacturers posted numbers. also, with the exception for one "upgrade" having an incorrect algorithm, the devices are functional after programming with no problems every time, to the extent of my experience. there have been a few cases of incorrect timing models but that's a s/w model, not inherent to antifuse or fpga reliability. now, their are two cases for programmed reliability of the antifuse; programmed and unbiased programmed. quicklogic (gordon and wong) have two nice articles on this for their m2m amorphous silicon antifuse, as does utmc and actel, for examples. anyways, for the unprogrammed biased antifuse, there is an electric stress on the device, and it is normally shown in graphs for time dependent dielectric breakdown (tddb), with one axis being electric field strength and the other being time to breakdown. of course, with any large device, this stress condition is present, well, everywhere. transistor gates have bias across a thin gate oxide. some manufacturers post their gate oxide thicknesses for each process they use, others don't. when i asked xilinx, for instance, they said that it was proprietary. [ok, a gentle poke in the ribs. when i get time, we'll saw one in half and just measure it, it's not going to be a well kept secret]. anyways, each and every fet is, similar to an unprogrammed antifuse, a place where disaster can happen, and i recall trouble shooting gate oxide failures in old cmos srams. it does happen. and, from what i've seen, as the process scales, so does the gate oxide thickness. if the voltage doesn't scale with it, then electric field strength goes up and reliability goes down. of course, on the newer parts, the voltage is dropping, for exactly that reason. now, a question: for the newer technology parts, say 0.35 um and 0.25 um, what are the ic vendors doing to ensure reliable operation with 5V tolerant inputs? what is the electric field strength in the i/o cells and in the internal array where they are running 3.3 volts? and will this ultimately limit fpga size, getting say 10,000,000 gate oxides with no defects, as any single gate rupture will render the device faulty? anyways, this was a bit long-winded, but perhaps you could add a bit more about the limiting factor in antifuse fpga size. personally, i'm hitting the "10,000 gate wall" for space apps, the a14100a, smaller than the commercial limit which is about 5 times higher (in gate array gates). <snip a bunch of stuff about pricing> pete: : The area saving has often been overstated by not mentioning the overhead : transistors required for doing the programming. Also, because of the : need for relatively high programming voltages, the antifuse process is : always some generations behind the more conventional logic process used : for "SRAM-base" FPGAs. Especially the last year has seen Xilinx and : Altera migrating very rapidly to smaller geometries. Xilinx now is in : volume production with 0.25 micron, which makes the chips much smaller : and cheaper. rich k: basically agree here, the sram stuff seems to always be ahead in process, which makes a big difference. along with xilinx at 0.25 um, i believe the lucent people are there, too, to a certain extent [stu jump in here if my memory fails]. actel's smallest now is the 0.45 um 42mx series, which retains the ability to run the core at 5 volts. quicklogic, with their pasic 3, is running a 0.35 um process with their sea of modules architecture, a device i've been recently using. while the numbers tell you how small the die is, along with the great sea of modules cartoons, looking at a 0.35 um die really drives home the point; the ql3025 has basically "disappeared." joshua: : > I would go with the one time programmables only if I needed their speed. pete: : I am not so sure about the speed advantage. I just finished the design : of a frequency counter with 6-digit LCD display in an XC4002XL-09. It : works at any frequency up to 421 MHz. I don't think antifuse devices are : any faster. rich k: well, i didn't do a frequency counter, but i'm running a ql3025, 8-bit ripple counter, at > 500 MHz, so here's a data point. supply was 3.3 volts, room temp, and the device saw 35 krads(si) of radiation (it's not fun unless you really beat on them and rough 'em up, first). also, iirc, it's a standard speed grade device. the design was not optimized for anything, i just put down 8 flip-flops, wired them up, and let the p&r do it's thing on the default settings. just to balance things out, we've seen some very impressive speed numbers from the orca 2t series. joshua: : > But it suprises me that they are : > so far behind in every other way it seems. If anyone can comment I'd : > like to get a thread going to expose : > the issues here a little more. Sorry if this is a rehash of something : > that appears here a lot. It seems that it : > is the kind of thing that would be talk about to the point of annoyance : > like "which is better VHDL or Verilog". pete: : I hope I did not sound too commercial. But we at Xilinx have some : hard-earned experience with antifuse technolgy. We developed a product : family to the point of product introduction, then cancelled it because : we found that our manufacturing energy was better spent on other things. rich k: i use both reprogrammable and otp technologies, mostly, because of environment, otp. i don't think i agree that they (otp) are behind in "every other way." we had some previous threads about p&r time, quality of automagic p&r and the amount of floor planning/hand placement that is required, etc., etc. there are a LOT of issues with each type of device being better at some. overall, it probably depends on your requirements. but i would like to use bigger otp's <hint hint>. rich k <insert all standard and non-standard disclaimers here. and if i said anything wrong, remember there's "no controlling legal authority" against it, i hope>Article: 9748
don: : > : Do you have a problem with this? : > : I have a valid license. It's the knuckleheads at Viewlogic that : > : fail to live up to their end of the agreement. I have no problem : > : with breaking the dongle under these circumstances. rk: : > of course, while we're all in b*tch mode, a certain company producing CAE : > software, say Brand 'V', has a marvelous policy with the dongle which : > creates the following, beautiful situation. let's say you have two : > machines, hypothetically speaking, both running software constrained to run : > the package for Brand 'X' (pun intended, of course). Now, let's say, you : > invest extra $ to have machine 2 run software for all brands, cause you : > want to do one or two designs using brand 'A' fpga. now machine 2, : > gloating with it's capability, does it thing, perhaps doing some work on a : > brand 'X' fpga, helping out designer 1, and then sends the files back to : > machine 1 and designer 1. the design, all for brand 'X', can no longer be : > read on machine 1 with the brand 'X' constrained licence. why, because the : > more powerful license on machine 2 'touched' the files. : > : > i'd say this qualifies as a pita, [ok, pain in the *ss], since after : > investing dollars to upgrade one piece of software, two designers, both : > licensed for Brand 'X', can no longer work on the same project, unless they : > spend more $. now what to do with those useless dongles sitting in my desk : > draw ... get out the hockey stick? rick c.: : I had exactly this problem using Viewlogic in my last job. When it came time to : buy FPGA design tools for my current posistion, I didn't even consider : Viewlogic. I was also very negatively impressed with their tech support. Now : that I am using the Orcad product, I feel that I made the right decision. rk: how is the orcad simulation? do they still give you all those pcb netlisters, for no additional $? we gotta know! as for viewlogic tech support, i've had mixed results. some very good guys that just jump right on a problem and solve it. and some other experiences, too. -------------------------------------------------------------- rk "there's nothing like real data to screw up a great theory" - me (modified from original, slightly more colorful version) --------------------------------------------------------------Article: 9749
rich k: : well, i didn't do a frequency counter, but i'm running a ql3025, 8-bit : ripple counter, at > 500 MHz, so here's a data point. supply was 3.3 : volts, room temp, and the device saw 35 krads(si) of radiation (it's not : fun unless you really beat on them and rough 'em up, first). also, iirc, : it's a standard speed grade device. the design was not optimized for : anything, i just put down 8 flip-flops, wired them up, and let the p&r do : it's thing on the default settings. oops, left off the following: @ 500 MHz, < 35 mWatts, AFTER nuking.
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