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AHDL can refer to either Abel HDL or Altera HDL. The Altera HDL can only be used for Altera parts (at least that I know of) but Abel HDL can be used for almost any FPGAs, as the vendors offer translators. I used Abel for an Altera (and Xilinx) design(s) and it worked actually, very very well. Austin Franklin darkroom@ix.netcom.com P.S. Hell, throw away all this HDL crap, and just use XACT to program the pips, magic boxes and FMAPs...;-) Victor Levandovsky <vic@alpha.podol.khmelnitskiy.ua> wrote in article <357e5234.10988180@mu.icmp.lviv.ua>... > > Hi, > > Which main differencies, anvantages, etc. between this HDL`s? > Sincerelly, > Victor Levandovsky > PLD application instructor > Technological University of Podillia > Ukraine > > vic@NSalpha.podol.khmelnitskiy.ua > remove@NS.for.email.me >Article: 10751
> Currently, floorplanning support seems to be a bit light from Xilinx if > you're using the M1 tools. Or running under NT... AustinArticle: 10752
african@hol.gr wrote:
>
> Hi!
> I'm working on multiplier architectures and i'd like to know if it
> possible to generate the Wallace tree structure using only VHDL code, or
> a Wallace tree generator (written perhaps in C) has to be used?
> Does anyone know if there any Wallace tree VHDL models available ? Any
> Wallace tree generators ? Any related literature?
> If anyone has any information I wouLd appreciate it.
>
It is possible to generate a Wallace structure using only VHDL.
The solution I used was to generate a constant map with all units
in the structure and then use generate loops and instantiate
the appropriate component. It is not very effective if one need
a fast synthesis, but very useful as a generic unit for
simulation/synthesis.
I recommend to use a generator if you don't absolutely need to
create a generic unit.
A generator for several types of operations is found at:
http://grrr.catt.rmit.edu.au/~pihl/modgen/modgenexec.html
A great book on artihmetic algorithms is:
Computer Arithmetic Algorithms, Israel Koren
http://www.prenhall.com/books/esm_0131519522.html
THomas
=================================================================
Thomas Johansson, Electronics Systems, LiTH, Sweden
e-mail: thomasj@isy.liu.se
www: http://www.es.isy.liu.se/ ftp: ftp://ftp.isy.liu.se/
=================================================================
Article: 10753Greetings, Take a look at "Computer Arithmetic Algorithms" by Israel Koren. He has a chapter on high speed multiplication. I seem to remember doing a search at www.dejanews.com for wallace tree when I found reference to his book. If you do come across a wallace tree generator please let us know. Hand coding them is a real pain. I did mine in Verilog. Looks more like a netlist than behavioral code. regards Jerry English african@hol.gr wrote: > Hi! > I'm working on multiplier architectures and i'd like to know if it > possible to generate the Wallace tree structure using only VHDL code, or > a Wallace tree generator (written perhaps in C) has to be used? > Does anyone know if there any Wallace tree VHDL models available ? Any > Wallace tree generators ? Any related literature? > If anyone has any information I wouLd appreciate it. > > ThanksArticle: 10754
Thomas Johansson <thomasj@isy.liu.se> writes:
>african@hol.gr wrote:
>>
>> Hi!
>> I'm working on multiplier architectures and i'd like to know if it
>> possible to generate the Wallace tree structure using only VHDL code, or
>> a Wallace tree generator (written perhaps in C) has to be used?
>> Does anyone know if there any Wallace tree VHDL models available ? Any
>> Wallace tree generators ? Any related literature?
>> If anyone has any information I wouLd appreciate it.
>>
>It is possible to generate a Wallace structure using only VHDL.
>The solution I used was to generate a constant map with all units
>in the structure and then use generate loops and instantiate
>the appropriate component. It is not very effective if one need
>a fast synthesis, but very useful as a generic unit for
>simulation/synthesis.
>I recommend to use a generator if you don't absolutely need to
>create a generic unit.
>A generator for several types of operations is found at:
> http://grrr.catt.rmit.edu.au/~pihl/modgen/modgenexec.html
>A great book on artihmetic algorithms is:
> Computer Arithmetic Algorithms, Israel Koren
> http://www.prenhall.com/books/esm_0131519522.html
>THomas
>=================================================================
>Thomas Johansson, Electronics Systems, LiTH, Sweden
>e-mail: thomasj@isy.liu.se
>www: http://www.es.isy.liu.se/ ftp: ftp://ftp.isy.liu.se/
>=================================================================
A generator for optimized multipliers using Booth-Encoding and
Wallace-Trees to sum up the partial products can be found under
http://www.tu-chemnitz.de/~str/mak
The generator is implemented in C and generates netlists in VHDL,
BLIF or XNF (Xilinx only).
------------------------------------------------------------------------------
Dipl.-Ing. Robert Siegmund email:rsie@hrz.tu-chemnitz.de
Tech. Univ.of Chemnitz
Dpt. of Systems and Circuit Design
Chemnitz,Germany
------------------------------------------------------------------------------
Article: 10755In article <01bd98f0$ccc94f40$5870d6ce@drt1>, "Austin Franklin" <darkro9om@ix.netcom.com> wrote: > > AHDL can refer to either Abel HDL or Altera HDL. The Altera HDL can only > be used for Altera parts (at least that I know of) but Abel HDL can be used > for almost any FPGAs, as the vendors offer translators. > Wow, this is the first time I've ever seen anybody say that AHDL refers to Abel, and I've been using both for a long time. Altera has called their language AHDL since it was introduced. I do not miss writing Abel test vectors! My $0.02. Cheers, James Means -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 10756
In article <3586728A.54CDDAF0@planetc.com>, Jerry English <jenglish@planetc.com> wrote: > > Greetings, > Take a look at "Computer Arithmetic Algorithms" by Israel Koren. He has a > chapter > on high speed multiplication. I seem to remember doing a search at > www.dejanews.com > for wallace tree when I found reference to his book. If you do come across > a wallace tree > generator please let us know. Hand coding them is a real pain. I did mine in > Verilog. Looks > more like a netlist than behavioral code. > > regards > Jerry English > Has somebody found the difference between a hardware implementation and a software implementation? ;-) -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 10757
african@hol.gr wrote: > > Hi! > I'm working on multiplier architectures and i'd like to know if it > possible to generate the Wallace tree structure using only VHDL code, or > a Wallace tree generator (written perhaps in C) has to be used? > Does anyone know if there any Wallace tree VHDL models available ? Any > Wallace tree generators ? Any related literature? > If anyone has any information I wouLd appreciate it. > > Thanks While Wallace trees make for fast multipliers in other technologies, they are not always the best solution in an FPGA, especially if the FPGA has a fast carry chain available and you can live with a pipeline latency of a few clocks. The optimization of a wallace tree does not take into account the delays introduced by the limited routing in an FPGA. A faster and more compact multiplier is possible in Xilinx 4K using a partial products method similar to long hand multiplication. The easiest case to visualize (and often the easiest to implement) is the case where you use 2 bit by n bit partials. Each bit pair in one multiplicand generates a partial product equal to 0,1,2 or 3 times the other multiplicand (the msb for a 2'sc multiplier generates 0,1,-2 or -1 times). Each partial product multiplier can be reduced to a mux that selects 0,1,2 or 3 x. The 3 x input to the mux is just the multiplicand shifted and added to itself (this shift and add can be done once and supplied to all the muxes). The partials for each bit pair are shifted (by wiring) and added in a simple adder tree to obtain the product. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://users.ids.net/~randraka The Andraka Consulting Group is a digital hardware design firm specializing in high performance FPGA designs for digital signal processing, computing and control applications.Article: 10758
> > >-Jeremy > > > > > >PS: This is not spam. I have posted it to newsgroups that I have > > >found computer-related material in. Please do not criticize me for > > >that. And of course all those news groups exist to further your lame pyramid scheme. I forgot that usenet exists so you can try to make a cheap buck. I was under the false impression it was for people seeking/spreading knowledge. Go spam your ads somewhere else because you have nothing else to contribute. -Mat. -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 10759
jimmeans@my-dejanews.com wrote in article <6m67ph$mc4$1@nnrp1.dejanews.com>... > In article <01bd98f0$ccc94f40$5870d6ce@drt1>, > "Austin Franklin" <darkro9om@ix.netcom.com> wrote: > > > > AHDL can refer to either Abel HDL or Altera HDL. The Altera HDL can only > > be used for Altera parts (at least that I know of) but Abel HDL can be used > > for almost any FPGAs, as the vendors offer translators. > > > > Wow, this is the first time I've ever seen anybody say that AHDL refers to > Abel, and I've been using both for a long time. Altera has called their > language AHDL since it was introduced. I do not miss writing Abel test > vectors! There was a name transition period for Data OhNo! back around version 4. The buzz word HDL was being bantered about, and if you remember, it was just called 'Abel' before then, and was not referred to as 'an HDL'. Then, to accommodate the buzz word lovers (namely marketing), they started to call it 'Abel HDL and AHDL'. I loved those test vecotors, very easy and very fast unit delay simulation ;-) AustinArticle: 10760
Hi, I was wondering if anyone used VHDL testbench for Maxplus2 simulator? The idea is to simulate the design (written in RTL) with some other components such as SRAM and FIFO (modeled with behavioral VHDL). It will be convenient to write a VHDL testbench to instantiate all of these and simulate it. Is it possible to do with Altera's Maxplus2? How about Xilinx tools? Any suggestion is greatly appreciated. ----------------------- Louis Zhang lzhang@eecg.toronto.eduArticle: 10761
RAZ Semiconductors wrote: > > Call me I can source any board level component. > New or obsolete. > RAZ SEMICONDUCTORS > 6525 VANDEN ABEELE > ST.LAURENT QUEBEC > H4S 1S1 CANADA > 1-514-334-2447 TEL > 1-514-334-7794 FAX > dackman@razsemi.com You never answeres my request for WD37C65 chips. If you can't supply them, it would be good business to say so. Jerry -- If my address has "x" or "z" in it, remove them to reply. Everyone is entitled to an opinion; not all opinions deserve respect. ---------------------------------------------------------------------Article: 10762
Are you tryed to uninstall and reinstall Fundation, I have M.1 working fine with Win95B on my Thikpad Walter. J.Simmons wrote: > > Try calling the hotline, they might be able to help > 1-800-255-7778 > > s.timm wrote in message <35748A7B.879D5656@fh-westkueste.de>... > >I have a problem with Foundation 1.4 from Xilinx. > > > >I cant start the program. Every time messages of errors ocour if I try > >to start the program. The messages are different; missing device; > >PCM.EXE not found; differnt types of DLL have errors; ... > >My System is a Pentium 133; 64 MB RAM; HDD1 with 2GB and HDD2 with 12 GB > >(exlusive for the cad-system) > >The OS is WIN95B. > > > >I have insall the OS and the software more times and it dosent help. > > > > > >Has anyone a idea ? > > > >S. Timm > >Article: 10763
> > A generator for several types of operations is found at: > > http://grrr.catt.rmit.edu.au/~pihl/modgen/modgenexec.html > The link above may have expired. Try this link instead http://serpens.fysel.ntnu.no/pihl/ THomas ================================================================= Thomas Johansson, Electronics Systems, LiTH, Sweden phone: +46 13 284059 fax: +46 13 139282 e-mail: thomasj@isy.liu.se www: http://www.es.isy.liu.se/ ftp: ftp://ftp.isy.liu.se/ =================================================================Article: 10764
On 17 Jun 98 02:24:47 GMT, lzhang@eecg.toronto.edu (Louis Zhang) wrote: >Hi, > >I was wondering if anyone used VHDL testbench >for Maxplus2 simulator? The idea is to simulate >the design (written in RTL) with some other >components such as SRAM and FIFO (modeled with >behavioral VHDL). It will be convenient to write >a VHDL testbench to instantiate all of these and >simulate it. Is it possible to do with Altera's >Maxplus2? How about Xilinx tools? > >Any suggestion is greatly appreciated. > >----------------------- >Louis Zhang >lzhang@eecg.toronto.edu > You can generate VHDL netlist with SDF file (menu Interface in MAX+PLUS II) and than simulate it in VHDL Simulator using Test Bench. (i.e. in Aldec's Active-VHDL simulator - www.aldec.com) Adam Biniszkiewicz Technical Univeristy of Zielona Góra, Poland e-mail: A.Biniszkiewicz@pz.zgora.plArticle: 10765
Jerry Avins wrote: > > RAZ Semiconductors wrote: > > > > Call me I can source any board level component. > > New or obsolete. > > RAZ SEMICONDUCTORS > > 6525 VANDEN ABEELE > > ST.LAURENT QUEBEC > > H4S 1S1 CANADA > > 1-514-334-2447 TEL > > 1-514-334-7794 FAX > > dackman@razsemi.com > You never answeres my request for WD37C65 chips. If you can't supply > them, it would be good business to say so. > > Jerry > -- > If my address has "x" or "z" in it, remove them to reply. > > Everyone is entitled to an opinion; not all opinions deserve respect. > --------------------------------------------------------------------- Yes I can get these for you no problem.... They are 2.50 each sorry aboout the delay I did not remove the "z" from your e-mail address and I did not respond to the newsgroup the first time. thanks dave -- RAZ SEMICONDUCTORS 6525 VANDEN ABEELE ST.LAURENT QUEBEC H4S 1S1 CANADA 1-514-334-2447 TEL 1-514-334-7794 FAX dackman@razsemi.comArticle: 10766
Hi, I am evaluating Xilinx FPGAs (Spartan XCS40XL-4 and XC4020XL-2). In this devices I need a 128x17Bit dualport fifo that runs at 62.5MHz. Xilinx says, that this would not run with this speedgrades.... Is it possible, that a interleaved dualport-fifo, implemented with single port Memorys could reach that speed? And how many CLBs would be used? Thanks Patrick ============================================================ Supercomputing Systems AG email: mueller@scs.ch Patrick Müller www: http://www.scs.ch Technoparkstrasse 1 phone: ++41 (0)1 445 16 09 CH-8005 Zurich fax: ++41 (0)1 445 16 10 ============================================================Article: 10767
I am hoping you can help me. I was scanning through the various news groups and came across a thread with your email. I am a technical recruiter in the New England area specializing in Hardware Engineering. I have 23 open reqs for ASIC designers and 35 companies looking for board level design engineers. Primarily in the Communications and Networking industries. Salaries $62K-107K). The positions exist in companies ranging from well funded START-UP's offering EQUITY, to more established companies (offering extra vacation time, flex hours, tuition reimbursement, great benefits, etc.) In all cases relocation, if necessary will not be a problem. I also have several openingings in the SF bay area. The need is acute and immediate. If you have any personal interest in working in the greater Boston, MA area (or CA), or if you know some one with a strong HW design background, I am certain I can be of assistance. These are full-time positions with AGGRESSIVE salaries ($62K-107K). Please forward a resume here and I will follow-up with you in 24 hours or less. Thomas P. Missert email: thomasm@net1plus.com Senior Recruiter Prostart Recruiting Resources Inc. 89 Stiles Road Suite 201 phone: 603-893-7772 xt35 Salem, NH 03079 fax: 603-893-7704 ProStart and client companies are Equal Opportunity Employers. All qualified applicants will be considered. Unless otherwise indicated all candidates must be citizens or permanent residents of the United States.Article: 10768
Does anybody know how much faster a SUN ultra-60 places and routes vs a 400 MHz PC? Frank Wallce Naval Surface Warfare Center -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 10769
J.Simmons wrote: > > The easiest way to reduce the archive size is to delete every VER and > REV that you have impemented/placed and routed. This will leave you > w/ all design entry stuff. > ( I do this all of the time) > By doing this you can reduce a 5 + meg file to ~ 1Meg, easy. > > email me directly if you need additional info; I don't check this NG > that often. > > Jeff > > Alexander Sherstuk wrote in message > <08210BF6F78BD111AAD80000F8009FD6BCE8CB@NS.amsd.com>... > > Hi ALL, > > The problem, which I am trying to solve - how to keep > reasonable size of an archive for the LCA design created > with > XILINX Foundation M1.4. Just ignore the Xilinx archive, junk the VER & REV stuff & put all the text files under RCS. Doesn't work for schematics but that's a problem with schematics. _________________________________________________________________________ Dr. Richard Filipkiewicz phone: +44 171 700 3301 Algorithmics Ltd. fax: +44 171 700 3400 3 Drayton Park email: rick@algor.co.uk London N5 1NU EnglandArticle: 10770
Subject: ANNOUNCE: FPGA design with FPGA Express - UK Seminars From June 19th to July 1st, Direct Insight are holding a series of seminars across the UK, showcasing the Viewlogic Systems EDA tools. Topics include: FPGA Design with FPGA Express 2.0 and Intelliflow There are both VHDL and Verilog-oriented versions of this seminar. For further details: http://www.edasource.com mail to: seminars@edasource.com or call 01280 700262Article: 10771
All: I am trying to get ahold of VCC - interested in getting more specific information (available OSes, etc) about the H.O.T II development system... Unfortunately, all of my email messages to vcc.com seem to be falling into a 'bit bucket'. I know that messages from vcc can get to my system from the outside - Steve Casselman sent me a message a while ago - but I'm not sure if mine are making it anywhere. Is there a phone number where vcc can be reached? And could someone from VCC ping me when they get this message (I have CC'ed it to info@vcc.com and sc@vcc.com ) so I can make sure that I am getting through and so I can possibly buy it? Thanks much, Ed -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 10772
Are there any good books which would help in predicting how many CLB's a particular code in vhdl will take....I assume that's quite far is there book or means to determine how much logic a particular statement in vhdl will take and which is registered and which is non registered. samir ------------------------------------------------------ Samir Khericha Graduate Research Assistant Department Of Computer Engineering Residence: 2383 duncan drive apt #8 fairborn OH 45324 PH No: 937-426-8076 _______________________________________________________Article: 10773
Pardon me if I am asking a dumb question, but is there a version of RCS which runs under windows? I am running windows 95 and if there is a version of any freeware VCS I would love to have it. I thought that RCS was only for Unix platforms. Rick Filipkewicz wrote: > > J.Simmons wrote: > > > > The easiest way to reduce the archive size is to delete every VER and > > REV that you have impemented/placed and routed. This will leave you > > w/ all design entry stuff. > > ( I do this all of the time) > > By doing this you can reduce a 5 + meg file to ~ 1Meg, easy. > > > > email me directly if you need additional info; I don't check this NG > > that often. > > > > Jeff > > > > Alexander Sherstuk wrote in message > > <08210BF6F78BD111AAD80000F8009FD6BCE8CB@NS.amsd.com>... > > > > Hi ALL, > > > > The problem, which I am trying to solve - how to keep > > reasonable size of an archive for the LCA design created > > with > > XILINX Foundation M1.4. > > Just ignore the Xilinx archive, junk the VER & REV stuff & put all the > text files under RCS. Doesn't work for schematics but that's a problem > with schematics. > > _________________________________________________________________________ > > Dr. Richard Filipkiewicz phone: +44 171 700 3301 > Algorithmics Ltd. fax: +44 171 700 3400 > 3 Drayton Park email: rick@algor.co.uk > London N5 1NU > England -- Rick Collins rickman@XYwriteme.com remove the XY to email me.Article: 10774
Hello I don't think Altera will provide tools for testbench nor Xilinx's Foundation. It is very inconvenient to replace the RAM with ROM and synthesis each time to get the result with Xilinix's Foundation. I used ModelTech's V-system simulator to do testbench and the performance is excellent! Try http://www.model.com Leslie Yip In article <Pine.GSO.3.96.980616221936.15842A-100000@ecl.eecg.toronto.edu>, lzhang@eecg.toronto.edu (Louis Zhang) wrote: > > Hi, > > I was wondering if anyone used VHDL testbench > for Maxplus2 simulator? The idea is to simulate > the design (written in RTL) with some other > components such as SRAM and FIFO (modeled with > behavioral VHDL). It will be convenient to write > a VHDL testbench to instantiate all of these and > simulate it. Is it possible to do with Altera's > Maxplus2? How about Xilinx tools? > > Any suggestion is greatly appreciated. > > ----------------------- > Louis Zhang > lzhang@eecg.toronto.edu > > -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreading
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