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Threads Starting Jan 2003

51098: 03/01/01: Steve Hurlock: bitfile back to ncd?
51099: 03/01/01: Liao Jirong: Any Xilinx Design Language(.xdl) document?
    51102: 03/01/01: Nicholas C. Weaver: Re: Any Xilinx Design Language(.xdl) document?
        51107: 03/01/02: Liao Jirong: Any Xilinx Design Language(.xdl) document?
            51119: 03/01/02: Nicholas C. Weaver: Re: Any Xilinx Design Language(.xdl) document?
                51125: 03/01/02: Steve Casselman: Re: Any Xilinx Design Language(.xdl) document?
51106: 03/01/01: Jeff: Question about HDL bencher (Xilinx) from newbie?
    51124: 03/01/02: Chen Wei Tseng: Re: Question about HDL bencher (Xilinx) from newbie?
        51181: 03/01/05: Jeff: Re: Question about HDL bencher (Xilinx) from newbie?
51121: 03/01/02: Sudip Saha: quartus-bus problem
    51129: 03/01/03: Subroto Datta: Re: quartus-bus problem
51122: 03/01/02: Prashant: Latch inferring : Async OR Sync ?
    51131: 03/01/02: RANGA REDDY: Re: Latch inferring : Async OR Sync ?
        51136: 03/01/03: Prashant: Re: Latch inferring : Async OR Sync ?
    51133: 03/01/03: Alan Fitch: Re: Latch inferring : Async OR Sync ?
    51190: 03/01/06: Symon: Re: Latch inferring : Async OR Sync ?
        53832: 03/03/25: Stan Lackey: Re: Latch inferring : Async OR Sync ?
51127: 03/01/02: Peter Alfke: Re: Running 2 inter related programs on the FPGA
    51147: 03/01/03: Mike Treseler: Re: Running 2 inter related programs on the FPGA
        51148: 03/01/03: Peter Alfke: Re: Running 2 inter related programs on the FPGA
            51161: 03/01/04: Stevenson: Re: Running 2 inter related programs on the FPGA
    51156: 03/01/04: Javier =?iso-8859-1?Q?Fern=E1ndez?=: Re: Running 2 inter related programs on the FPGA
51134: 03/01/03: Markus Walter: Alternative to theXilinx XC4005E
    51138: 03/01/03: rickman: Re: Alternative to theXilinx XC4005E
    51140: 03/01/03: Peter Alfke: Re: Alternative to theXilinx XC4005E
51137: 03/01/03: Cavailles Eric: Latch edge sensitive on data & RESET
    51158: 03/01/04: Stan Lackey: Re: Latch edge sensitive on data & RESET
51153: 03/01/04: Charlie Root: xst adding rams?
51154: 03/01/04: Kevin Yeoh: Warnings in FPGA...
    51197: 03/01/06: Joe Frese: Re: Warnings in FPGA...
51157: 03/01/04: chris: How can you tell if your clock signals are on the clock net?
    51166: 03/01/04: Phil Hays: Re: How can you tell if your clock signals are on the clock net?
    51168: 03/01/04: john jakson: Re: How can you tell if your clock signals are on the clock net?
    51171: 03/01/05: S. Ramirez: Re: How can you tell if your clock signals are on the clock net?
51159: 03/01/04: Sumanth Donthi: Dynamic Reconfiguration
    51164: 03/01/04: Rene Tschaggelar: Re: Dynamic Reconfiguration
    51170: 03/01/04: Peter Alfke: Re: Dynamic Reconfiguration
51162: 03/01/04: Masoud Naderi: HDMP-1032/34 Design experinces, hints and so
51163: 03/01/04: Jason Berringer: conversions and some assistance please
    51165: 03/01/04: dave garnett: Re: conversions and some assistance please
    51174: 03/01/05: Ralf Hildebrandt: Re: conversions and some assistance please
    51285: 03/01/09: Jason Berringer: Re: conversions and some assistance please
    51286: 03/01/10: Jim Granville: Re: conversions and some assistance please
    51305: 03/01/10: Aurash Lazarut: Re: conversions and some assistance please
51167: 03/01/04: Talal: place and route problem
    51179: 03/01/05: Talal: Re: place and route problem
51172: 03/01/04: Sumanth Donthi: reconfiguration times
    51173: 03/01/05: Tony M: Re: reconfiguration times
        51175: 03/01/05: Tony M: Re: reconfiguration times
        51177: 03/01/05: Sumanth Donthi: Re: reconfiguration times
            51178: 03/01/05: Tony M: Re: reconfiguration times
51182: 03/01/05: David Buckley: Xilinx 5202 peripheral mode configuration problem
    51371: 03/01/12: David Buckley: Re: Xilinx 5202 peripheral mode configuration problem
51183: 03/01/06: 123: help for MAXPLUS2!
    51186: 03/01/06: Rene Tschaggelar: Re: help for MAXPLUS2!
        51242: 03/01/07: siriuswmx: Re: help for MAXPLUS2!
51187: 03/01/06: Brendan Lynskey: Contracting in the UK
    51188: 03/01/06: Mike Harrison: Re: Contracting in the UK
        51191: 03/01/06: Nial Stewart: Re: Contracting in the UK
    51199: 03/01/06: Andy Rushton: Re: Contracting in the UK
        51202: 03/01/06: Nial Stewart: Re: Contracting in the UK
51192: 03/01/06: valentin tihomirov: asynchronous inputs
    51198: 03/01/06: Peter Alfke: Re: asynchronous inputs
    51203: 03/01/06: Nial Stewart: Re: asynchronous inputs
    51205: 03/01/06: Georgi Beloev: Re: asynchronous inputs
    51208: 03/01/06: Richard Iachetta: Re: asynchronous inputs
    51221: 03/01/07: Oggie: Re: asynchronous inputs
        51223: 03/01/07: Hal Murray: Re: asynchronous inputs
    51247: 03/01/08: valentin tihomirov: Re: asynchronous inputs
51194: 03/01/06: Markus Meng: SPI programming through the pc parallel port
51195: 03/01/06: Clyde R. Shappee: Constraining a purely combinatorial logic path
    51200: 03/01/06: rickman: Re: Constraining a purely combinatorial logic path
        51204: 03/01/06: Clyde R. Shappee: Re: Constraining a purely combinatorial logic path
            51211: 03/01/06: rickman: Re: Constraining a purely combinatorial logic path
                51213: 03/01/06: Clyde R. Shappee: Re: Constraining a purely combinatorial logic path
                    51218: 03/01/07: Ray Andraka: Re: Constraining a purely combinatorial logic path
                    51224: 03/01/07: rickman: Re: Constraining a purely combinatorial logic path
                        51230: 03/01/07: Clyde R. Shappee: Re: Constraining a purely combinatorial logic path
                            51232: 03/01/07: rickman: Re: Constraining a purely combinatorial logic path
    51206: 03/01/06: Chen Wei Tseng: Re: Constraining a purely combinatorial logic path
    51207: 03/01/06: Chen Wei Tseng: Re: Constraining a purely combinatorial logic path
        51212: 03/01/06: Clyde R. Shappee: Re: Constraining a purely combinatorial logic path
            51220: 03/01/07: Chen Wei Tseng: Re: Constraining a purely combinatorial logic path
51210: 03/01/07: jimmy: Help for LeonardoSpectrum LS2002d_22
51214: 03/01/07: David: Co-simulation of Spice and Vhdl
    51215: 03/01/07: Allan Herriman: Re: Co-simulation of Spice and Vhdl
        51222: 03/01/07: Uncle Noah: Re: Co-simulation of Spice and Vhdl
            51235: 03/01/07: David: Re: Co-simulation of Spice and Vhdl
                51236: 03/01/08: Jim Granville: Re: Co-simulation of Spice and Vhdl
                    51241: 03/01/07: David: Re: Co-simulation of Spice and Vhdl
51217: 03/01/07: Petter Gustad: Stratix IOE "Input Pin to Input Register Delay"
    51340: 03/01/10: Greg Steinke: Re: Stratix IOE "Input Pin to Input Register Delay"
        51414: 03/01/13: Petter Gustad: Re: Stratix IOE "Input Pin to Input Register Delay"
51226: 03/01/07: name: Running Synplify under Windows XP
51227: 03/01/07: Rah: Spartan II:Bidirectional IO interfacing 5V CMOS ?
    51231: 03/01/07: Austin Lesea: Re: Spartan II:Bidirectional IO interfacing 5V CMOS ?
51229: 03/01/07: Rene Tschaggelar: Bug in Quartus2 Web 2.2
    51239: 03/01/08: Subroto Datta: Re: Bug in Quartus2 Web 2.2
        51240: 03/01/08: Rene Tschaggelar: Re: Bug in Quartus2 Web 2.2
            51250: 03/01/08: Austin Lesea: Re: Bug in Quartus2 Web 2.2
                51252: 03/01/08: Rene Tschaggelar: Re: Bug in Quartus2 Web 2.2
                    51254: 03/01/08: Austin Lesea: Re: Bug in Quartus2 Web 2.2
                        51265: 03/01/09: Rene Tschaggelar: Re: Bug in Quartus2 Web 2.2
                    51337: 03/01/11: Russell: Re: Bug in Quartus2 Web 2.2
                        51376: 03/01/12: Rene Tschaggelar: Re: Bug in Quartus2 Web 2.2
                51409: 03/01/13: Matjaz Finc: Re: Bug in Quartus2 Web 2.2
                    51592: 03/01/16: <nospam@aol.com>: Re: Bug in Quartus2 Web 2.2
                        51623: 03/01/17: Karl de Boois: Re: Bug in Quartus2 Web 2.2
    51296: 03/01/10: Subroto Datta: Re: Bug in Quartus2 Web 2.2
51234: 03/01/08: fb: USB OPENCORE IP usage
    51238: 03/01/08: Muzaffer Kal: Re: USB OPENCORE IP usage
        51243: 03/01/08: Frederic Bastenaire: Re: USB OPENCORE IP usage
            51249: 03/01/08: Caleb Hess: Re: USB OPENCORE IP usage
                51263: 03/01/09: Thorsten Trenz: Re: USB OPENCORE IP usage
                    51274: 03/01/09: Frederic Bastenaire: Re: USB OPENCORE IP usage
                        51278: 03/01/09: Caleb Hess: Re: USB OPENCORE IP usage
                            51308: 03/01/10: Frederic Bastenaire: Re: USB OPENCORE IP usage
                                51311: 03/01/10: Caleb Hess: Re: USB OPENCORE IP usage
                                    51345: 03/01/11: Frederic Bastenaire: Re: USB OPENCORE IP usage
                    51300: 03/01/10: Rudolf Usselmann: Re: USB OPENCORE IP usage
                        51347: 03/01/11: Frederic Bastenaire: Re: USB OPENCORE IP usage
                            51403: 03/01/13: Thorsten Trenz: Re: USB OPENCORE IP usage
51244: 03/01/08: tk: Newbie question
    51245: 03/01/08: Nial Stewart: Re: Newbie question
        51248: 03/01/09: tk: Re: Newbie question
    51253: 03/01/08: Florin Franovici: Re: Newbie question
51246: 03/01/08: Nagaraj: internal nets
    51356: 03/01/11: Gilad Cohen: Re: internal nets
51255: 03/01/08: needhelp: 4-bit excess-3 counter with parallel load
    51257: 03/01/09: John_H: Re: 4-bit excess-3 counter with parallel load
        51268: 03/01/09: rickman: Re: 4-bit excess-3 counter with parallel load
    51258: 03/01/08: Peter Alfke: Re: 4-bit excess-3 counter with parallel load
51259: 03/01/08: Dar Shan: Small outline FPGA/PLD with differential LVPECL capability
    51306: 03/01/10: Neeraj Varma: Re: Small outline FPGA/PLD with differential LVPECL capability
51260: 03/01/08: siriuswmx: can maxplusII use the result produced by other synthesize tool ,for axample synplify ?
    51262: 03/01/09: Fredrik: Re: can maxplusII use the result produced by other synthesize tool ,for axample synplify ?
51261: 03/01/09: Noddy: External RAM...
    51266: 03/01/09: Dmitri Katchalov: Re: External RAM...
        51279: 03/01/09: Marlboro: Re: External RAM...
        51324: 03/01/10: jetmarc: Re: External RAM...
    51269: 03/01/09: Marc Randolph: Re: External RAM...
        51280: 03/01/09: Marc Baker: Re: External RAM...
51264: 03/01/09: Itsaso Zuazua: XILINX ISE + ACTIVE-HDL design flow, HELP PLEASE!!!
    51270: 03/01/09: Tullio Grassi: Re: XILINX ISE + ACTIVE-HDL design flow, HELP PLEASE!!!
        51312: 03/01/10: Tullio Grassi: Re: XILINX ISE + ACTIVE-HDL design flow, HELP PLEASE!!!
51267: 03/01/09: Alon Z: In-Rush current in Stratix device
    51271: 03/01/09: Rene Tschaggelar: Re: In-Rush current in Stratix device
        51338: 03/01/10: Greg Steinke: Re: In-Rush current in Stratix device
            51372: 03/01/12: Rene Tschaggelar: Re: In-Rush current in Stratix device
51273: 03/01/09: Jon Jacox: NIOS - first attempt
    51315: 03/01/10: crob: Re: NIOS - first attempt
        51322: 03/01/10: Jon Jacox: Re: NIOS - first attempt
51275: 03/01/09: Mike D: Xilinx 5.1i Map question
    51290: 03/01/10: Ray Andraka: Re: Xilinx 5.1i Map question
51276: 03/01/09: Kuan Zhou: Power usage of CLOCK in FPGA
    51281: 03/01/09: Peter Alfke: Re: Power usage of CLOCK in FPGA
        51294: 03/01/09: Kuan Zhou: Re: Power usage of CLOCK in FPGA
    51301: 03/01/10: Thomas Stanka: Re: Power usage of CLOCK in FPGA
        51309: 03/01/10: Austin Lesea: Re: Power usage of CLOCK in FPGA
            51456: 03/01/14: Brendan Cullen: Re: Power usage of CLOCK in FPGA
        51321: 03/01/10: Peter Alfke: Re: Power usage of CLOCK in FPGA
            51333: 03/01/10: Tim: Re: Power usage of CLOCK in FPGA
51277: 03/01/09: David: Student development board
    51302: 03/01/10: Rene Tschaggelar: Re: Student development board
        51318: 03/01/10: Austin Lesea: Re: Student development board
            51515: 03/01/15: geeko: Re: Student development board
                51522: 03/01/15: Austin Lesea: Re: Student development board
    51367: 03/01/12: Alex Gibson: Re: Student development board
        51544: 03/01/16: Frederic Bastenaire: Re: Student development board
    51591: 03/01/16: Will: Re: Student development board
        51600: 03/01/16: Will: Re: Student development board
            51602: 03/01/17: geeko: Re: Student development board
                51660: 03/01/17: Will: Re: Student development board
                    51672: 03/01/18: Kevin Brace: Re: Student development board
51282: 03/01/09: tbiggs: Virtex-II Pro misfire?
    51283: 03/01/09: Peter Alfke: Re: Virtex-II Pro misfire?
        51284: 03/01/10: Tim: Re: Virtex-II Pro misfire?
            51287: 03/01/10: Nicholas C. Weaver: Re: Virtex-II Pro misfire?
            51288: 03/01/10: Steve Casselman: Re: Virtex-II Pro misfire?
                51289: 03/01/10: Jim Granville: Re: Virtex-II Pro misfire?
                    51291: 03/01/10: Nicholas C. Weaver: Re: Virtex-II Pro misfire?
                        51299: 03/01/10: Hal Murray: Re: Virtex-II Pro misfire?
                            51319: 03/01/10: Peter Alfke: Re: Virtex-II Pro misfire?
                                51326: 03/01/11: Jim Granville: Re: Virtex-II Pro misfire?
                                    51341: 03/01/11: Nicholas C. Weaver: Re: Virtex-II Pro misfire?
                                51399: 03/01/12: Valeri Serebrianski: Re: Virtex-II Pro misfire?
                                    51423: 03/01/13: Peter Alfke: Re: Virtex-II Pro misfire?
                            51320: 03/01/10: Austin Lesea: Re: Virtex-II Pro misfire?
                    51292: 03/01/10: Steve Casselman: Re: Virtex-II Pro misfire?
                        51314: 03/01/10: tbiggs: Re: Virtex-II Pro misfire?
                            51316: 03/01/10: Hal Murray: Re: Virtex-II Pro misfire?
                            51327: 03/01/11: Jim Granville: Re: Virtex-II Pro misfire?
                                51331: 03/01/10: Peter Alfke: Re: Virtex-II Pro misfire?
                                    51332: 03/01/11: Jim Granville: Re: Virtex-II Pro misfire?
                                        51334: 03/01/10: Peter Alfke: Re: Virtex-II Pro misfire?
                                            51335: 03/01/11: Jim Granville: Re: Virtex-II Pro misfire?
                                                51343: 03/01/10: john jakson: Re: Virtex-II Pro misfire?
                                                    51366: 03/01/12: Nicholas C. Weaver: Re: Virtex-II Pro misfire?
                                                        51394: 03/01/12: john jakson: Re: Virtex-II Pro misfire?
                            51437: 03/01/13: Nicholas C. Weaver: Re: Virtex-II Pro misfire?
51297: 03/01/10: Dziadek: Spartan-2 reset: sync or async?
    51298: 03/01/10: Hal Murray: Re: Spartan-2 reset: sync or async?
    51313: 03/01/10: John_H: Re: Spartan-2 reset: sync or async?
    51362: 03/01/11: Rob Finch: Re: Spartan-2 reset: sync or async?
51304: 03/01/10: astonish: typedef ram in Handel-C
    51353: 03/01/11: Steffan Westcott: Re: typedef ram in Handel-C
51307: 03/01/10: Thorsten Bunte: DLL/PLL with global clock net
    51310: 03/01/10: Austin Lesea: Re: DLL/PLL with global clock net
        51401: 03/01/13: Thorsten Bunte: Re: DLL/PLL with global clock net
            51405: 03/01/13: Uwe Bonnes: Re: DLL/PLL with global clock net
                51415: 03/01/13: Marc Randolph: Re: DLL/PLL with global clock net
                    51439: 03/01/13: Thorsten Bunte: Re: DLL/PLL with global clock net
51317: 03/01/10: Prashant: Asynchronous RAM problems
    51323: 03/01/10: rickman: Re: Asynchronous RAM problems
        51368: 03/01/12: Dmitri Katchalov: Re: Asynchronous RAM problems
            51441: 03/01/13: rickman: Re: Asynchronous RAM problems
        51419: 03/01/13: Prashant: Re: Asynchronous RAM problems
    51359: 03/01/11: Rob Finch: Re: Asynchronous RAM problems
51328: 03/01/10: Robert S. Grimes: Generating a 4x Clock using DLLs with Spartan-II
    51346: 03/01/11: Brian Drummond: Re: Generating a 4x Clock using DLLs with Spartan-II
        51350: 03/01/11: Robert S. Grimes: Re: Generating a 4x Clock using DLLs with Spartan-II
51336: 03/01/10: Theron Hicks: ESD question on Spartan2e series inputs?
51339: 03/01/10: Bob Fischer: Interfacing to a PC using EPP parallel port
    51416: 03/01/13: Iwo Mergler: Re: Interfacing to a PC using EPP parallel port
    52066: 03/01/30: Ernest Jamro: Re: Interfacing to a PC using EPP parallel port
        52143: 03/02/02: Bob Fischer: Re: Interfacing to a PC using EPP parallel port
        52349: 03/02/07: Blake: Re: Interfacing to a PC using EPP parallel port
        52350: 03/02/07: Blake: Re: Interfacing to a PC using EPP parallel port
51342: 03/01/10: Duy K Do: MicroBlaze MDK2.2 opb_timer
    51361: 03/01/11: Raj Kumar Nagarajan: Re: MicroBlaze MDK2.2 opb_timer
51348: 03/01/11: arvind: Help for Generating Video Clock synchronous to Hsync of the Video..........
    51352: 03/01/11: Falk Brunner: Re: Help for Generating Video Clock synchronous to Hsync of the Video..........
    51355: 03/01/12: Jim Granville: Re: Help for Generating Video Clock synchronous to Hsync of the Video..........
    51411: 03/01/13: Caleb Hess: Re: Help for Generating Video Clock synchronous to Hsync of the Video..........
        51412: 03/01/13: Caleb Hess: Re: Help for Generating Video Clock synchronous to Hsync of the Video..........
            51461: 03/01/14: Marlboro: Re: Help for Generating Video Clock synchronous to Hsync of the Video..........
51349: 03/01/11: B. Joshua Rosen: Has anyone used the SerDes on the VirtexIIP?
51351: 03/01/11: Antonio Di Stefano: Partial reconfiguration
    51357: 03/01/11: Steve Casselman: Re: Partial reconfiguration
51358: 03/01/11: Emil Wennman: MPEG ASIC
    51767: 03/01/21: sudip saha: Re: MPEG ASIC
51360: 03/01/12: TigerMole: Bidirectional Digital Switch in CPLD ?
    51417: 03/01/13: Mikeandmax: Re: Bidirectional Digital Switch in CPLD ?
        51424: 03/01/13: John_H: Re: Bidirectional Digital Switch in CPLD ?
        51436: 03/01/13: TigerMole: Re: Bidirectional Digital Switch in CPLD ?
            51473: 03/01/14: TigerMole: Re: Bidirectional Digital Switch in CPLD ?
51363: 03/01/12: 2Penny: from ABEL/PLDs to VHDL&VeriLog/FPGAs
    51421: 03/01/13: Barry Brown: Re: from ABEL/PLDs to VHDL&VeriLog/FPGAs
    51427: 03/01/13: Dennis McCrohan: Re: from ABEL/PLDs to VHDL&VeriLog/FPGAs
51364: 03/01/12: Richard B. Katz: Call for Papers: 6th MAPLD International Conference
51365: 03/01/12: S. Ramirez: Anyone Used DCI in Virtex-2?
51369: 03/01/12: RANGA REDDY: schematic to VHDL conversion???
51370: 03/01/12: Andrew Rogers: Open FPGA please!
    51373: 03/01/12: Falk Brunner: Re: Open FPGA please!
        51374: 03/01/12: Andrew Rogers: Re: Open FPGA please!
            51383: 03/01/12: Falk Brunner: Re: Open FPGA please!
            51388: 03/01/12: Nicholas C. Weaver: Re: Open FPGA please!
    51378: 03/01/12: Rene Tschaggelar: Re: Open FPGA please!
        51380: 03/01/12: Andrew Rogers: Re: Open FPGA please!
            51381: 03/01/12: Falk Brunner: Re: Open FPGA please!
            51392: 03/01/12: john jakson: Re: Open FPGA please!
    51385: 03/01/12: john jakson: Re: Open FPGA please!
        51387: 03/01/12: Andrew Rogers: Re: Open FPGA please!
            51445: 03/01/13: Steve Lass: Re: Open FPGA please!
    51393: 03/01/12: Larry Doolittle: Re: Open FPGA please!
        51395: 03/01/13: Steve Casselman: Re: Open FPGA please!
            51431: 03/01/13: Andrew Rogers: Re: Open FPGA please!
                51438: 03/01/13: Nicholas C. Weaver: Re: Open FPGA please!
                    51443: 03/01/13: Peter Alfke: Re: Open FPGA please!
                        51479: 03/01/14: glen herrmannsfeldt: Re: Open FPGA please!
                            51480: 03/01/14: Nicholas C. Weaver: Re: Open FPGA please!
                                51485: 03/01/14: Peter Alfke: Re: Open FPGA please!
                                    51486: 03/01/15: John Williams: Re: Open FPGA please!
                                    51490: 03/01/14: John_H: Re: Open FPGA please!
                                        51494: 03/01/14: Steve Lass: Re: Open FPGA please!
                                            51496: 03/01/15: Nicholas C. Weaver: Re: Open FPGA please!
                                                51497: 03/01/14: Steve Lass: Re: Open FPGA please!
                                            51503: 03/01/15: Ray Andraka: Re: Open FPGA please!
                                                51511: 03/01/15: Jim Granville: Re: Open FPGA please!
                                                    51524: 03/01/15: Ray Andraka: Re: Open FPGA please!
                                                        51528: 03/01/16: Jim Granville: Re: Open FPGA please!
                                                            51532: 03/01/15: Ray Andraka: Re: Open FPGA please!
                    51449: 03/01/13: Andrew Rogers: Re: Open FPGA please!
                        51451: 03/01/14: John Williams: Re: Open FPGA please!
                            51452: 03/01/14: Andrew Rogers: Re: Open FPGA please!
                51447: 03/01/13: Steve Casselman: Re: Open FPGA please!
                    51448: 03/01/14: John Williams: Re: Open FPGA please!
    51442: 03/01/13: rickman: Re: Open FPGA please!
    51504: 03/01/14: B. Joshua Rosen: Re: Open FPGA please!
51375: 03/01/12: tk: State machine problem
    51382: 03/01/12: Falk Brunner: Re: State machine problem
        51386: 03/01/13: tk: Re: State machine problem
            51428: 03/01/13: Falk Brunner: Re: State machine problem
                51462: 03/01/15: tk: Re: State machine problem
51377: 03/01/12: naveen: CONCEPT OF BALL GRID ARRAY
    51389: 03/01/12: Andrew Rogers: Re: CONCEPT OF BALL GRID ARRAY
        51481: 03/01/14: naveen: Re: CONCEPT OF BALL GRID ARRAY
51379: 03/01/12: John Tan: SChematic design approach compared to VHDL entry approach
    51384: 03/01/12: Falk Brunner: Re: SChematic design approach compared to VHDL entry approach
    51391: 03/01/12: Ray Andraka: Re: SChematic design approach compared to VHDL entry approach
        51396: 03/01/12: John Larkin: Re: SChematic design approach compared to VHDL entry approach
            51398: 03/01/13: Austin Franklin: Re: SChematic design approach compared to VHDL entry approach
            51400: 03/01/12: john jakson: Re: SChematic design approach compared to VHDL entry approach
            51408: 03/01/13: rk: Re: SChematic design approach compared to VHDL entry approach
    51420: 03/01/13: Kevin Brace: Re: SChematic design approach compared to VHDL entry approach
        51464: 03/01/14: Austin Franklin: Re: SChematic design approach compared to VHDL entry approach
            51475: 03/01/14: Keith R. Williams: Re: SChematic design approach compared to VHDL entry approach
                51478: 03/01/14: Nicholas C. Weaver: Re: SChematic design approach compared to VHDL entry approach
                51501: 03/01/14: Austin Franklin: Re: SChematic design approach compared to VHDL entry approach
                    51530: 03/01/15: Keith R. Williams: Re: SChematic design approach compared to VHDL entry approach
                        51535: 03/01/15: Austin Franklin: Re: Schematic design approach compared to VHDL entry approach
                            51536: 03/01/15: Eric Smith: Re: Schematic design approach compared to VHDL entry approach
                                51539: 03/01/16: Austin Franklin: Re: Schematic design approach compared to VHDL entry approach
                                    51541: 03/01/15: Eric Smith: Re: Schematic design approach compared to VHDL entry approach
                                        51553: 03/01/16: Ray Andraka: Re: Schematic design approach compared to VHDL entry approach
                                        51568: 03/01/16: Austin Franklin: Re: Schematic design approach compared to VHDL entry approach
                                            51590: 03/01/16: Eric Smith: Re: Schematic design approach compared to VHDL entry approach
                                                51619: 03/01/17: Austin Franklin: Re: Schematic design approach compared to VHDL entry approach
                                                    51644: 03/01/17: Eric Smith: Re: Schematic design approach compared to VHDL entry approach
                                                        51652: 03/01/17: Austin Franklin: Re: Schematic design approach compared to VHDL entry approach
                                                            51658: 03/01/18: Ray Andraka: Re: Schematic design approach compared to VHDL entry approach
                                                                51671: 03/01/18: Austin Franklin: Re: Schematic design approach compared to VHDL entry approach
                                                            51661: 03/01/17: Eric Smith: Re: Schematic design approach compared to VHDL entry approach
                                                                51670: 03/01/18: Austin Franklin: Re: Schematic design approach compared to VHDL entry approach
                                                                    51690: 03/01/19: Eric Smith: Re: Schematic design approach compared to VHDL entry approach
                                                                        51691: 03/01/19: Austin Franklin: Re: Schematic design approach compared to VHDL entry approach
                                                                            51702: 03/01/19: Eric Smith: Re: Schematic design approach compared to VHDL entry approach
                                                                                51718: 03/01/20: Austin Franklin: Re: Schematic design approach compared to VHDL entry approach
                                                                                    51725: 03/01/20: Eric Smith: Re: Schematic design approach compared to VHDL entry approach
                                                                                        51748: 03/01/20: Austin Franklin: Re: Schematic design approach compared to VHDL entry approach
                                                                        51692: 03/01/19: Hal Murray: Re: Schematic design approach compared to VHDL entry approach
                                                                            51697: 03/01/19: Austin Franklin: Re: Schematic design approach compared to VHDL entry approach
                                                                                51699: 03/01/20: Ray Andraka: Re: Schematic design approach compared to VHDL entry approach
                                                                                    51720: 03/01/20: Austin Franklin: Re: Schematic design approach compared to VHDL entry approach
                                                                                        51726: 03/01/20: Eric Smith: Re: Schematic design approach compared to VHDL entry approach
                                                                                            51751: 03/01/21: Austin Franklin: Re: Schematic design approach compared to VHDL entry approach
                                                                                        51743: 03/01/21: Ray Andraka: Re: Schematic design approach compared to VHDL entry approach
                                                                                            51750: 03/01/21: Austin Franklin: Re: Schematic design approach compared to VHDL entry approach
                                                                                                51769: 03/01/21: Magnus Homann: Re: Schematic design approach compared to VHDL entry approach
                                                                                                    52080: 03/01/30: Austin Franklin: Re: Schematic design approach compared to VHDL entry approach
                                                                                            51768: 03/01/21: Magnus Homann: Re: Schematic design approach compared to VHDL entry approach
                                                                                                51782: 03/01/21: Ray Andraka: Re: Schematic design approach compared to VHDL entry approach
                                                                    51825: 03/01/22: Eric Smith: Re: Schematic design approach compared to VHDL entry approach
                                        51571: 03/01/16: Nicholas C. Weaver: Re: Schematic design approach compared to VHDL entry approach
                                    51558: 03/01/16: Brian Drummond: Re: Schematic design approach compared to VHDL entry approach
                                    51674: 03/01/18: Spam Hater: Re: Schematic design approach compared to VHDL entry approach
                            51578: 03/01/16: Keith R. Williams: Re: Schematic design approach compared to VHDL entry approach
                                51593: 03/01/17: Ray Andraka: Re: Schematic design approach compared to VHDL entry approach
                                    51610: 03/01/17: Ray Andraka: Re: Schematic design approach compared to VHDL entry approach
                                51620: 03/01/17: Austin Franklin: Re: Schematic design approach compared to VHDL entry approach
        51465: 03/01/14: Austin Franklin: Re: SChematic design approach compared to VHDL entry approach
        51467: 03/01/14: Lorenzo Lutti: Re: SChematic design approach compared to VHDL entry approach
            51472: 03/01/14: Kevin Brace: Re: SChematic design approach compared to VHDL entry approach
        51492: 03/01/14: Spam Hater 7: Re: SChematic design approach compared to VHDL entry approach
            51529: 03/01/15: Keith R. Williams: Re: SChematic design approach compared to VHDL entry approach
        51493: 03/01/14: Tim: Re: SChematic design approach compared to VHDL entry approach
            51506: 03/01/15: Austin Franklin: Re: SChematic design approach compared to VHDL entry approach
                51510: 03/01/15: Spam Hater: Re: SChematic design approach compared to VHDL entry approach
                51550: 03/01/16: Tim: Re: SChematic design approach compared to VHDL entry approach
        51811: 03/01/22: Colin Marquardt: Re: Schematic design approach compared to VHDL entry approach
    51468: 03/01/14: Michael S: Re: SChematic design approach compared to VHDL entry approach
        51471: 03/01/14: Nicholas C. Weaver: Re: SChematic design approach compared to VHDL entry approach
        51476: 03/01/14: Austin Franklin: Re: SChematic design approach compared to VHDL entry approach
            51537: 03/01/15: Keith R. Williams: Re: SChematic design approach compared to VHDL entry approach
        51487: 03/01/14: Bryan: Re: SChematic design approach compared to VHDL entry approach
        51502: 03/01/15: Phil Hays: Re: SChematic design approach compared to VHDL entry approach
        51509: 03/01/15: Rene Tschaggelar: Re: SChematic design approach compared to VHDL entry approach
            51519: 03/01/15: Marlboro: Re: SChematic design approach compared to VHDL entry approach
        51549: 03/01/16: john jakson: Re: SChematic design approach compared to VHDL entry approach
            51572: 03/01/16: Austin Franklin: Re: SChematic design approach compared to VHDL entry approach
                51574: 03/01/16: Nicholas C. Weaver: Re: SChematic design approach compared to VHDL entry approach
                51596: 03/01/16: john jakson: Re: SChematic design approach compared to VHDL entry approach
    51542: 03/01/15: Assaf Sarfati: Re: SChematic design approach compared to VHDL entry approach
        51585: 03/01/16: Ad Verschueren: Re: SChematic design approach compared to VHDL entry approach
            51683: 03/01/18: Assaf Sarfati: Re: SChematic design approach compared to VHDL entry approach
                51685: 03/01/19: Ad Verschueren: Re: SChematic design approach compared to VHDL entry approach
                51687: 03/01/19: Hal Murray: Re: SChematic design approach compared to VHDL entry approach
                    51698: 03/01/19: Austin Franklin: Re: SChematic design approach compared to VHDL entry approach
                        51730: 03/01/20: Ad Verschueren: Re: SChematic design approach compared to VHDL entry approach
                            51869: 03/01/24: Austin Franklin: Re: SChematic design approach compared to VHDL entry approach
                                51889: 03/01/24: Pat Ford: Re: SChematic design approach compared to VHDL entry approach
                                    52079: 03/01/30: Austin Franklin: Re: SChematic design approach compared to VHDL entry approach
                                        52127: 03/02/02: Stephen Williams: Re: SChematic design approach compared to VHDL entry approach
                                            52140: 03/02/03: Ray Andraka: Re: SChematic design approach compared to VHDL entry approach
                    51706: 03/01/19: Assaf Sarfati: Re: SChematic design approach compared to VHDL entry approach
    52978: 03/02/27: proski: Re: SChematic design approach compared to VHDL entry approach
51390: 03/01/12: David: filter coefficient multiplication in vhdl
    51407: 03/01/13: raymund hofmann: Re: filter coefficient multiplication in vhdl
    51434: 03/01/13: john jakson: Re: filter coefficient multiplication in vhdl
    51512: 03/01/15: Ken Chapman: Re: filter coefficient multiplication in vhdl
51397: 03/01/13: 2Penny: need pointers to FPGA software & download hardware
    51410: 03/01/14: Alex Gibson: Re: need pointers to FPGA software & download hardware
    51418: 03/01/13: Dan: Re: need pointers to FPGA software & download hardware
    51444: 03/01/13: rickman: Re: need pointers to FPGA software & download hardware
        51594: 03/01/17: 2Penny: Re: need pointers to FPGA software & download hardware
51402: 03/01/13: astonish: Celoxica's White Paper on TripleDES
    51413: 03/01/13: Vikram Pasham: Re: Celoxica's White Paper on TripleDES
    51455: 03/01/13: Rudolf Usselmann: Re: Celoxica's White Paper on TripleDES
51404: 03/01/13: Nagaraj: FPGA to ASIC migration - Help
    51429: 03/01/13: john jakson: Re: FPGA to ASIC migration - Help
    51430: 03/01/13: Kevin Brace: Re: FPGA to ASIC migration - Help
        51432: 03/01/13: Kevin Brace: Re: FPGA to ASIC migration - Help
51422: 03/01/13: Jim Raynor: Simulate Virtex Primitive using ModelSim
    51433: 03/01/13: Ray Andraka: Re: Simulate Virtex Primitive using ModelSim
        51435: 03/01/13: Jim Raynor: Re: Simulate Virtex Primitive using ModelSim
            51440: 03/01/13: Len Harold: Re: Simulate Virtex Primitive using ModelSim
            51453: 03/01/14: Ray Andraka: Re: Simulate Virtex Primitive using ModelSim
    51463: 03/01/14: Barry Brown: Re: Simulate Virtex Primitive using ModelSim
        51466: 03/01/14: Ken McElvain: Re: Simulate Virtex Primitive using ModelSim
            51505: 03/01/15: Allan Herriman: Re: Simulate Virtex Primitive using ModelSim
51426: 03/01/13: satchit: RS-232 connection with SOPC Development Kit
    51491: 03/01/14: Prashant: Re: RS-232 connection with SOPC Development Kit
51446: 03/01/13: Frederic Bastenaire: How to coerce a list of discrete signals to an array in VHDL
    51450: 03/01/13: Jim Lewis: Re: How to coerce a list of discrete signals to an array in VHDL
    51454: 03/01/13: Clyde R. Shappee: Re: How to coerce a list of discrete signals to an array in VHDL
    51459: 03/01/14: frederic Bastenaire: Re: How to coerce a list of discrete signals to an array in VHDL
51457: 03/01/14: Tom Deblauwe: fpga versus cpld
    51458: 03/01/14: Uwe Bonnes: Re: fpga versus cpld
51460: 03/01/14: Pat Ford: Cesys xc2s_eval opinions
    51469: 03/01/14: Kevin Brace: Re: Cesys xc2s_eval opinions
51470: 03/01/14: Ann: Virtex, Virtex II and Virtex II Pro
    51474: 03/01/14: Ray Andraka: Re: Virtex, Virtex II and Virtex II Pro
    51477: 03/01/14: Tullio Grassi: Re: Virtex, Virtex II and Virtex II Pro
51483: 03/01/14: Jeff: How to run XST from command line?
    51499: 03/01/14: John Retta: Re: How to run XST from command line?
51484: 03/01/14: naveen: software for
51488: 03/01/14: Terry Herter: Off Topic: Single Board Computers?
    51489: 03/01/14: Nicholas C. Weaver: Re: Off Topic: Single Board Computers?
        51498: 03/01/14: Terry Herter: Re: Off Topic: Single Board Computers?
            51576: 03/01/16: john jakson: Re: Off Topic: Single Board Computers?
51495: 03/01/15: Tim: Clock routing in Virtex/E/II
51500: 03/01/14: Kuan Zhou: How to add pins in ISE 4.2
    51543: 03/01/16: Amit: Re: How to add pins in ISE 4.2
        51563: 03/01/16: Kuan Zhou: Re: How to add pins in ISE 4.2
            51595: 03/01/16: Amit: Re: How to add pins in ISE 4.2
51507: 03/01/15: Austin Franklin: Re: Spartan II found on Ebay
    51508: 03/01/15: Nicholas C. Weaver: Re: Spartan II found on Ebay
51513: 03/01/15: Skillwood: what is a Systolic Array
51514: 03/01/15: BÝrge Strand: Short FIFO in Verilog / Spartan IIE
    51516: 03/01/15: Frank Hoffmann: Re: Short FIFO in Verilog / Spartan IIE
        51518: 03/01/15: BÝrge Strand: Re: Short FIFO in Verilog / Spartan IIE
        51520: 03/01/15: Ken Chapman: Re: Short FIFO in Verilog / Spartan IIE
    51525: 03/01/15: Ray Andraka: Re: Short FIFO in Verilog / Spartan IIE
        51605: 03/01/17: Rick Filipkiewicz: Re: Short FIFO in Verilog / Spartan IIE
    51526: 03/01/15: Peter Alfke: Re: Short FIFO in Verilog / Spartan IIE
        51527: 03/01/15: Peter Alfke: Re: Short FIFO in Verilog / Spartan IIE
            51533: 03/01/15: Ray Andraka: Re: Short FIFO in Verilog / Spartan IIE
        51545: 03/01/16: BÝrge Strand: Re: Short FIFO in Verilog / Spartan IIE
51517: 03/01/15: Cisa: How can I use DCM to 1/24 freq-division?
    51521: 03/01/15: Austin Lesea: Re: How can I use DCM to 1/24 freq-division?
        51638: 03/01/17: Marc Randolph: Re: How can I use DCM to 1/24 freq-division?
            51643: 03/01/17: Austin Lesea: Re: How can I use DCM to 1/24 freq-division?
                51714: 03/01/20: Marc Randolph: Re: How can I use DCM to 1/24 freq-division?
51523: 03/01/15: Anonymous4: implementation of a switcher
51531: 03/01/15: Andrew Rogers: Problem with XST libraries.
    51534: 03/01/16: Andrew Rogers: Re: Problem with XST libraries.
        51731: 03/01/20: David Rogoff: Re: Problem with XST libraries.
            51824: 03/01/23: Andrew Rogers: Re: Problem with XST libraries.
            51826: 03/01/22: Eric Smith: Re: Problem with XST libraries.
                51827: 03/01/22: Eric Smith: Re: Problem with XST libraries.
                52085: 03/01/31: David Rogoff: Re: Problem with XST libraries.
        51737: 03/01/20: Uwe Bonnes: Re: Problem with XST libraries.
51538: 03/01/16: Matt: quality of software tools in general
    51569: 03/01/16: rickman: Re: quality of software tools in general
        51582: 03/01/16: Matt: Re: quality of software tools in general
            51599: 03/01/17: rickman: Re: quality of software tools in general
            51601: 03/01/16: john jakson: Re: quality of software tools in general
                51627: 03/01/17: Matt: Re: quality of software tools in general
                    51634: 03/01/17: Ray Andraka: Re: quality of software tools in general
                        51646: 03/01/17: Matt: Re: quality of software tools in general
                            51656: 03/01/18: Ray Andraka: Re: quality of software tools in general
                            51666: 03/01/17: john jakson: Re: quality of software tools in general
                                51679: 03/01/19: Ray Andraka: Re: quality of software tools in general
                    51665: 03/01/17: john jakson: Re: quality of software tools in general
                        51680: 03/01/19: Ray Andraka: Re: quality of software tools in general
                        51790: 03/01/22: Matt: Re: quality of software tools in general
                            51794: 03/01/22: Hal Murray: Re: quality of software tools in general
                                51819: 03/01/22: Matt: Re: quality of software tools in general
                            51805: 03/01/22: Ray Andraka: Re: quality of software tools in general
                    51668: 03/01/18: Ed: Re: quality of software tools in general
                        51676: 03/01/18: john jakson: Re: quality of software tools in general
51540: 03/01/16: Kuan Zhou: Virtex II pro architecture question
    51556: 03/01/16: Florian-Wolfgang Stock: Re: Virtex II pro architecture question
    51559: 03/01/16: Amit: Re: Virtex II pro architecture question
51546: 03/01/16: David R Brooks: Xilinx XST & multiple (source) libraries
51547: 03/01/16: Skillwood: HSPICE simulator
    51564: 03/01/16: Muzaffer Kal: Re: HSPICE simulator
51548: 03/01/16: HJO: Xilinx PCI core PCI-X compatible ?
    51612: 03/01/17: Kevin Brace: Re: Xilinx PCI core PCI-X compatible ?
        51689: 03/01/19: Nial Stewart: Re: Xilinx PCI core PCI-X compatible ?
            51704: 03/01/19: Eric Crabill: Re: Xilinx PCI core PCI-X compatible ?
            51809: 03/01/22: Kevin Brace: Re: Xilinx PCI core PCI-X compatible ?
51551: 03/01/16: Jock: Xilinx Constraint Problem
    51554: 03/01/16: Nicolas Matringe: Re: Xilinx Constraint Problem
        51560: 03/01/16: Jock: Re: Xilinx Constraint Problem
            51570: 03/01/16: rickman: Re: Xilinx Constraint Problem
                51573: 03/01/16: Falk Brunner: Re: Xilinx Constraint Problem
                    51597: 03/01/16: Amit: Re: Xilinx Constraint Problem
                        51598: 03/01/17: Ray Andraka: Re: Xilinx Constraint Problem
                            51608: 03/01/17: Amit: Re: Xilinx Constraint Problem
                                51759: 03/01/21: Jock: Re: Xilinx Constraint Problem
                51603: 03/01/17: Jock: Re: Xilinx Constraint Problem
                    51615: 03/01/17: Amit: Re: Xilinx Constraint Problem
51555: 03/01/16: tsao: 200K gates FPGA for GPU
    51557: 03/01/16: tsao: Re: 200K gates FPGA for GPU
        51562: 03/01/16: Ray Andraka: Re: 200K gates FPGA for GPU
    51561: 03/01/16: Jan Gray: Re: 200K gates FPGA for GPU
        51565: 03/01/17: tsao: Re: 200K gates FPGA for GPU
            51579: 03/01/16: emanuel stiebler: Re: 200K gates FPGA for GPU
        51580: 03/01/16: emanuel stiebler: Re: 200K gates FPGA for GPU
51566: 03/01/16: Prashant: Multiple FPGA-boards integration issues
    51575: 03/01/16: Rene Tschaggelar: Re: Multiple FPGA-boards integration issues
        51587: 03/01/16: Prashant: Re: Multiple FPGA-boards integration issues
            51606: 03/01/17: Rene Tschaggelar: Re: Multiple FPGA-boards integration issues
    51604: 03/01/17: jetmarc: Re: Multiple FPGA-boards integration issues
        51617: 03/01/17: Prashant: Re: Multiple FPGA-boards integration issues
            51624: 03/01/17: Mike Treseler: Re: Multiple FPGA-boards integration issues
            51632: 03/01/17: Spam Hater 7: Re: Multiple FPGA-boards integration issues
                51655: 03/01/17: Prashant: Re: Multiple FPGA-boards integration issues
51567: 03/01/16: Langmann: Support for older Virtex
    51586: 03/01/16: Steve Lass: Re: Support for older Virtex
        51588: 03/01/16: Kevin Brace: Re: Support for older Virtex
            51589: 03/01/16: Nicholas C. Weaver: Re: Support for older Virtex
            51630: 03/01/17: Steve Lass: Re: Support for older Virtex
                51635: 03/01/17: Langmann: Re: Support for older Virtex
                    51642: 03/01/17: Steve Lass: Re: Support for older Virtex
                        51678: 03/01/18: Aare Tali: Re: Support for older Virtex
                            51744: 03/01/20: Steve Lass: Re: Support for older Virtex
51577: 03/01/16: Dongho: adaptive filter with many zero input
    51584: 03/01/16: Patrick Mullarky: Re: adaptive filter with many zero input
51581: 03/01/16: M Schreiber: FPGA Express FSM state ordering
51583: 03/01/16: Richard Coster: SpartanII DLL lock issue
    51626: 03/01/17: Falk Brunner: Re: SpartanII DLL lock issue
        51740: 03/01/20: Richard Coster: Re: SpartanII DLL lock issue
            51806: 03/01/22: John Grant: Re: SpartanII DLL lock issue
51607: 03/01/17: flora: copy of a project
    51628: 03/01/17: Patrick Mullarky: Re: copy of a project
51609: 03/01/17: Imadur Rahman: Problem in compiling EDIF in Handel-C
51611: 03/01/17: Michael Wilspang: Booting Spartan IIE from SPI
    51625: 03/01/17: Falk Brunner: Re: Booting Spartan IIE from SPI
        51640: 03/01/17: Michael Wilspang: Re: Booting Spartan IIE from SPI
            51649: 03/01/17: Peter Wallace: Re: Booting Spartan IIE from SPI
                51654: 03/01/17: Peter Alfke: Re: Booting Spartan IIE from SPI
            51669: 03/01/18: Falk Brunner: Re: Booting Spartan IIE from SPI
                51677: 03/01/18: Hal Murray: Re: Booting Spartan IIE from SPI
                    51684: 03/01/19: Falk Brunner: Re: Booting Spartan IIE from SPI
    51629: 03/01/17: Patrick Mullarky: Re: Booting Spartan IIE from SPI
51613: 03/01/17: <scepan@serbiancafe.com>: Modelsim crashes
    51614: 03/01/17: Alan Raphael: Re: Modelsim crashes
    51631: 03/01/17: Patrick Mullarky: Re: Modelsim crashes
        51708: 03/01/20: <scepan@serbiancafe.com>: Re: Modelsim crashes
        51710: 03/01/20: <scepan@serbiancafe.com>: Re: Modelsim crashes
    51707: 03/01/19: <scepan@serbiancafe.com>: Re: Modelsim crashes
51616: 03/01/17: Thomas Buerner: Generating EDIF from HandelC
    52550: 03/02/13: James: Re: Generating EDIF from HandelC
51618: 03/01/17: Austin Franklin: PCI Device/Vendor resource off line now...
    51622: 03/01/17: Steve Casselman: Re: PCI Device/Vendor resource off line now...
51621: 03/01/17: Tariq Naqvi: Atmel FPSLIC UART Code
    51784: 03/01/21: jetmarc: Re: Atmel FPSLIC UART Code
51633: 03/01/17: Mu Young Lee: Lecroy Research Systems - what happened?
    51647: 03/01/17: John Larkin: Re: Lecroy Research Systems - what happened?
        51650: 03/01/17: Eric Inazaki: Re: Lecroy Research Systems - what happened?
            51657: 03/01/17: John Larkin: Re: Lecroy Research Systems - what happened?
        51773: 03/01/21: Paul Smith: Re: Lecroy Research Systems - what happened?
    51653: 03/01/17: Mu Young Lee: Re: Lecroy Research Systems - what happened?
    51659: 03/01/17: Tullio Grassi: Re: Lecroy Research Systems - what happened?
    51803: 03/01/22: Kolja Sulimma: Re: Lecroy Research Systems - what happened?
        51816: 03/01/22: Peter Bennett: Re: Lecroy Research Systems - what happened?
        51818: 03/01/22: Eric Inazaki: Re: Lecroy Research Systems - what happened?
51637: 03/01/17: DanyXP: Synopsys tools for Linux
51641: 03/01/17: naveen: newbie questions
51645: 03/01/17: Roger Green: XST vs Synplify observations
    51648: 03/01/17: Mike Treseler: Re: XST vs Synplify observations
        51663: 03/01/17: Roger Green: Re: XST vs Synplify observations
            51681: 03/01/19: <hamish@cloud.net.au>: Re: XST vs Synplify observations
            51741: 03/01/21: Ray Andraka: Re: XST vs Synplify observations
    51651: 03/01/17: Austin Franklin: Re: XST vs Synplify observations
    51664: 03/01/17: Roger Green: Re: XST vs Synplify observations
        51667: 03/01/18: Matt: Re: XST vs Synplify observations
    51682: 03/01/19: Ken McElvain: Re: XST vs Synplify observations
        51701: 03/01/19: Clyde R. Shappee: Re: XST vs Synplify observations
        51715: 03/01/20: Roger Green: Re: XST vs Synplify observations
51673: 03/01/18: Jerry: Multi Project DIE
    51733: 03/01/20: Steve Casselman: Re: Multi Project DIE
        51745: 03/01/20: Jerry: Re: Multi Project DIE
    51747: 03/01/20: john jakson: Re: Multi Project DIE
51675: 03/01/18: Katherine Compton: FPGA 2003 Program and Registration
51686: 03/01/19: Paul Cousoulis: PLX PCI DMA address
    51693: 03/01/19: Austin Franklin: Re: PLX PCI DMA address
        51695: 03/01/20: Paul Cousoulis: Re: PLX PCI DMA address
            51696: 03/01/19: Austin Franklin: Re: PLX PCI DMA address
                51700: 03/01/20: Paul Cousoulis: Re: PLX PCI DMA address
                    51711: 03/01/20: Michael S: Re: PLX PCI DMA address
    51727: 03/01/20: Paul Cousoulis: Re: PLX PCI DMA address
51688: 03/01/19: Davar Robdan: A Request: VHDL Source of a 32bit Floating Point ALU
    51703: 03/01/19: Eric Smith: Re: A Request: VHDL Source of a 32bit Floating Point ALU
        51762: 03/01/21: Davar Robdan: Re: A Request: VHDL Source of a 32bit Floating Point ALU - Still Looking!
            51770: 03/01/21: Jim Lewis: Re: A Request: VHDL Source of a 32bit Floating Point ALU - Still
    51776: 03/01/21: Eduard Kriegler: Re: A Request: VHDL Source of a 32bit Floating Point ALU
    51906: 03/01/25: David Bishop: Re: A Request: VHDL Source of a 32bit Floating Point ALU
51705: 03/01/19: Tom Hawkins: New Language Generates Verilog, VHDL, and C
    51716: 03/01/20: john jakson: Re: New Language Generates Verilog, VHDL, and C
    51774: 03/01/21: Caleb Hess: Re: New Language Generates Verilog, VHDL, and C
51709: 03/01/20: Marcin E. Hamerla: FLEXlm
    51742: 03/01/21: Kevin Neilson: Re: FLEXlm
        51752: 03/01/21: Marcin E. Hamerla: Re: FLEXlm
            51760: 03/01/21: Nial Stewart: Re: FLEXlm
                51785: 03/01/21: Marcin E. Hamerla: Re: FLEXlm
                    51797: 03/01/22: Thomas Rudloff: Re: FLEXlm
                        51800: 03/01/22: Marcin E. Hamerla: Re: FLEXlm
                51786: 03/01/21: jetmarc: Re: FLEXlm
                    51787: 03/01/22: Domagoj: Re: FLEXlm
                        51837: 03/01/23: jetmarc: Re: FLEXlm
                    51871: 03/01/24: Austin Franklin: Re: FLEXlm
51712: 03/01/20: Richard: Parsing Xilinx Timing Reports
    51717: 03/01/20: John_H: Re: Parsing Xilinx Timing Reports
        51732: 03/01/20: Dennis McCrohan: Re: Parsing Xilinx Timing Reports
            51763: 03/01/21: Richard: Re: Parsing Xilinx Timing Reports
                51817: 03/01/22: Richard: Re: Parsing Xilinx Timing Reports
                    51886: 03/01/24: <hamish@cloud.net.au>: Re: Parsing Xilinx Timing Reports
51713: 03/01/20: x: Virtex2 configuration problem
51719: 03/01/20: Sudip Saha: Altera Excalibur devices, Arm integrator board
51721: 03/01/20: Ediz Cetin: Virtex 2 FPGA Board ...
    51722: 03/01/20: Alan Raphael: Re: Virtex 2 FPGA Board ...
    51736: 03/01/20: Christoph Hauzeneder: Re: Virtex 2 FPGA Board ...
51723: 03/01/20: frank: frequency matching of ring oscillators
    51728: 03/01/20: Peter Alfke: Re: frequency matching of ring oscillators
    51729: 03/01/20: Austin Lesea: Re: frequency matching of ring oscillators
        51735: 03/01/20: Ray Andraka: Re: frequency matching of ring oscillators
            51739: 03/01/20: Austin Lesea: Re: frequency matching of ring oscillators
    51746: 03/01/20: john jakson: Re: frequency matching of ring oscillators
    51783: 03/01/21: frank: Re: frequency matching of ring oscillators
        52005: 03/01/29: Jim Granville: Re: frequency matching of ring oscillators
51738: 03/01/20: Bill: fpga accelerated architectures
51749: 03/01/20: DILEEP: Ram bits for Registers
    51754: 03/01/21: Peng Cong: Re: Ram bits for Registers
    51771: 03/01/21: Peter Alfke: Re: Ram bits for Registers
    51789: 03/01/21: Amit: Re: Ram bits for Registers
51753: 03/01/20: RISC taker: Tristate vs. MUX
    51765: 03/01/21: Ray Andraka: Re: Tristate vs. MUX
    51766: 03/01/21: Felix Madlener: Re: Tristate vs. MUX
51755: 03/01/21: Peng Cong: FPGA new bie question
    51772: 03/01/21: Falk Brunner: Re: FPGA new bie question
51756: 03/01/21: Dave: Simulink to vhdl tools
    51942: 03/01/27: Bernhard Holzmayer: Re: Simulink to vhdl tools
        52096: 03/01/31: Justin Cowling: Re: Simulink to vhdl tools
51757: 03/01/21: Sam Duncan: Virtex II embedded multipliers
    51758: 03/01/21: Sam Duncan: Re: Virtex II embedded multipliers
        51764: 03/01/21: Ray Andraka: Re: Virtex II embedded multipliers
51761: 03/01/21: Riccardo Rubini: WTB: 16L8 / 20L8 programmer
    51967: 03/01/27: Christoph Brinkhaus: Re: WTB: 16L8 / 20L8 programmer
51775: 03/01/21: John M: Virtex II: noise on Vcco causing loss of DCM lock
    51779: 03/01/21: Bob Perlman: Re: Virtex II: noise on Vcco causing loss of DCM lock
    51781: 03/01/21: Austin Lesea: Re: Virtex II: noise on Vcco causing loss of DCM lock
        51813: 03/01/22: John M: Re: Virtex II: noise on Vcco causing loss of DCM lock
            51815: 03/01/22: Austin Lesea: Re: Virtex II: noise on Vcco causing loss of DCM lock
                51833: 03/01/23: Martin Thompson: Re: Virtex II: noise on Vcco causing loss of DCM lock
            51820: 03/01/22: Ray Andraka: Re: Virtex II: noise on Vcco causing loss of DCM lock
                51845: 03/01/23: John M: Re: Virtex II: noise on Vcco causing loss of DCM lock
51777: 03/01/21: Roger: VHDL or Verilog?
    51788: 03/01/21: B. Joshua Rosen: Re: VHDL or Verilog?
        51802: 03/01/22: john jakson: Re: VHDL or Verilog?
        51804: 03/01/22: Ray Andraka: Re: VHDL or Verilog?
    51792: 03/01/22: Kyle Davis: Re: VHDL or Verilog?
    51793: 03/01/21: Assaf Sarfati: Re: VHDL or Verilog?
        51798: 03/01/22: Hal Murray: Re: VHDL or Verilog?
            51823: 03/01/22: B. Joshua Rosen: Re: VHDL or Verilog?
            51832: 03/01/22: Assaf Sarfati: Re: VHDL or Verilog?
                51858: 03/01/23: Andy Peters: Re: VHDL or Verilog?
                    51919: 03/01/25: Assaf Sarfati: Re: VHDL or Verilog?
            51841: 03/01/23: Jeff Cunningham: Re: VHDL or Verilog?
                51842: 03/01/23: Jonathan Bromley: Re: VHDL or Verilog?
                    51843: 03/01/23: B. Joshua Rosen: Re: VHDL or Verilog?
                        51849: 03/01/23: Caleb Hess: Re: VHDL or Verilog?
                            51851: 03/01/23: Jonathan Bromley: Re: VHDL or Verilog?
                        51852: 03/01/23: Tim: Re: VHDL or Verilog?
                    51860: 03/01/23: Andy Peters: Re: VHDL or Verilog?
                    51941: 03/01/27: Martin Thompson: Somewhat OT - TECO, was Re: VHDL or Verilog?
                        51963: 03/01/27: Philip Freidin: Re: Somewhat OT - TECO
                            51964: 03/01/27: Jonathan Bromley: Re: Somewhat OT - TECO
                51859: 03/01/23: Andy Peters: Re: VHDL or Verilog?
                    51865: 03/01/24: Larry Doolittle: Re: VHDL or Verilog?
                        51870: 03/01/24: Muzaffer Kal: Re: VHDL or Verilog?
                        51877: 03/01/24: Jonathan Bromley: Re: VHDL or Verilog?
                        51887: 03/01/24: <hamish@cloud.net.au>: Re: VHDL or Verilog?
                            51891: 03/01/24: Larry Doolittle: Re: VHDL or Verilog?
                                51894: 03/01/25: Allan Herriman: Re: VHDL or Verilog?
                            51892: 03/01/24: Michael: Re: VHDL or Verilog?
        52008: 03/01/28: Matthew Fowle: Re: VHDL or Verilog?
    51814: 03/01/22: Tom Hawkins: Re: VHDL or Verilog?
    51868: 03/01/24: Tim: Re: VHDL or Verilog?
    51935: 03/01/26: Rob Finch: Re: VHDL or Verilog?
        51973: 03/01/28: Ray Andraka: Re: VHDL or Verilog?
        52012: 03/01/28: Andy Peters: Re: VHDL or Verilog?
51778: 03/01/21: Florin Franovici: ISE 5.1 help
    51808: 03/01/22: Frederic Bastenaire: Re: ISE 5.1 help
        51810: 03/01/22: Chen Wei Tseng: Re: ISE 5.1 help
51791: 03/01/22: Kyle Davis: Xilinx Foundation and ISE compatibility
    51795: 03/01/22: Noddy: Re: Xilinx Foundation and ISE compatibility
        51796: 03/01/22: Kyle Davis: Re: Xilinx Foundation and ISE compatibility
    51799: 03/01/22: Fritz: Re: Xilinx Foundation and ISE compatibility
51801: 03/01/22: Eduardo Wenzel Bri„o: Partial Reconfiguration : Xapp290 Example
    51846: 03/01/23: Chen Wei Tseng: Re: Partial Reconfiguration : Xapp290 Example
        51949: 03/01/27: Eduardo Wenzel Bri„o: Re: Partial Reconfiguration : Xapp290 Example
51807: 03/01/22: Frederic Bastenaire: Conditional signal assignment
    51812: 03/01/22: Caleb Hess: Re: Conditional signal assignment
51821: 03/01/22: John Providenza: Xilinx Spartan2 with more than 4 clocks
    51822: 03/01/22: Austin Lesea: Re: Xilinx Spartan2 with more than 4 clocks
    51829: 03/01/22: Duane Clark: Re: Xilinx Spartan2 with more than 4 clocks
        51848: 03/01/23: John Providenza: Re: Xilinx Spartan2 with more than 4 clocks
51828: 03/01/22: Eric Smith: What's a "D-MIPS"?
    51830: 03/01/23: Nicholas C. Weaver: Re: What's a "D-MIPS"?
        51866: 03/01/23: Eric Smith: Re: What's a "D-MIPS"?
    51831: 03/01/23: Neeraj Varma: Re: What's a "D-MIPS"?
51834: 03/01/23: Uwe Bonnes: Using unbonded CPLD IO Pads?
    51850: 03/01/23: Falk Brunner: Re: Using unbonded CPLD IO Pads?
51835: 03/01/23: Michael: free x86 core ip
    51844: 03/01/23: Felix Bertram: Re: free x86 core ip
    51855: 03/01/23: Kevin Brace: Re: free x86 core ip
        51861: 03/01/23: Nicholas C. Weaver: Re: free x86 core ip
        51867: 03/01/24: Michael: Re: free x86 core ip
    51864: 03/01/24: f5: Re: free x86 core ip
        51890: 03/01/24: john jakson: Re: free x86 core ip
51836: 03/01/23: Thomas Buerner: Xilinx Impact on a SUN/Solaris
    51838: 03/01/23: Uwe Bonnes: Re: Xilinx Impact on a SUN/Solaris
    51847: 03/01/23: Petter Gustad: Re: Xilinx Impact on a SUN/Solaris
51839: 03/01/23: Patrick Twomey: Celoxica RC100 Demo Board: Video In
    51862: 03/01/24: John Williams: Re: Celoxica RC100 Demo Board: Video In
51840: 03/01/23: Peng Cong: What's the reason?
51853: 03/01/23: Tim At This Newsgroup: Xilinx/Altera pricing
    51854: 03/01/23: Uwe Bonnes: Re: Xilinx/Altera pricing
        51856: 03/01/23: Tim At This Newsgroup: Re: Xilinx/Altera pricing
51872: 03/01/24: geeko: AES(Rijindal) CTR with CBC MAC
    51880: 03/01/24: Nicholas C. Weaver: Re: AES(Rijindal) CTR with CBC MAC
    51884: 03/01/24: David Jones: Re: AES(Rijindal) CTR with CBC MAC
        51893: 03/01/24: Nicholas C. Weaver: Re: AES(Rijindal) CTR with CBC MAC
    51904: 03/01/25: Rudolf Usselmann: Re: AES(Rijindal) CTR with CBC MAC
51873: 03/01/24: Kuan Zhou: What's the difference between LUT and RAM?
    51898: 03/01/24: Ray Andraka: Re: What's the difference between LUT and RAM?
        51902: 03/01/25: Kuan Zhou: Re: What's the difference between LUT and RAM?
            51912: 03/01/25: Ray Andraka: Re: What's the difference between LUT and RAM?
                51920: 03/01/26: glen herrmannsfeldt: Re: What's the difference between LUT and RAM?
                    51958: 03/01/27: Peter Alfke: Re: What's the difference between LUT and RAM?
                    51961: 03/01/27: Ray Andraka: Re: What's the difference between LUT and RAM?
                        51995: 03/01/28: glen herrmannsfeldt: Re: What's the difference between LUT and RAM?
                            52001: 03/01/28: Ray Andraka: Re: What's the difference between LUT and RAM?
                                52675: 03/02/18: Marc Baker: Re: What's the difference between LUT and RAM?
51874: 03/01/24: geeko: AMBA AHB compliant core
    51943: 03/01/27: John Penton: Re: AMBA AHB compliant core
51875: 03/01/24: <email_address@message.end>: Expansion for Cypress Demo Board
51876: 03/01/24: kooos: Byteblaster
51878: 03/01/24: Stefan Kulke: Problems with "impact.exe" from ISE webpack 5.1
    51881: 03/01/24: Jan Pech: Re: Problems with "impact.exe" from ISE webpack 5.1
        51888: 03/01/24: Stefan Kulke: Re: Problems with "impact.exe" from ISE webpack 5.1
51879: 03/01/24: Vladislav Vasilenko: SRL initialization problem
    51903: 03/01/24: RISC taker: Re: SRL initialization problem
51883: 03/01/24: David Collier: Xilinx ise 51. how to do a nice simple simulation
    52108: 03/01/31: Tullio Grassi: Re: Xilinx ise 51. how to do a nice simple simulation
51885: 03/01/24: Imadur Rahman: Using Xilinx Logicores in Handel-C!
    51899: 03/01/24: Steffan Westcott: Re: Using Xilinx Logicores in Handel-C!
51895: 03/01/24: Sean: Using an EPC16 as ONLY flash memory (ie. no configuration) - overkill?
    51896: 03/01/24: Petter Gustad: Re: Using an EPC16 as ONLY flash memory (ie. no configuration) - overkill?
        51934: 03/01/26: Sean: Re: Using an EPC16 as ONLY flash memory (ie. no configuration) - overkill?
            51994: 03/01/28: Petter Gustad: Re: Using an EPC16 as ONLY flash memory (ie. no configuration) - overkill?
51897: 03/01/24: Wayne: Altera Cyclone EP1C12 pins changed in Quartus 2.2 from 2.1
    52567: 03/02/13: Greg Steinke: Re: Altera Cyclone EP1C12 pins changed in Quartus 2.2 from 2.1
51900: 03/01/25: tsao: DK1 grunt
    51910: 03/01/25: Imadur Rahman: Re: DK1 grunt
51901: 03/01/24: Sonali Kale: PROM : Master serial configuration
51905: 03/01/25: astonish: Rijndael Implementation using DK1
51907: 03/01/25: David: Why so many pins?
    51908: 03/01/25: Phil Hays: Re: Why so many pins?
        51911: 03/01/25: Ray Andraka: Re: Why so many pins?
        51913: 03/01/25: Nicholas C. Weaver: Re: Why so many pins?
            51915: 03/01/25: Kuan Zhou: Re: Why so many pins?
                51916: 03/01/26: Nicholas C. Weaver: Re: Why so many pins?
                    51917: 03/01/25: Kuan Zhou: Re: Why so many pins?
                        51918: 03/01/26: Nicholas C. Weaver: Re: Why so many pins?
                            51926: 03/01/26: Kuan Zhou: Re: Why so many pins?
                                51928: 03/01/26: Nicholas C. Weaver: Re: Why so many pins?
        51914: 03/01/25: David: Re: Why so many pins?
    51932: 03/01/26: John_H: Re: Why so many pins?
51909: 03/01/25: Charles Stuart: registered bi-directional IOB?
    51931: 03/01/26: John_H: Re: registered bi-directional IOB?
51921: 03/01/26: RISC taker: Extending a Virtex-II block RAM?
    51925: 03/01/26: Falk Brunner: Re: Extending a Virtex-II block RAM?
    51930: 03/01/26: John_H: Re: Extending a Virtex-II block RAM?
        51938: 03/01/26: RISC taker: Re: Extending a Virtex-II block RAM?
            51952: 03/01/27: Ray Andraka: Re: Extending a Virtex-II block RAM?
51922: 03/01/26: cedi: Bus models & test benches
51923: 03/01/26: Vladimir: IEEE 1149.1
    51940: 03/01/27: Petter Gustad: Re: IEEE 1149.1
51927: 03/01/26: Jens Niemann: Prob. with data-input of SDRAM-Controller
    53327: 03/03/10: rickman: Re: Prob. with data-input of SDRAM-Controller
        53364: 03/03/12: S. Ramirez: Re: Prob. with data-input of SDRAM-Controller
51929: 03/01/26: Houman: New to FPGA world...need guidline/help
    51933: 03/01/26: Rene Tschaggelar: Re: New to FPGA world...need guidline/help
    51936: 03/01/26: Mauricio Lange: Re: New to FPGA world...need guidline/help
    51939: 03/01/27: RISC taker: Re: New to FPGA world...need guidline/help
    51959: 03/01/27: Peter Alfke: Re: New to FPGA world...need guidline/help
    51969: 03/01/27: john jakson: Re: New to FPGA world...need guidline/help
51937: 03/01/26: Saurabh Pal: better clock speed???
    52026: 03/01/28: praveen: Re: better clock speed???
51944: 03/01/27: Robert Koch: conversion from Xilinx schematics to Mentor Graphics?
    51966: 03/01/27: Laurent Gauch, Amontec: Re: conversion from Xilinx schematics to Mentor Graphics?
        51981: 03/01/28: robka: Re: conversion from Xilinx schematics to Mentor Graphics?
51945: 03/01/27: praveen: vhdl core of PCI bridge
    51974: 03/01/28: Mike D: Re: vhdl core of PCI bridge
        52021: 03/01/28: praveen: Re: vhdl core of PCI bridge
    52022: 03/01/29: Kevin Brace: Re: vhdl core of PCI bridge
        52034: 03/01/29: praveen: Re: vhdl core of PCI bridge
            52041: 03/01/29: Mike D: Re: vhdl core of PCI bridge
            52217: 03/02/04: Kevin Brace: Re: vhdl core of PCI bridge
                52238: 03/02/04: praveen: Re: vhdl core of PCI bridge
                    52239: 03/02/05: Kevin Brace: Re: vhdl core of PCI bridge
51946: 03/01/27: Richard: Map report in XML?
51947: 03/01/27: sduszyk: xilinx schematics conversion
51948: 03/01/27: Vladislav Vasilenko: XST 4.1 bug or ..?
51950: 03/01/27: itsme: Xilinx ISE 5.1 SP3: XST BUG!!!
    51953: 03/01/27: Uwe Bonnes: Re: Xilinx ISE 5.1 SP3: XST BUG!!!
51951: 03/01/27: Alain: FSM and XST
    51962: 03/01/27: Mike Treseler: Re: FSM and XST
        52007: 03/01/28: Vikram: Re: FSM and XST
            52028: 03/01/29: Alain: Re: FSM and XST
                52135: 03/02/02: Clyde R. Shappee: Re: FSM and XST
51954: 03/01/27: Paulo Valentim: Virtex-II and LVDS clocks.
    52129: 03/02/02: <hamish@cloud.net.au>: Re: Virtex-II and LVDS clocks.
51955: 03/01/27: Moss Ben: Carry Logic propagation delay
    51956: 03/01/27: John_H: Re: Carry Logic propagation delay
    51960: 03/01/27: Ray Andraka: Re: Carry Logic propagation delay
        51970: 03/01/27: Moss Ben: Re: Carry Logic propagation delay
            51972: 03/01/28: Ray Andraka: Re: Carry Logic propagation delay
            51996: 03/01/28: Peter Alfke: Re: Carry Logic propagation delay
            51997: 03/01/28: John_H: Re: Carry Logic propagation delay
51968: 03/01/28: Florian: Clock Feedback for DDR-SDRAM (XApp200)
    51993: 03/01/28: John_H: Re: Clock Feedback for DDR-SDRAM (XApp200)
    52123: 03/02/01: Boris Foelsch: Re: Clock Feedback for DDR-SDRAM (XApp200)
    52179: 03/02/03: B. Joshua Rosen: Re: Clock Feedback for DDR-SDRAM (XApp200)
        52185: 03/02/03: Boris Foelsch: Re: Clock Feedback for DDR-SDRAM (XApp200)
        52186: 03/02/03: Boris Foelsch: Re: Clock Feedback for DDR-SDRAM (XApp200)
51971: 03/01/27: Sudip Saha: excalibur device : clock routing
    51984: 03/01/28: Sujatha: Re: excalibur device : clock routing
51975: 03/01/28: Ralph Mason: Re: GNU C for custom processor
51976: 03/01/28: Rene Tschaggelar: Switching clock ( Altera ACEX )
    51977: 03/01/28: phil: Re: Switching clock ( Altera ACEX )
51978: 03/01/28: Jonathan Bromley: Re: GNU C for custom processor
    51983: 03/01/28: Alan Fitch: Re: GNU C for custom processor
51979: 03/01/28: Stefano M: AND gate into CPLD
    51985: 03/01/28: Rick Filipkiewicz: Re: AND gate into CPLD
51980: 03/01/28: Lars Unger: 1024bit Adder
    51982: 03/01/28: Ken Chapman: Re: 1024bit Adder
    51986: 03/01/28: Ray Andraka: Re: 1024bit Adder
    51998: 03/01/28: glen herrmannsfeldt: Re: 1024bit Adder
        52004: 03/01/28: Muzaffer Kal: Re: 1024bit Adder
    52029: 03/01/29: Lars Unger: Re: 1024bit Adder
    52030: 03/01/29: Lars Unger: Re: 1024bit Adder
    52031: 03/01/29: Lars Unger: Re: 1024bit Adder
51987: 03/01/28: dimmy: Re: GNU C for custom processor
51988: 03/01/28: Moss Ben: Installing 2 versions of Xilinx software in the same machine
    51990: 03/01/28: Ray Andraka: Re: Installing 2 versions of Xilinx software in the same machine
    51991: 03/01/28: Chen Wei Tseng: Re: Installing 2 versions of Xilinx software in the same machine
    52027: 03/01/29: Noddy: Re: Installing 2 versions of Xilinx software in the same machine
        52077: 03/01/30: MikeJ: Re: Installing 2 versions of Xilinx software in the same machine
51989: 03/01/28: Andrew Rogers: XC3020 .nph
    52000: 03/01/28: Peter Alfke: Re: XC3020 .nph
        52003: 03/01/28: Andrew Rogers: Re: XC3020 .nph
            52014: 03/01/28: Steve Lass: Re: XC3020 .nph
        52018: 03/01/29: Tim: Re: XC3020 .nph
            52019: 03/01/28: Peter Alfke: Re: XC3020 .nph
51992: 03/01/28: Mauricio Lange: PCI protocol - assigning an address to my device
    51999: 03/01/28: glen herrmannsfeldt: Re: PCI protocol - assigning an address to my device
    52002: 03/01/28: Kevin Brace: Re: PCI protocol - assigning an address to my device
        52023: 03/01/28: Mauricio Lange: Re: PCI protocol - assigning an address to my device
        52024: 03/01/28: praveen: Re: PCI protocol - assigning an address to my device
            52035: 03/01/29: Mauricio Lange: Re: PCI protocol - assigning an address to my device
    52114: 03/01/31: Austin Franklin: Re: PCI protocol - assigning an address to my device
        52187: 03/02/03: Mauricio Lange: Re: PCI protocol - assigning an address to my device
        52218: 03/02/04: Kevin Brace: Re: PCI protocol - assigning an address to my device
            52270: 03/02/05: Austin Franklin: Re: PCI protocol - assigning an address to my device
52006: 03/01/28: Roberto Gallo: Random number generator
    52009: 03/01/28: Peter Alfke: Re: Random number generator
    52013: 03/01/28: Ray Andraka: Re: Random number generator
        52110: 03/01/31: Ray Andraka: Re: Random number generator (OT)
    52025: 03/01/29: glen herrmannsfeldt: Re: Random number generator
    52033: 03/01/29: svhb: Re: Random number generator
        52036: 03/01/29: Uwe Bonnes: Re: Random number generator
            52094: 03/01/31: svhb: Re: Random number generator
    52062: 03/01/30: s.d.: Re: Random number generator
52010: 03/01/28: Ryan Gammon: JTAG
    52011: 03/01/28: Falk Brunner: Re: JTAG
        52017: 03/01/28: Michol Bauer: Re: JTAG
    52039: 03/01/29: Wayne: Re: JTAG
        52047: 03/01/29: Uwe Bonnes: Re: JTAG
            52070: 03/01/30: Ryan Gammon: Re: JTAG
                52071: 03/01/30: Uwe Bonnes: Re: JTAG
52015: 03/01/28: Antonio Pasini: [help] timing closure problem on two slightly different xilinx designs
    52056: 03/01/29: Kate Kelley: Re: [help] timing closure problem on two slightly different xilinx
        52072: 03/01/30: Antonio Pasini: Re: [help] timing closure problem on two slightly different xilinx designs
            52099: 03/01/31: Kate Kelley: Re: [help] timing closure problem on two slightly different xilinx
52016: 03/01/29: Marc Van Riet: GNU C for custom processor
    52038: 03/01/29: Wayne: Re: GNU C for custom processor
    52040: 03/01/29: Tim Olson: Re: GNU C for custom processor
        52067: 03/01/30: Larry Doolittle: Re: GNU C for custom processor
        52075: 03/01/30: Marc Van Riet: Re: GNU C for custom processor
52020: 03/01/28: Pete Dudley: analog in analog out DSP development board for Xilinx
    52032: 03/01/29: Bob: Re: analog in analog out DSP development board for Xilinx
    52046: 03/01/29: Tom Loredo: Re: analog in analog out DSP development board for Xilinx
52037: 03/01/29: Dave Wilson: Reading External .txt files in Quartus II
    52042: 03/01/29: Arash Salarian: Re: Reading External .txt files in Quartus II
        52059: 03/01/30: Dave Wilson: Re: Reading External .txt files in Quartus II
            52068: 03/01/30: Arash Salarian: Re: Reading External .txt files in Quartus II
            52069: 03/01/30: Mike Treseler: Re: Reading External .txt files in Quartus II
                52089: 03/01/31: Dave Wilson: Re: Reading External .txt files in Quartus II
52043: 03/01/29: RM: Xilinx memory size
    52044: 03/01/29: Ray Andraka: Re: Xilinx memory size
    52045: 03/01/29: Peter Alfke: Re: Xilinx memory size
52048: 03/01/29: Roberto Gallo: Reconfigure only some elements
    52050: 03/01/29: Peter Alfke: Re: Reconfigure only some elements
        52052: 03/01/29: Nicholas C. Weaver: Re: Reconfigure only some elements
            52054: 03/01/29: Peter Alfke: Re: Reconfigure only some elements
        52053: 03/01/29: Chen Wei Tseng: Re: Reconfigure only some elements
52049: 03/01/29: Talal: problem in Virtex
52051: 03/01/29: jianghongtu@hotmail.com: problem with JTAG downloading
    52055: 03/01/29: FPGA Newsgroups: Re: problem with JTAG downloading
52057: 03/01/29: Rahul: Huffman Encoder and Decoder in verilog/ vhdl
    52060: 03/01/30: Kolja Sulimma: Re: Huffman Encoder and Decoder in verilog/ vhdl
    52086: 03/01/30: Rudolf Usselmann: Re: Huffman Encoder and Decoder in verilog/ vhdl
52058: 03/01/29: Poolar Bear: Writing and Reading into RC100 Flash RAM
    52261: 03/02/05: Sameer D. Sahasrabuddhe: Re: Writing and Reading into RC100 Flash RAM
52061: 03/01/30: zhengyu: one hot encoding
    52064: 03/01/30: RM: Re: one hot encoding
    52148: 03/02/03: Ernest Jamro: Re: one hot encoding
        52154: 03/02/03: Ray Andraka: Re: one hot encoding
        52162: 03/02/03: Hal Murray: Re: one hot encoding
52063: 03/01/30: Alexey: Xilinx Foundation 3.1 problem
52065: 03/01/30: Sean: How to do on-the-fly reconfiguration of a Flex10ke using an EPC16?
    52122: 03/02/01: Jaap Mol: Re: How to do on-the-fly reconfiguration of a Flex10ke using an EPC16?
52073: 03/01/30: david lamb: How to set leonardo path in Quartus?
    52082: 03/01/31: Subroto Datta: Re: How to set leonardo path in Quartus?
    52097: 03/01/31: Subroto Datta: Re: How to set leonardo path in Quartus?
        52109: 03/01/31: David: Re: How to set leonardo path in Quartus?
52076: 03/01/30: Roger: Quartus
    52084: 03/01/31: Subroto Datta: Re: Quartus
        52088: 03/01/31: Paul Baxter: Re: Quartus
            52092: 03/01/31: Nial Stewart: Re: Quartus
                52095: 03/01/31: Paul Baxter: Re: Quartus
                52101: 03/01/31: Kevin Brace: Re: Quartus
52078: 03/01/31: John Williams: Microblaze - triggering exceptions
    52081: 03/01/30: Goran Bilski: Re: Microblaze - triggering exceptions
        52083: 03/01/31: John Williams: Re: Microblaze - triggering exceptions
            52098: 03/01/31: Goran Bilski: Re: Microblaze - triggering exceptions
                52138: 03/02/03: John Williams: Proper OS for Microblaze [was Re: Microblaze - triggering exceptions]
52087: 03/01/31: Markus Meng: More than four clocks within a spartan-ii device?
    52100: 03/01/31: John Providenza: Re: More than four clocks within a spartan-ii device?
        52102: 03/01/31: Kate Kelley: Re: More than four clocks within a spartan-ii device?
    52144: 03/02/03: Hal Murray: Re: More than four clocks within a spartan-ii device?
52090: 03/01/31: Imadur Rahman: WLAN Implementation using Handel-C?
52091: 03/01/31: Muthu: Xilinx Design Softwares?
    52106: 03/01/31: Steve Lass: Re: Xilinx Design Softwares?
        52116: 03/02/01: Muthu: Re: Xilinx Design Softwares?
            52160: 03/02/03: Steve Lass: Re: Xilinx Design Softwares?
52093: 03/01/31: Thijs: problem programming atmel fpga config mem
52103: 03/01/31: freny: STATE PROBLEM!
    52104: 03/01/31: Falk Brunner: Re: STATE PROBLEM!
    52105: 03/01/31: Mike Treseler: Re: STATE PROBLEM!
        52111: 03/01/31: Ray Andraka: Re: STATE PROBLEM!
52107: 03/01/31: Mauricio Lange: LogiBLOX behavior
52112: 03/01/31: Gordon Friend: Virtex2 PCI and 5V


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