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Threads Starting Nov 1995
2206: 95/11/01: Kurt R. Zaske: Re: FREE $$$ MAKING SOFTWARE !!!
2207: 95/11/01: Sashi Obilisetty: **ANNOUNCEMENT: VHDL to Verilog Translator**
2208: 95/11/02: Steve Casselman: XC4025 routing
2227: 95/11/06: Christian Grebe: Re: XC4025 routing
2209: 95/11/02: S.J.B.Acock: Xilinx XSI FPGA User Guide
2214: 95/11/02: Peter Alfke: Re: Xilinx XSI FPGA User Guide
2215: 95/11/02: Andy Gulliver: Re: Xilinx XSI FPGA User Guide
2228: 95/11/06: Christian Grebe: Re: Xilinx XSI FPGA User Guide
2212: 95/11/02: Wayne Addy: altera problems
2216: 95/11/03: Philip Freidin: Re: altera problems
2213: 95/11/02: Russ Tessier: request for RTL netlists
2285: 95/11/17: John Cooley: Re: request for RTL netlists
2297: 95/11/17: Erik Jessen: Re: request for RTL netlists
2335: 95/11/21: yehuda yizraeli: Re: request for RTL netlists
2220: 95/11/03: David R. Brooks: FPGA => ASIC
2225: 95/11/06: kayvon irani: Re: FPGA => ASIC
2221: 95/11/04: Bas Evers: US-NY-Syracuse Engineering positions
2223: 95/11/05: Mike Diack: simulation (.hst) file compatability
2224: 95/11/05: Nico Coesel: Wanted motorola fpga mpa1036
2226: 95/11/06: TWColl: X-Blox...The good, bad and ugly
2233: 95/11/07: <cha>: Re: X-Blox...The good, bad and ugly
2234: 95/11/07: John McCluskey: Re: X-Blox...The good, bad and ugly
2245: 95/11/09: Lauri Kuru: Re: X-Blox...The good, bad and ugly
2249: 95/11/09: Per Bjureus: Re: X-Blox...The good, bad and ugly
2229: 95/11/06: Satnam Singh: Re: DCC'96 2nd Call for Papers
2230: 95/11/06: Carol Perkins: IMPORTANT WORLD COMMUNITY PUBLIC ANNOUNCEMENT
2232: 95/11/07: NAM MIN WOO: I find large VHDL code(for my partition system)
2236: 95/11/07: Little Caesar: Re: I find large VHDL code(for my partition system)
2235: 95/11/07: Jeffrey Bain: Needed: Protozone Adapter
2239: 95/11/08: Mark Snook: Wanted Xilinx XC3090LTQ176-8PC
2240: 95/11/08: Guy Gerard Lemieux: FPD'96 Call for Papers
2241: 95/11/08: Jeffrey M. Arnold: FPL'96 Call for Papers
2242: 95/11/09: <caleb@audiologic.com>: Can X30xx Reset itself?
2248: 95/11/09: Don Husby: Re: Can X30xx Reset itself?
2251: 95/11/09: Don Husby: Re: Can X30xx Reset itself?
2250: 95/11/09: Andy Gulliver: Re: Can X30xx Reset itself?
2253: 95/11/10: Peter Alfke: Re: Can X30xx Reset itself?
2264: 95/11/15: eric: Can Actel A12XX probe itself? (was: Can X30xx Reset itself?)
2243: 95/11/09: Alan Cooney: BP Micro and CUPL -- a good start?
2254: 95/11/10: Trevor Hall: Re: BP Micro and CUPL -- a good start?
2246: 95/11/09: Alberto Broggi: Final CFP - Real-Time Imaging J. - Special Issue on Special Purpose Architectures
2247: 95/11/09: Paul Brown: JTAG IEEE std 1149.1
2252: 95/11/09: David Van den Bout: Re: JTAG IEEE std 1149.1
2256: 95/11/11: Brett Christopher WALKER: FPGA references and good starting points?
2258: 95/11/12: David Van den Bout: Re: FPGA references and good starting points?
2261: 95/11/14: Frank Soehnge: Industry Trends
2267: 95/11/15: Rocky Awalt: Re: Industry Trends
2273: 95/11/16: Rob Janssen: Re: Industry Trends
2303: 95/11/18: Ray Andraka: Re: Industry Trends
2304: 95/11/18: Dwight Elvey: Re: Industry Trends
2270: 95/11/16: <geneb@entropy.ultranet.com>: Re: Industry Trends
2283: 95/11/17: Frank Soehnge: Re: Industry Trends
2359: 95/11/22: John Payson: Re: Industry Trends
2282: 95/11/17: Erik Jessen: Re: Industry Trends
2305: 95/11/18: gyoung.sna.com: Re: Industry Trends
2308: 95/11/18: David Van den Bout: Re: Industry Trends
2361: 95/11/23: Jack Sandell: Re: Industry Trends
2408: 95/12/01: Steve Jones: Industry Trends
2416: 95/12/02: David Van den Bout: Re: Industry Trends
2262: 95/11/14: NAM MIN WOO: Looking for large circuit
2265: 95/11/15: M. Movahedin: Re: Looking for large circuit
2266: 95/11/15: Jan Kubuschok: Xilinx XACT Windows Version
2315: 95/11/19: Georg Acher: Re: Xilinx XACT Windows Version
2332: 95/11/21: David J Starr: Re: Xilinx XACT Windows Version
2352: 95/11/22: Joe Samson: Re: Xilinx XACT Windows Version
2393: 95/11/28: alain arnaud: Re: Xilinx XACT Windows Version
2403: 95/11/30: David J Starr: Re: Xilinx XACT Windows Version
2404: 95/11/30: alain arnaud: Re: Xilinx XACT Windows Version
2406: 95/12/01: David J Starr: Re: Xilinx XACT Windows Version
2415: 95/12/02: Baskaran Kasimani: Re: Xilinx XACT Windows Version
2414: 95/12/02: Baskaran Kasimani: Re: Xilinx XACT Windows Version
2422: 95/12/03: Steven K. Knapp, Xilinx, Inc.: Re: Xilinx XACT Windows Version
2271: 95/11/16: Scott A. Hauck: Thesis available: multi-FPGA systems
2292: 95/11/17: Scott Alan Hauck: Re: Thesis available: multi-FPGA systems
2272: 95/11/16: Uwe Bonnes: [Q] FPGA Software for Linux
2276: 95/11/16: Michael J. Wirthlin: Re: [Q] FPGA Software for Linux
2299: 95/11/17: Jack Greenbaum: Re: [Q] FPGA Software for Linux
2310: 95/11/18: Ingo Cyliax: Re: [Q] FPGA Software for Linux
2330: 95/11/20: Erik Jessen: Re: [Q] FPGA Software for Linux
2301: 95/11/17: Petri Havanto: Re: [Q] FPGA Software for Linux
2274: 95/11/16: <cha>: WHO WAS THE XACT'S PROGRAMMER?
2275: 95/11/16: -N.RAMESH: Any user experiences with Exemplar VHDL synthesis for FPGA
2295: 95/11/17: Erik Jessen: Re: Any user experiences with Exemplar VHDL synthesis for FPGA
2277: 95/11/16: Russ Tessier: request for synthesizable Verilog/VHDL
2278: 95/11/16: <srivasta@cobaf.unt.edu>: Tape
2279: 95/11/16: Philip Freidin: Re: Tape
2280: 95/11/16: Ido Nir: 2nd Global Clocks in ALTERA MAX7000E ? Help !!!
2294: 95/11/17: Paul S Secinaro: Re: 2nd Global Clocks in ALTERA MAX7000E ? Help !!!
2284: 95/11/17: mush: Re: BP Micro and CUPL -- a good start?
2318: 95/11/20: Trevor Hall: Re: BP Micro and CUPL -- a good start?
2286: 95/11/17: John Cooley: NeoCAD and AT&T vs. Xilinx
2293: 95/11/17: Pete Becker: Re: NeoCAD and AT&T vs. Xilinx
2316: 95/11/19: John Cooley: Re: NeoCAD and AT&T vs. Xilinx
2343: 95/11/21: Dick Gray: Re: NeoCAD and AT&T vs. Xilinx
2296: 95/11/17: Erik Jessen: Re: NeoCAD and AT&T vs. Xilinx
2314: 95/11/19: Udi Finkelstein: Re: NeoCAD and AT&T vs. Xilinx
2324: 95/11/20: Bob Hoffman x8931: Re: NeoCAD and AT&T vs. Xilinx
2362: 95/11/23: <ericd>: Re: NeoCAD and AT&T vs. Xilinx
2395: 95/11/28: W. S. Zuk: Re: NeoCAD and AT&T vs. Xilinx
2405: 95/11/30: Eric Dellinger: Re: NeoCAD and AT&T vs. Xilinx
2409: 95/12/01: David Pashley: Re: NeoCAD and AT&T vs. Xilinx
2419: 95/12/02: Ian McEwen: Re: NeoCAD and AT&T vs. Xilinx
2420: 95/12/02: John Lazzaro: Re: NeoCAD and AT&T vs. Xilinx
2388: 95/11/27: John Cooley: Re: NeoCAD and AT&T vs. Xilinx
2397: 95/11/28: Eliot Blennerhassett: Re: NeoCAD and AT&T vs. Xilinx
2424: 95/12/04: Darren Wedgwood: Re: NeoCAD and AT&T vs. Xilinx
2287: 95/11/17: John Cooley: Re: [q][Reverse Engineering Protection]
2300: 95/11/17: Erik Jessen: Re: [q][Reverse Engineering Protection]
2320: 95/11/20: Erik Jessen: Re: [q][Reverse Engineering Protection]
2321: 95/11/20: Richard M. Greene: Re: [q][Reverse Engineering Protection]
2326: 95/11/20: John Cooley: Re: [q][Reverse Engineering Protection]
2329: 95/11/20: Erik Jessen: Re: [q][Reverse Engineering Protection]
2331: 95/11/20: Ray Andraka: Re: [q][Reverse Engineering Protection]
2346: 95/11/21: Michael Hasselberg: Re: [q][Reverse Engineering Protection]
2306: 95/11/18: Mike Saltmarsh: Re: [q][Reverse Engineering Protection]
2312: 95/11/19: Les Bartel: Re: [q][Reverse Engineering Protection]
2317: 95/11/20: tzechien: Re: [q][Reverse Engineering Protection]
2307: 95/11/18: Mark Indovina: Re: [q][Reverse Engineering Protection]
2311: 95/11/19: Philip Freidin: Re: [q][Reverse Engineering Protection]
2309: 95/11/18: Eric Edwards: Re: [q][Reverse Engineering Protection]
2515: 95/12/22: R. D. Davis: Re: [q][Reverse Engineering Protection]
2518: 95/12/23: Charles W. Hubbard: Re: [q][Reverse Engineering Protection]
2519: 95/12/23: Dan Fraser: Re: [q][Reverse Engineering Protection]
2625: 96/01/13: Robert York: Re: [q][Reverse Engineering Protection]
2520: 95/12/24: John Souders: Re: [q][Reverse Engineering Protection]
2543: 95/12/30: Raymond K. Petry: Re: [q][Reverse Engineering Protection]
2523: 95/12/27: Rob-L: Re: [q][Reverse Engineering Protection]
2524: 95/12/27: Henry Baker: Re: [q][Reverse Engineering Protection]
2526: 95/12/27: Mike Saltmarsh: Re: [q][Reverse Engineering Protection]
2531: 95/12/28: John Lull: Re: [q][Reverse Engineering Protection]
2530: 95/12/28: Rob-L: Re: [q][Reverse Engineering Protection]
2525: 95/12/27: Ed Beers: Re: [q][Reverse Engineering Protection]
2528: 95/12/27: Bill Clark: Re: [q][Reverse Engineering Protection]
2529: 95/12/27: Bill Clark: Re: [q][Reverse Engineering Protection]
2533: 95/12/28: Jeff Hunsinger: Re: [q][Reverse Engineering Protection]
2607: 96/01/10: eric schonning: Re: [q][Reverse Engineering Protection]
2629: 96/01/15: Mike Saltmarsh: Re: [q][Reverse Engineering Protection]
2630: 96/01/16: Henry Baker: Re: [q][Reverse Engineering Protection]
2633: 96/01/16: Steve Work: Re: [q][Reverse Engineering Protection]
2642: 96/01/17: G. Herrmannsfeldt: Re: [q][Reverse Engineering Protection]
2644: 96/01/18: kephart: Re: [q][Reverse Engineering Protection]
2635: 96/01/16: kephart: Re: [q][Reverse Engineering Protection]
2636: 96/01/17: Henry Baker: Re: [q][Reverse Engineering Protection]
2643: 96/01/17: Bernd "Bernie" Meyer: Re: [q][Reverse Engineering Protection]
2650: 96/01/19: Michael Williams: Re: [q][Reverse Engineering Protection]
2540: 95/12/29: Henry Spencer: Re: [q][Reverse Engineering Protection]
2584: 96/01/06: John Cooley: Re: [q][Reverse Engineering Protection]
2589: 96/01/09: Morris Jones: Re: [q][Reverse Engineering Protection]
2596: 96/01/10: Michael Lodman: Re: [q][Reverse Engineering Protection]
2627: 96/01/13: kephart: Re: [q][Reverse Engineering Protection]
2572: 96/01/04: Dennis O'Connor~: Re: [q][Reverse Engineering Protection]
2288: 95/11/17: John Cooley: Vendors For Verilog On The PC
2325: 95/11/20: Bob Hoffman x8931: Re: Vendors For Verilog On The PC
2344: 95/11/21: Garnett Hamilton: Re: Vendors For Verilog On The PC
2390: 95/11/28: suzanne M southworth: Re: Vendors For Verilog On The PC
2428: 95/12/04: Ravi Ramakrishnan: Re: Vendors For Verilog On The PC
2389: 95/11/28: suzanne M southworth: Re: Vendors For Verilog On The PC
2290: 95/11/17: Gary Moneysmith: FYI: Flash memory data recording
2291: 95/11/17: Doug Shade: Wanted-limited Verilog or VHDL synthesis
2298: 95/11/17: Erik Jessen: Re: Wanted-limited Verilog or VHDL synthesis
2302: 95/11/17: John Cooley: Re: X-Blox...The good, bad and ugly
2313: 95/11/19: Eric Edwards: options for VHDL or Verilog simulation/synthesis < $10,000 ?
2319: 95/11/20: Pete Becker: Re: options for VHDL or Verilog simulation/synthesis < $10,000 ?
2334: 95/11/21: Eric Edwards: Re: options for VHDL or Verilog simulation/synthesis < $10,000 ?
2322: 95/11/20: Pete Becker: Looking for Low-$ Programmer
2323: 95/11/20: John Cooley: Rorschach Testing 273 Engineers With The Verilog-VHDL Contest
2407: 95/12/01: John Cooley: INDUSTRY GADFLY: The Fall(ing) VIUF '95
2327: 95/11/20: Clarence Brown (Cla): Device Programmer Selection
2348: 95/11/21: KeilSoftW: Re: Device Programmer Selection
2356: 95/11/22: Jay Francis: Re: Device Programmer Selection
2328: 95/11/20: Pete Becker: PC VHDL synth for FPGA?
2365: 95/11/24: Wayne Hammerschlag: Re: PC VHDL synth for FPGA?
2413: 95/12/02: Maurice Moore: Re: PC VHDL synth for FPGA?
2423: 95/12/04: Erik Jessen: Re: PC VHDL synth for FPGA?
2333: 95/11/21: Comp Arch Lab Group #6: request for synthesizable VHDL for RAM
2367: 95/11/24: Michael Gschwind: Re: request for synthesizable VHDL for RAM
2376: 95/11/25: Steven K. Knapp, Xilinx, Inc.: Re: request for synthesizable VHDL for RAM
2336: 95/11/21: David Mot: (no subject)
2337: 95/11/21: David Mot: (no subject)
2338: 95/11/21: David Mot: (no subject)
2371: 95/11/24: Jay Francis: Re: (no subject)
2372: 95/11/24: Jay Francis: Re: (no subject)
2382: 95/11/27: David Mot: Chipmaster 3000 Universal Device Programmer
2386: 95/11/27: David Pashley: Re: Chipmaster 3000 Universal Device Programmer
2339: 95/11/21: David Mot: (no subject)
2340: 95/11/21: David Mot: Re: (no subject)
2341: 95/11/21: David Mot: (no subject)
2342: 95/11/21: David Mot: Low Cost Tools
2350: 95/11/22: Andreas Kugel: Re: Low Cost Tools
2357: 95/11/22: Alan Cooney: Re: Low Cost Tools
2351: 95/11/22: Jonathon Ralston: ISSPA 96 Final Call for Papers
2353: 95/11/22: Jason Cong: FPGA'96 Advance Program
2355: 95/11/22: Steven K. Knapp, Xilinx, Inc.: Re: Xilinx Viewlogic simulation
2369: 95/11/24: Andrew Dyer: Re: Xilinx Viewlogic simulation
2373: 95/11/24: Oleg Sheynin: Re: Xilinx Viewlogic simulation
2375: 95/11/25: Steven K. Knapp, Xilinx, Inc.: Re: Xilinx Viewlogic simulation
2358: 95/11/22: Edward C. Schram: Re: Device Programmer Selection
2360: 95/11/22: Oleg Sheynin: Xilinx Viewlogic simulation
2368: 95/11/24: Baskaran Kasimani: Re: Xilinx Viewlogic simulation
2363: 95/11/23: Gerhard Hoffmann: Re: XBLOX: the good, the bad and the shocking
2378: 95/11/26: Eric Aardoom: Re: XBLOX: the good, the bad and the shocking
2380: 95/11/26: Bill Clark: Re: XBLOX: the good, the bad and the shocking
2392: 95/11/28: Jan Gray: XBLOX vs. "CNets", lfsr dividers, etc.
2399: 95/11/28: Bill Clark: Re: XBLOX vs. "CNets", lfsr dividers, etc.
2364: 95/11/23: Andreas Kirschbaum: Call for Papers: FPL '96
2370: 95/11/24: Ingo Cyliax: XNF netlister for Chipmunk
2374: 95/11/24: Ingo Cyliax: PC/Parallel poret Atmel Configuration EEPROM programmer
2377: 95/11/25: Andreas Doering: looking for FPGA prototype platform
2379: 95/11/26: David Van den Bout: Re: looking for FPGA prototype platform
2381: 95/11/27: David Mot: (no subject)
2456: 95/12/07: Mark Byers: Re: (no subject)
2383: 95/11/27: David Mot: Low Cost Altera Development System
2384: 95/11/27: Som Sikdar: CRC-32 implementation
2387: 95/11/27: Hing-Fai Lee: Re: CRC-32 implementation
2443: 95/12/06: Alex Koegel: Re: CRC-32 implementation
2445: 95/12/06: alain arnaud: Re: CRC-32 implementation
2467: 95/12/08: Fred Schimmel: Re: CRC-32 implementation
2468: 95/12/09: Ray Andraka: Re: CRC-32 implementation
2471: 95/12/11: Fred Schimmel: CRC-32 implementation
2385: 95/11/27: richard taylor: Second CFP : Cosynthesis for reconfigurable systems
2391: 95/11/28: <granville@decus.org.nz>: Lattice GAL16VP8 -is it real ?
2396: 95/11/28: Jay Lessert: Re: Lattice GAL16VP8 -is it real ?
2400: 95/11/28: David Van den Bout: Re: Lattice GAL16VP8 -is it real ?
2394: 95/11/28: Jim Kapcio: Checksum from .pof file
2398: 95/11/28: Scott Murphy: bus model of the 68EC000
2401: 95/11/29: <SHAR@shams.eun.eg>: subscribe
2402: 95/11/29: Arrigo Benedetti: Opinions on Cadence FPGA designer
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
