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In article <DLCKD6.Lr@wombat.hanse.de>,
Bernd "Bernie" Meyer <root@wombat.hanse.de> wrote:
>hbaker@netcom.com (Henry Baker) writes:
>>Since the chips on the American cars are probably more sophisticated, they may
>>be doing more than their European counterparts.
>
>Do I detect a certain snobbishness here?
I think he's basing his opinion on the emission regulations in the states
being more stringent than those in the Europe. However I suspect some
European manufacturers (Audi/Porsche, BMW, Volvo, Jaguar all spring to
mind) might argue the point.
Mike.
_____________________________________________________________________
\ x / Michael Williams Advanced RISC Machines Limited
|\/|\/\ michael.williams@armltd.co.uk Fulbourn Road, Cambridge, CB1 4JN, UK
| |.__)"I might well think that Matti, ARM Ltd. couldn't possibly comment."
Article: 2651I'm searching for a tool (program) that will take a PLD JDEC file and reproduce the logic equations for the PLD. We are currently trying to debug circuit cards with PLDs on them, however the documentation for the PLDs are out dated and incorrect (as can be seen with a logic analyzer). The PLDs that we are using are 22V10. I would appreciate any pointers that people may have. -SimonArticle: 2652
: I have since been working on another old design where a microprocessor : configures the chip (Peripheral Mode). This ceased to function - and I had : forgotton about the problem with the other design so wasted a similar amount : of time diagnosing it! : : Although it was easy to explain why the first design ceased to function, I am : somewhat perplexed about the other. It appears that the Xilinx chip is unable : to produce the last (or it seems like the last two, when I hook a counter on : it) RDY pulses to haul in all of the configuration. Surely if the IOBs : take over too early, this is a problem with the chip? : : Incidentally, I managed to get the chip to configure without the -xa option : by altering the length count - but I'm glad I've found out how to do it : properly! : : Matthew matthew@rd.bbc.co.uk My opinions, not Auntie's. I think I may have had a similar problem to this just last week - a 3190A in peripheral mode would assert its DONE/PG_ pin but the IOBs remained in configuration mode (i.e. LDC low, HDC high and all others high-Z). The solution, discovered at the end of a Xilinx app. note after a day of probing around with the 'scope looking for dodgy bus activity, turned out to be modifying the length count by a few bits using the "-lc=aligned_lc" option to makeprom. It has worked fine ever since. Ian. e-mail ima@nemesys.co.uk Nemesys Research Ltd. www http://www.nemesys.co.uk 14 Regent Street 'phone +44 1223 566300 Cambridge fax +44 1223 566301 England CB2 1DB ---Article: 2653
In article <hersman.821993240@aplcomm.jhuapl.edu>
hersman@aplcomm.jhuapl.edu "Chris Hersman" writes:
"Does anyone know of a way to program an Actel FPGA in the circuit?
"
"I am aware that even if it is possible, it's not straight forward.
"
Apparently, the programming is a very complex and demanding matter.
To my knowledge only three programmer vendors have managed to do it
(BP Microsystems, Data I/O, SMS), so you're unlikely to be able to
do it in circuit.
--
David Pashley
Article: 2654Article: 2655
No doubt I will regret this (I am already regretting it)... but here goes
Jason Feinsmith at Xilinx wrote:
JF> I have a study which was done by a researcher at University of
JF> Toronto which does a full comparison of routing in the Xilinx
JF> 4000 versus the Altera 8000 (Flex) family. The summary you
JF> may find interesting, and if you would like a faxed copy of
JF> it, please send your fax number to me (my email is
JF> jason.feinsmith@xilinx.com). The conclusion implies that
JF> Xilinx 4000 routes better than does the Altera Flex 8000.
JF> I'll quote 2 summary items from the paper:
JF> "3.1 Results for the Xilinx XC4000 FPGAs... It is interesting
JF> to note that for all circuits used, none of them becomes
JF> un-routable even under the worst pin constraints. This was
JF> true even for the circuits that were very tightly packed, in
JF> terms of percentage of available CLBs and I/O pins used."
JF> and
JF> "3.2 Results for the Altera FLEX 8000 FPGAs... The Altera
JF> FLEX 8000 FPGAs seem to be slightly susceptible to routing
JF> failures uner random pin constraints in cases where the I/O
JF> pin or logic element utilization is close to 100%. ... It
JF> seems that system designers, when implementig a circuit using
JF> FLEX 8000 FPGAs, should leave about 20% of the logic eements
JF> and I/O pins free to avoid routability problems due to pin
JF> constraints."
and then,
I (B. Hutchings) at Brigham Young flamed Jason. Rather than flaming
Jason, I should have said what I thought was wrong with the post. I
apologize for being harsh. My main problem was that there was no
indication of where the paper had been published or who had wrote it.
That being said, I also disagree with the sweeping conclusion (which
might have been Jason's or the paper's, I could not tell). We do a lot
of work with a variety of FPGA devices here at BYU and while the
ability to route inspite of lots of pin constraints is important,
there are many other things to consider. For example, what happens to
your *timing* as you lock down pins and use more FPGA resources? That is
just one of several questions that the paper may even respond to (for
all I know) but wasn't addressed in Jason's post. Why not just post
the citation and let everyone draw their own conclusion?
Well, sorry to waste bandwidth...
--
Brad L. Hutchings - (801) 378-2667 - hutch@ee.byu.edu
Brigham Young University - Electrical Eng. Dept. - 459 CB - Provo, UT 84602
Reconfigurable Logic Laboratory
Article: 2656
Try this
//*************** Verilog Code *****************
module test ;
reg input ;
reg output ;
initial
begin
input = 1'b0 ;
output = 1'b0 ;
#10 input = 1'b1 ;
#1 input = 1'b0 ;
end
always @(input)
if (input)
#10 output = 1'b1 ;
else
#5 output = 1'b0 ;
endmodule
//*************** Verilog Code *****************
/* I pulse the signal for 1 ns
I expected the output to pulse 10ns later
What happened is the ouput stayed high !
*/
Thanks
___ ___
/ /\ /\ Bill Seiler
/___/ \/__\ Circuit City / Patapsco West
/\ \ / /\ 3255-4 Scott Blvd, Suite 105
/__\___\/___/ \ Santa Clara, CA 95054
\ / /\ \ / 408 982 5420 Direct
\/___/ \___\/ 408 982 5430 FAX
\ \ /\ /\ ccwest@ix.netcom.com
\___\/__\/ \
\ \ / "Fold me up into 4D space."
\___\/
muzok@msn.com (muzo) wrote:
>hi,
>I am looking for suggestions on good interview questions for a digital designer.
>Interesting verilog coding issues, synthesis questions, issues which shows the
>understanding of basic design fundemantals (meta-stability etc) are welcome.
>thanks
>muzo
>standard disclaimer
Article: 2657
In article <4do6ve$t7f@portal.gmu.edu>
swood@melpar.esys.com "S.G. Wood, Jr." writes:
> I'm searching for a tool (program) that will take a PLD JDEC file and
> reproduce the logic equations for the PLD. We are currently trying to debug
> circuit cards with PLDs on them, however the documentation for the PLDs are
> out dated and incorrect (as can be seen with a logic analyzer). The PLDs that
> we are using are 22V10. I would appreciate any pointers that people may have.
>
I believe (not certain though) that e-mailing mpe@mpe.demon.co.uk will get you
some information on some such software. I think it was a part of their X-Shell
package which is a Forth based Cross-Compiler System.
Their Tel: is +44 (0) 1703-780084.
--
Paul E. Bennett
peb@transcontech.co.uk
Going Forth Safely
Article: 2658Matthew Marks wrote: > > My gripe concerns Xilinx changing a default in makebits > between versions 4.5 (?) and 5.1 (?). --SNIP-- > I had one design where the configuration ROM held 8 configurations and the > Xilinx chip itself was able to initate re-configuration if it detected that > this was necessary. This stopped working. (Master Parallel Mode) --SNIP-- > Although it was easy to explain why the first design ceased to function, I am > somewhat perplexed about the other. It appears that the Xilinx chip is unable > to produce the last (or it seems like the last two, when I hook a counter on > it) RDY pulses to haul in all of the configuration. Surely if the IOBs > take over too early, this is a problem with the chip? > > Incidentally, I managed to get the chip to configure without the -xa option > by altering the length count - but I'm glad I've found out how to do it > properly! > I've run into this problem too and lost a day or two of work. The length count wierdness is documented in the makebits chapter as well as in an app note or two. I was peeved at the makebits command line change as well as the easter egg hunt I had to undertake to discover a problem that a good portion of the Xilinx community has probably suffered through. I guess we've all earned our Xilinx purple hearts over this! Cheers, ScottArticle: 2659
in <4do6ve$t7f@portal.gmu.edu>, S.G. Wood, Jr. wrote: : I'm searching for a tool (program) that will take a PLD JDEC file and : reproduce the logic equations for the PLD. We are currently trying to debug : circuit cards with PLDs on them, however the documentation for the PLDs are : out dated and incorrect (as can be seen with a logic analyzer). The PLDs that : we are using are 22V10. I would appreciate any pointers that people may have. Opal Jr, National Semi's free or cheap Pal assembler package included the JED2EQN program that would revert a 22V10. (If you were lucky enough to get a chip not copy protected.) Should be a common part of any recent PAL assembler by the competing manufacturers. I'm not sure of any current net location, and National has dropped their GAL/PAL line, so their sales rep may no longer carry it. You can buy the software disks for a GAL programmer from the hobby magazine Elektor Electronics that includes OPAL Jr. Here are a few URL's that may or may not still be valid for PLD software. ftp://ftp.funet.fi/pub/cae. ftp://ftp.cs.indiana.edu/pub/goo/PLD/ http://www.cs.ucla.edu/csd-grads-gs3/loving/www/m2l.html Mark Zenier mzenier@eskimo.com mzenier@netcom.comArticle: 2660
swood@melpar.esys.com (S.G. Wood, Jr.) wrote: >I'm searching for a tool (program) that will take a PLD JDEC file and >reproduce the logic equations for the PLD. We are currently trying to debug >circuit cards with PLDs on them, however the documentation for the PLDs are >out dated and incorrect (as can be seen with a logic analyzer). The PLDs that >we are using are 22V10. I would appreciate any pointers that people may have. > >-Simon I believe that ABEL by Data-IO can do this. Also the PLDshell that Intel used to sell (now part of Altera) could do it (I think). You could also check with Logical Devices, who makes CUPL to see if they can do this. Good luck- Larry -- _ __ __ _____ | | | \ / | / ___ \ Larry Martin Consulting | | | \ \ / / | / / \_\ Analog - RF - Microwave | | | |\ \/ /| | | | | | | | \ / | | | | __ Frequency Synthesizers | |____ | | \/ | | \ \___/ / |______| |_| |_| \_____/ Voice: 707-829-0633Article: 2661
As a user of FPGA and EPLD devices. Very often I bumped into routing
problem e.g.
1) not able to fit my design into my target chip even it is in the 80%
range. (vendor A)
2) routed my design but 100s of ns late (vendor B)
3) routed my design, but if I spend a day in routing it manually, I could
get decrease the area used for 50% + the improvement in timming.
(vendor C)
4) routed my design and then I fixed the pin they give me and they failed
to route it again with the pin fixed. (vendor D + A)
5) It crash during place and route.
Yes I know it is very HARD to design the place and route software. If you
asked me to design one, I have no idea where to start. After optimized the
logic equation, how would one start place the logic?
Is there any introduction article on place and route software on the NET.
So that FPGA/EPLD users like me could understand a bit more and
appreciate the hard work our P&R designer do.
May be it could help us to design a more routable design.
Yes, it may affect the protability and ability to reuse the design.
But more than often, for some parts of my designs I would use schematic
instead of VHDL to take advantage of the target device's architecture,
though I wish I don't need to do that if the software could take care
of it.
--
Edwin Tsang, Email:edwint@bnr.ca , NORTEL
Opinion is mine only and I reserved the right to change it
Article: 2662Yes, I attended a presentation by Steven about two weeks ago in Mountain View. They have this SBUS card with a single Xilinx chip that was pretty interesting. Here's the address: Virtual Computer Corp 6925 Canby Ave #103 Reseda, Ca 91335 818 342-8294 info@vcc.com Arrigo Benedetti (benedett@dsi.unimo.it) wrote: : Does anyone know if Steven Casselman's Virtual Computer Corporation : is still alive?Article: 2663
In article <4ddfu1$4kd@news.csie.nctu.edu.tw>, Chuang Hsien-Ho <eea80593@orioles.EE.NCTU.edu.tw> wrote: >Chuang Hsien-Ho (eea80593@maddux.EE.NCTU.edu.tw) ´£¨ì: >: We have a project, "A Baseband Chip Set for Digital Cellular Phone", in >: progress. We will soon finish the verilog coding. Now we want to prepare >: for the emulation step. We have about tens of thousands of gates, targeting >: on at least 6MHz. >: Being a academic project, we might not able to afford a complete commercial >: system. We plan to buy some RAM-based FPGAs(like XC4000 or ALTERA FLEX series), >: maybe some FPICs(like Aptix). >: Could you experienced persons give me some comments or suggestions? Or where >: can I get the detail information of these vendors? Thanks a lot. > >Many thanks to those who gave me suggestion. It sounds that ALTERA will be >better in rounting, but Xilinx will be easy for first user. I am really >interested in the average utilization of XC4000 and FLEX8000(FLEX10K). >Does anyone has experience? > >However, no one told me about the FPICs. The only vendor I know is Aptix, >but I don't know if they have agent in Taiwan. Could anyone tell me? >I also heard that the FPIC is expensive. If we don't use FPIC, is there >any alternatives for the emulation board? > Try the chips from I-Cube. They are smaller than the Aptix chips (160 I/O although I think they are coming out with a 320 I/O version) but easier to work with. They have a cross-bar architecture so they don't need a complicated router. I-Cube used to supply a simple C library you could use to make your own downloading software. I can personally vouch that I-Cube's stuff worked very well (at least back in 1993). -- || Dave Van den Bout -- XESS Corp. || || 2608 Sweetgum Dr., Apex, NC 27502 || || (919) 387-0076 FAX:(919) 387-1302 || || devb@xess.com devb@vnet.net ||Article: 2664
>> I'm searching for a tool (program) that will take a PLD JDEC file and >> reproduce the logic equations for the PLD. We are currently trying to debug >> circuit cards with PLDs on them, however the documentation for the PLDs are >> out dated and incorrect (as can be seen with a logic analyzer). The PLDs that >> we are using are 22V10. I would appreciate any pointers that people may have. >> ALTERA's free PLDSHELL tools include a disassembler that will take a JEDEC file and return a PLDasm file for a particular part. I believe one of the parts it works for is the 22V10. You can call ALTERA and get them to send you the tools. You can also download them from ftp://ftp.vnet.net/pub/users/xess/PLDSHELL/pldsh.zip (I think -- I can never get the path right). -- || Dave Van den Bout -- XESS Corp. || || 2608 Sweetgum Dr., Apex, NC 27502 || || (919) 387-0076 FAX:(919) 387-1302 || || devb@xess.com devb@vnet.net ||Article: 2665
In article <4do6ve$t7f@portal.gmu.edu>
swood@melpar.esys.com "S.G. Wood, Jr." writes:
> I'm searching for a tool (program) that will take a PLD JDEC file and
> reproduce the logic equations for the PLD. We are currently trying to debug
> circuit cards with PLDs on them, however the documentation for the PLDs are
> out dated and incorrect (as can be seen with a logic analyzer). The PLDs that
> we are using are 22V10. I would appreciate any pointers that people may have.
>
Old versions of AMD's PALASM have a JEDEC "disassembler". The new (MINC based)
MACH XL for AMD devices does not have such a feature.
I believe ABEL from Data I/O has this feature.
T.H.
Article: 2666
cnuddep@sh.bel.alcatel.be (peter cnudde sh146 8218) wrote:
> We all agree that the level of abstraction will increase, how else could
> we design 10M gate ASICs?
Simon J Davidmann <simond@vchips.com> wrote:
>I am sure we won't be writing it in VHDL, what we shall be doing is doing
>a lot of design re-use and purchasing complete packaged blocks from 3rd
>parties - like our PCI, PCMCIA, USB, ATM cores - chip designers will be
>putting blocks together - with small bits of new design - not designing
>10M gates from scratch...
>
>Simon Davidmann
>Virtual Chips, Inc.
Although Simon works at a company that sells 3rd party designs, I think his
view on this is right on. That is, the big designs of the future will
contain a hell of a lot of pre-packaged subdesigns that will be provided
by people/companies other than the 10M chip designer with the value add
of the 10M chip designer being in the significantly smaller custom glue
logic & subdesigns he/she creates.
- John Cooley
Part Time EDA Consumer Advocate
Full Time ASIC, FPGA & EDA Design Consultant
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 3713 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 2667
Tony Goodloe <tgoodloe@adtran.com> wrote:
>Verilog vs. VHDL - IT DOESN'T MATTER! People have shipped products
>and made money using each. Learn one. Don't fret about the decision.
>The hard part is understanding what HDLs are all about in general.
>Once you learn one, the other will come.
Sorry, Tony, but I have to disagree with you on this one here. Unlike Europe
or in Japan, U.S. engineers are basically hired by the buzzwords they have
on their resume *and* how well the engineers know them. Most U.S. companies
don't like to train if they can get a person with the right buzzwords in the
first place. In light of the last 10 years, most U.S. workers know they're
disposable at any moment -- so it pays to keep your career such that the
right buzzwords are on your resume at all times.
- John Cooley
Part Time EDA Consumer Advocate
Full Time ASIC, FPGA & EDA Design Consultant
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 3713 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 2668As well as giving you the PALASM equations, PLDLab95 from iNt (in Munich) also generates state-machine descriptions and schematics from JEDEC files. -- David Pashley < ------------------------ < < < ---------- Email: david@fpga.demon.co.uk | Direct Insight Ltd < < < < > Tel: +44 1280 700262 | | *The EDA Source* < < < Fax: +44 1280 700577 | --------------------------- < ------------------------------------------Article: 2669
In article <DLKMv9.Is5@world.std.com>, John Cooley <jcooley@world.std.com> writes >cnuddep@sh.bel.alcatel.be (peter cnudde sh146 8218) wrote: >> We all agree that the level of abstraction will increase, how else could >> we design 10M gate ASICs? > >Simon J Davidmann <simond@vchips.com> wrote: >>I am sure we won't be writing it in VHDL, what we shall be doing is doing >>a lot of design re-use and purchasing complete packaged blocks from 3rd >>parties - like our PCI, PCMCIA, USB, ATM cores - chip designers will be >>putting blocks together - with small bits of new design - not designing >>10M gates from scratch... >> >>Simon Davidmann >>Virtual Chips, Inc. > >Although Simon works at a company that sells 3rd party designs, I think his >view on this is right on. That is, the big designs of the future will >contain a hell of a lot of pre-packaged subdesigns that will be provided >by people/companies other than the 10M chip designer with the value add >of the 10M chip designer being in the significantly smaller custom glue >logic & subdesigns he/she creates. > > - John Cooley > Part Time EDA Consumer Advocate > Full Time ASIC, FPGA & EDA Design Consultant > I also agree with this trend. In fact it is already here... You only have to look at the companies who used to (and probably still do) provide custom design services, who now publish/market an extensive range of 'off the shelf cores'. What appears to be missing is any good design tools to assist designers (or do you know different). I see the challenge for the EDA tool companies is to provide tools which allow designers to 'manage' this process. Some parallels have been drawn, in the past, with PCB design techniques i.e. the value added is how you put these blocks together. Whilst some aspects of PCB design are relevant, I think there is one fundimental difference which will have a major impact on the style of design tools required. In the PCB world when you use, say a pentium chip, you can only use that chip they way it was designed to work i.e. you can't change the gate implementation. With embeded cores you can and typically get synthisable HDL which is also user configurable. This means that each gate level implementation is going to be different. It will have different timing characteristics, implementation etc. The factors which will influence the implementation are not only the configuration parameters you set as a designer, but the synthsis tool used, its version (different versions of the same tool typically build gates differently) but also the user specified logic surrounding the core. This leads me to the question of how do you evaluate one companies core against anothers, without doing a full design? At the time you would evaluate a core, typically very early in the design cycle, the factors which would influence the suitablity of one core over another are not known. Is this a silicon definition of 'Catch 22'? What I think is needed is effectively on line data books (similar to what PCB designers have) which provide you with not only the functional data, but 'generic' timing data and simulatable code for functional suitabliity verification. The generic timing data would be used with a black boxed level of hierarchy, so that the synthesis tool has something reasonable to work on and then depending on wether you can meet these timing constraints would dictate your next step. Whilst I don't see any alternative to using cores, if you want chips > 10m gates, new EDA tools are going to be required to help manage this subtly different design approach. I have not seen any tools out there today that come close to providing this sort of functionality. If you know different please do let me know. PS. If this mail appears to come from Brian Childs, sorry, this is not correct. It should come from Steve Bird steve@vizef.demon.co.uk. We have installed some new mailer s/w and it is proving to be difficult to configure correctly.... -- Steve Bird steve@vizef.demon.co.uk Opinions are mine, mine, mine...Article: 2670
John Cooley (jcooley@world.std.com) wrote: : Sorry, Tony, but I have to disagree with you on this one here. Unlike Europe : or in Japan, U.S. engineers are basically hired by the buzzwords they have : on their resume *and* how well the engineers know them. Most U.S. companies : don't like to train if they can get a person with the right buzzwords in the : first place. In light of the last 10 years, most U.S. workers know they're : disposable at any moment -- so it pays to keep your career such that the : right buzzwords are on your resume at all times. John, you are right on. What are those buzzwords (for FPGA/ASIC designer): VHDL, Verilog, ASIC, FPGA, Synopsys, Viewlogic, PAL/GAL, EPLD, CPLD, simulation, synthesis, Vendors(Xilinix, Lattice, Altera, ATEL, ATMEL ....) HDL, ABEL Anybody want to add to this list? -- Edwin Tsang, Email:edwint@bnr.ca , NORTEL Opinion is mine only and I reserved the right to change itArticle: 2671
Brian Childs <brian@vizef.demon.co.uk> writes: > I also agree with this trend. In fact it is already here... You only > have to look at the companies who used to (and probably still do) > provide custom design services, who now publish/market an extensive > range of 'off the shelf cores'. This is because whenever a design shop designs a chip for one customer, its elements then become potential "off the shelf cores" for the next customer. Problem is, the actual level of circuit re-use is always lower than one hopes. Rule of thumb -- if you can get by with less than half of a design being newly-designed circuitry, you're doing really well. If the design shop is accumulating large numbers of "off the shelf cores" it's a good bet they are desinging these things anew for each customer and that is why they have so many of them. > What appears to be missing is any good > design tools to assist designers (or do you know different). We've been saying this for the last 15 years. :) SteveArticle: 2672
In article <BENEDETT.96Jan19105901@iago.dsi.unimo.it>, benedett@dsi.unimo.it (Arrigo Benedetti) wrote: >Does anyone know if Steven Casselman's Virtual Computer Corporation >is still alive? > >Thanks in advance, > >-Arrigo Benedetti Try Virtual Computer Corporation 6925 Canby Ave #103 Reseda, CA teL: 818-342-8294 fax: 818-342-0240 John Schewel, VP Marketing & Sales jas@vcc.com mark -- mark stephens "In constraint, NASA GSFC Code 521 is freedom" Greenbelt, MD (301) 286-4269 mark.stephens@gsfc.nasa.govArticle: 2673
Very interesting. I had to change 'input' and 'output' because
Cadence Verilog-XL considers them reserved keywords. And I added
a $monitor statement to see what went on. So I got:
> Highest level modules:
> test
>
> 0 inputa = 0, outputa = 0
> 10 inputa = 1, outputa = 0
> 11 inputa = 0, outputa = 0
> 20 inputa = 0, outputa = 1
> 19 simulation events
> CPU time: 0.3 secs to compile + 0.2 secs to link + 0.0 secs in simulation
> End of VERILOG-XL 2.2.1 Jan 22, 1996 14:11:05
Is this result because once the output = 1 is scheduled
at time 20, the output = 0 which would occur at time 16 isn't
scheduled because there's already a later event scheduled?
In fact gate-level event-driven simulators I've used in the
past used an "inertial delay" model which would basically
swallow input pulses that were shorter than the propagation
delay of the gate. Since that's roughly what the real
gate would really do. Such a simulator would never pass a 1
to the output with that stimulus.
--Mike
--
Mike Butts, Portland, Oregon mbutts@netcom.com
Article: 2674Hi All, I am using the windows based XACT (step) tools, and have found them to be a little "flaky", with occasional lockups and crashes -- in particular the Design Editor (V5.2.0). This version has run fine from DOS, but the need for simulation has forced me to use the Windows tools. One particular problem -- XDE doesn't always seem to generate the same bitstream each time DebugLoad is run. The machine has been OK in the past, and I have tried both QEMM and HIMEM, with no observable difference. The problem occurs 1-5 times per day. Has anyone else, in particular anyone who depends on these tools found Ver 6.0.0 to be flaky ? -- Gavin Melville, gavin@cypher.co.nz
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