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FWIW, I didn't have a problem installing it on a Dell machine w/ 2 AMD Opteron 64-bit running RH Enterprise 3. Jim "Rudolf Usselmann" <russelmann@hotmail.com> wrote in message news:d37v3o$2dq$1@nobel.pacific.net.sg... > > It's been now several weeks since the release of 7.1. However > I still have not seen a "fix" that would allow us to install > ISE 7.1 on 64 bit platforms: > > [rudi@cpu10 ISE71i_DesignEnv_lin64]$ ./setup > /home/tmp/7.1/ISE71i_DesignEnv_lin64/platform/lin64/bin/lin64 > /home/tmp/7.1/ISE71i_DesignEnv_lin64/platform/lin64/xilsetup: Symbol > `_XtperDisplayList' causes overflow in R_X86_64_PC32 relocation > /home/tmp/7.1/ISE71i_DesignEnv_lin64/platform/lin64/xilsetup: Symbol > `_XtGetPerDisplayInput' causes overflow in R_X86_64_PC32 relocation > Wind/U Error (294): Unable to install Wind/U ini file > (/home/tmp/7.1/ISE71i_DesignEnv_lin64/platform/lin64/data/WindU). > See the Wind/U manual for more details on the ".WindU" file and the "WINDU" > environment variable. > /home/tmp/7.1/ISE71i_DesignEnv_lin64/platform/lin64/setup: line 163: 19510 > Segmentation fault (core dumped) $setuploc/xilsetup $switch $batchfile > > > ************ setup done! *************** > > Will xilinx ever release a setup program that works, or do we > have to wait for 7.2 ? > > Thanks, > rudi > ============================================================= > Rudolf Usselmann, ASICS World Services, http://www.asics.ws > Your Partner for IP Cores, Design, Verification and SynthesisArticle: 82251
"vax, 9000" <vax9000@gmail.com> wrote in message news:d36s7p$7nn$1@charm.magnus.acs.ohio-state.edu... > I am a newbie and I need rules to assign pins to FPGA. I would imagine some, > > 1. Group signals that are natually related, and assign them to the same I/O > bank/side of the FPGA; This is the way to go. You need to watch out for SSO though. > 2. Let the software to assign pins, then fix some pins according to the > automatic assignment, then let the software run again. Do this iteratively > for several times. No, do not do this. JimArticle: 82252
> FWIW, I didn't have a problem installing it on a Dell machine w/ 2 AMD > Opteron 64-bit running RH Enterprise 3. I thought, Dell just sells Intel ? ;-) ThomasArticle: 82253
On Sat, 9 Apr 2005 11:18:30 -0400, "Jim Wu" <nospam@nospam.com> wrote: >FWIW, I didn't have a problem installing it on a Dell machine w/ 2 AMD >Opteron 64-bit running RH Enterprise 3. I think you're confused. Are you sure it's a Dell machine with AMD Opterons ? Or do you mean a Dell machine with two cpus supporting AMD64 extensions from Intel ?Article: 82254
is there anybody knows? thanks a lot!Article: 82255
Eric Smith wrote: > I wrote: > > What MIPS invented and patented was the idea that instead of having the > > hardware deal with unaligned bus accesses, they require software to > > issue *two* instructions to do an unaligned access. One does the > > "left part" and one does the "right part" of the word. > Everett M. Greene writes: > > This must be a misstatement or it's a ridiculous patent. > > How can a patent be issued for NOT doing something? > Of course you can patent something new that eliminates the need > for something old! > The patent is on the two instructions, and their use in eliminating > the need for the usual hardware that would support unaligned access. This certainly does make sense. There definitely is prior art for computers that do not support unaligned access to memory; the System/360 comes to mind. And they can handle unaligned operands, but it takes at least four instructions: A 5,ALIGNED becomes, say LH 6,UALIGNED SLL 6,16 IH 6,UALIGNED+2 A 5,6 or even LC 6,UALIGNED SLL 6,24 L 7,UALIGNED+1 SR 7,8 N 7,#X'00FFFFFF' O 6,7 A 5,6 so if the MIPS speeds things up by having a "fetch left half of n bytes" followed by "fetch right half of N-n bytes, then perform the operation" instructions (as a RISC chip, it might not have the 'perform the operation' part) it has indeed done something new. John SavardArticle: 82256
jsavard@ecn.ab.ca writes:
> And they can handle unaligned operands, but it takes at least four
> instructions:
>
> A 5,ALIGNED
>
> becomes, say
>
> LH 6,UALIGNED
> SLL 6,16
> IH 6,UALIGNED+2
> A 5,6
>
> or even
>
> LC 6,UALIGNED
> SLL 6,24
> L 7,UALIGNED+1
> SR 7,8
> N 7,#X'00FFFFFF'
> O 6,7
> A 5,6
ICM was introduced with 370 ... insert character under mask
ICM 6,B'1111',UNALIGNED
ar 5,6
problem with LH was that it was arithmetic (not logical) and
propogated the sign bit (and it required half-word alignment).
--
Anne & Lynn Wheeler | http://www.garlic.com/~lynn/
Article: 82257"Robert Baer" <robertbaer@earthlink.net> wrote in message news:KzG5e.2943$An2.1588@newsread2.news.pas.earthlink.net... > ...and, pray tell, how do you get to that conclusion? > Every time one generates a document or a pattern (in this case the > codes, masks, etc), such items *by FEDERAL law* are copyrighted! > In fact, your missive to this NG, and my answer here is copyrighted! > Now, if anyone wanted to make some lawyers rich and go to court over > mis-use of copyrighted material, then copyright *registration* would be > considered as the ultimate proof that judges cannot go against. Hey Robert, Just a quick reminder that not everyone in this newsgroup is an American. I'm led to believe that some of the contributors here actually live in foreign countries. Apparently, these godforsaken places have their own laws, and even the FEDERAL government has no jurisdiction. Crazy or what! Cheers, Syms. p.s. One of these far off places is called the UK, or something like that. It seems copyright there is similar to copyright in the US. I imagine the buggers copied the law from the US. http://www.patent.gov.uk/copy/definition.htmArticle: 82258
hi, How do I setup my MicroBlaze design to use XMDStub for debugging my embedded design?I am using virtex-II pro ML310 platform and EDK 6.3. When I am creating a new system with microblaze i come to an option : Processor Confirguration debug I/F 1.on chip H/W debug module 2.XMD with S/W debug stub 3.no debug I choose XMD with S/W debug stub.Then later on after i write the code for my design and have to intilize the bram,Should i initialize it with my executable code or the xmdstub or both? thanx.Article: 82259
Eric Smith wrote: > Ray Andraka wrote about reverse-engineering ASICs based on behavior vs. > analyzing the mask layout: >> it may take a bit of work to ferret out all the operation, but it is >> likely still easier than trying to reverse engineer from masks. > > Speaking of such things, I have a number of old chips from which I want > to extract masked ROM and PLA contents from. Since those are very > regular strutures, and they in parts with single layer metal in 5 micron > and larger geometry, it should be fairly easy. In fact, here's an > example of someone doing this: > http://www.pmonta.com/calculators/hp-35/ This seems to have emerged from another newsgroup so the context of the original question is not clear. However, I think that those who need to perform reverse engineering of anything (and I have done more than my fair share of it - by neccessity) should be on clear ground as far as IP issues are concerned. My own reverse engineering work was always for a client who owned the equipment and IP rights but had lost the documentation for systems that needed to be modified. If you are doing it for reasons other than that then the wicket is getting very sticky. -- ******************************************************************** Paul E. Bennett ....................<email://peb@amleth.demon.co.uk> Forth based HIDECS Consultancy .....<http://www.amleth.demon.co.uk/> Mob: +44 (0)7811-639972 Tel: +44 (0)1235-811095 Going Forth Safely ....EBA. http://www.electric-boat-association.org.uk/ ********************************************************************Article: 82260
Seems like I gave you a bad URL. Try this one: http://www.te.rl.ac.uk/esdg/atlas-flt/talks/StockholmXilinx.pdf. Peter AlfkeArticle: 82261
Has anyone investigated implementimg neural nets in FPGAs?Article: 82262
No, no-one has. That's why when you put 'neural nets fpga' into Google, you get no hits whatsoever. Apart from the first 10000, that is. Syms. "e" <e@yahoo.com> wrote in message news:WKudnX4QIdcO9sXfRVn-ig@adelphia.com... > Has anyone investigated implementimg neural nets in FPGAs?Article: 82263
Never done this myself and I'm not sure of the answer even after reading the xmd part of the manual. Why not use MDM--I use that all the time and it avoids the whole sw stub issue? Paul kittyawake@gmail.com wrote: > > hi, > How do I setup my MicroBlaze design to use XMDStub for debugging my > embedded design?I am using virtex-II pro ML310 platform and EDK 6.3. > When I am creating a new system with microblaze i come to an option : > Processor Confirguration > debug I/F > 1.on chip H/W debug module > 2.XMD with S/W debug stub > 3.no debug > I choose XMD with S/W debug stub.Then later on after i write the code > for my design and have to intilize the bram,Should i initialize it with > my executable code or the xmdstub or both? > > thanx.Article: 82264
kittyawake@gmail.com wrote in news:1113076705.654974.7640 @g14g2000cwa.googlegroups.com: > hi, > How do I setup my MicroBlaze design to use XMDStub for debugging my > embedded design?I am using virtex-II pro ML310 platform and EDK 6.3. > When I am creating a new system with microblaze i come to an option : > Processor Confirguration > debug I/F > 1.on chip H/W debug module > 2.XMD with S/W debug stub > 3.no debug > I choose XMD with S/W debug stub.Then later on after i write the code > for my design and have to intilize the bram,Should i initialize it with > my executable code or the xmdstub or both? I believe you should mark the xmdstub so it will be initialized into the BRAM. Once you download to the FPGA, the xmdstub starts executing and I think it looks for debug commands arriving through the serial port. You can use your debugger to download your application code through the serial port. I've never actually done it, so I stand to be corrected. > > thanx. > > -- ---------------------------------------------------------------- Dave Van den Bout XESS Corp. PO Box 33091 Raleigh NC 27636 Phn: (919) 363-4695 Fax: (801) 749-6501 devb@xess.com http://www.xess.comArticle: 82265
Bret Wade wrote: > Rudolf Usselmann wrote: >> >> Just a short note of caution .... >> >> After installing sp1 for ise 7.1 (linux) mapper is crashing: >> >> map -p xc4vlx25-sf363-10 -timing -register_duplication -pr b -o >> usb_top_map.ncd usb_top.ngd usb_top.pcf >> Release 7.1.01i - Map H.39 >> Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. >> Using target part "4vlx25sf363-10". >> Mapping design into LUTs... >> Writing file usb_top_map.ngm... >> Running directed packing... >> Running delay-based LUT packing... >> Running timing-driven packing... >> >> Phase 1.1 >> Phase 1.1 (Checksum:9e05bf) REAL time: 8 secs >> >> <SNIP> >> >> Phase 14.5 >> Phase 14.5 (Checksum:8583af2) REAL time: 5 mins 23 secs >> >> Invoking physical synthesis ... >> Abort (core dumped) >> >> Regards, >> rudi >> ============================================================= >> Rudolf Usselmann, ASICS World Services, http://www.asics.ws >> Your Partner for IP Cores, Design, Verification and Synthesis >> >> > > This problem can be avoided if you turn off that new > "-register_duplication" feature. > > Bret Bret, Before sp1, "-register_duplication" helped me meet timing when IO buffer registers needed to be duplicated. Do you know of another work around ? Thanks, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 82266
So I got ISE 7.1 on an old 32 bit box up and running. But now when I am trying to use EDK, I get: cpu08:~/projects/xsys/system_lx_66m_64k >xps $XILINX does not point to an iSE 6.3 installation Press enter to close. As far as I know there is no update for EDK (yet). Thanks, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 82267
"Rudolf Usselmann" <russelmann@hotmail.com> schrieb im Newsbeitrag news:d3aaet$105$2@nobel.pacific.net.sg... > > So I got ISE 7.1 on an old 32 bit box up and running. But now > when I am trying to use EDK, I get: > > cpu08:~/projects/xsys/system_lx_66m_64k >xps > $XILINX does not point to an iSE 6.3 installation > > Press enter to close. > > As far as I know there is no update for EDK (yet). > > Thanks, > rudi >============================================================= >Rudolf Usselmann, ASICS World Services, http://www.asics.ws >Your Partner for IP Cores, Design, Verification and Synthesis Dead mr Usselman it ist is very important to use same version of ISE and EDK EDK 6.3 will defenetly not work with ISE 7.1 you need to obatain EDK 7.1 to use ISE 7.1 anttiArticle: 82268
On Sat, 9 Apr 2005 18:17:18 -0700, "Symon" <symon_brewer@hotmail.com> wrote: >No, no-one has. That's why when you put 'neural nets fpga' into Google, you >get no hits whatsoever. Apart from the first 10000, that is. >Syms. More importantly, has anybody found a use for neural nets? JohnArticle: 82269
Hi as of Xfest2005 special Memec is offering S3 based development boards at special price $295 to our best knowledge S3E are not yet available, so how come its possible to get S3E based board at the Xtest? the first xfest is scheduled 26 April, does memec really have S3e based boards ready to ship by then or is business as usual, shipment 4 to 6 months after order? I am really confused, all our inquires have gotten the same result, NO S3E available until end of the year. And now S3E boards announced? I guess Memec will just take orders and ship whenever they get the chips. What means that there is no reason to order from Memec as better boards may be announced before Memec is actually shipping any S3E based board. Similar story was with V4, I ordered the very first announced 'orderable' V4 kit (from Avnet) but before that kit was shipped a lot of more better value V4 kits did become available. So I would wait with S3E order from Memec, specially the price wonders me, the S3E kit special is $295, while normal price is $885 !!!! 900 box for the eval board for the lowest cost FPGA ever?? Good way to go Memec!! Ok the price I figured out, memec is not selling the board, but is selling the board and ISE-baseX so at xfest they drop baseX price, that is the board is not actually at special price at all, you just get ISE baseX as bonus. haha, I checked Memec prices S3E kit alone 99 USD S3E kit + ise BaseX 695 USD orders can be placed now! but... beware in the memec reference design centre there are no docs on the S3E boards yet, and I am guessing memec can not ship immediatly any S3E boards, but at $99 price it makes sense to place order of course! and yes on the Product brief of the S3E board the marking on the S3E chip is not readable at all, even though I think it might be readable at the given JPEG resolution, so either the chip is 'blurred' or the JPEG compression ratio was choosen so that the marking is not readable. poor guys who order the board of $99 value Xfest special for $295 !! (I mean those who do not need BaseX otherwise the deal would be ok) Antti PSArticle: 82270
They can supply them for the same reason Xilinx can supply them in July. Their is production versions.. and there are pre-release versions. I am actually on the Xilinx list.. their board costs only a fraction more and does a lot more (with a bigger FPGA too) Simon "Antti Lukats" <antti@openchip.org> wrote in message news:d3aedf$834$05$1@news.t-online.com... > Hi > > as of Xfest2005 special Memec is offering S3 based development boards at > special price $295 to our best knowledge S3E are not yet available, so how > come its possible to get S3E based board at the Xtest? the first xfest is > scheduled 26 April, does memec really have S3e based boards ready to ship by > then or is business as usual, shipment 4 to 6 months after order? I am > really confused, all our inquires have gotten the same result, NO S3E > available until end of the year. And now S3E boards announced? I guess Memec > will just take orders and ship whenever they get the chips. What means that > there is no reason to order from Memec as better boards may be announced > before Memec is actually shipping any S3E based board. > > Similar story was with V4, I ordered the very first announced 'orderable' V4 > kit (from Avnet) but before that kit was shipped a lot of more better value > V4 kits did become available. So I would wait with S3E order from Memec, > specially the price wonders me, the S3E kit special is $295, while normal > price is $885 !!!! 900 box for the eval board for the lowest cost FPGA > ever?? Good way to go Memec!! > > Ok the price I figured out, memec is not selling the board, but is selling > the board and ISE-baseX so at xfest they drop baseX price, that is the board > is not actually at special price at all, you just get ISE baseX as bonus. > > haha, I checked Memec prices > S3E kit alone 99 USD > S3E kit + ise BaseX 695 USD > > orders can be placed now! > but... beware in the memec reference design centre there are no docs on the > S3E boards yet, and I am guessing memec can not ship immediatly any S3E > boards, but at $99 price it makes sense to place order of course! > and yes on the Product brief of the S3E board the marking on the S3E chip is > not readable at all, even though I think it might be readable at the given > JPEG resolution, so either the chip is 'blurred' or the JPEG compression > ratio was choosen so that the marking is not readable. > > poor guys who order the board of $99 value Xfest special for $295 !! (I mean > those who do not need BaseX otherwise the deal would be ok) > > Antti > PS > >Article: 82271
While browsing ebay I came across this - http://cgi.ebay.co.uk/ws/eBayISAPI.dll?ViewItem&category=11223&item=5766178884&rd=1 Its a Spartan xl on a PCI board, and thats about all I know about it. It has no dedicated PCI interface IC, and I'm *really* not up to writing my own, so I thought I'd post it here for the benefeit of anyone who fancies a play around with one of these. I couldn't find much info about them, and the seller didnt bother emailing me back when I asked him for some, so yeah. I suppose it might be good for some of the hobbyists on here.Article: 82272
"Simon Peacock" <nowhere@to.be.found> schrieb im Newsbeitrag news:4258cef6@news2.actrix.gen.nz... > They can supply them for the same reason Xilinx can supply them in July. > Their is production versions.. and there are pre-release versions. > I am actually on the Xilinx list.. their board costs only a fraction more > and does a lot more (with a bigger FPGA too) > Simon oh yes I can belive that! I mean that the Xilinx board is better and just little more expensive. well avnet similar to memec board is only $69 for that price, oh well its not available as well. until august I guess. did you mean the pre-production silicon of S3E is available now? I wonder why then both memec and avnet are using such image resolution that the Spartan3e can not be read from the S3E board photos. still having photos of eval kits with chips on it, and knowing that those boards will not be shipped before august, it is not fair. Both avnet and memec have 'order now' buttons on the S3E boards. Antti > "Antti Lukats" <antti@openchip.org> wrote in message > news:d3aedf$834$05$1@news.t-online.com... > > Hi > > > > as of Xfest2005 special Memec is offering S3 based development boards at > > special price $295 to our best knowledge S3E are not yet available, so how > > come its possible to get S3E based board at the Xtest? the first xfest is > > scheduled 26 April, does memec really have S3e based boards ready to ship > by > > then or is business as usual, shipment 4 to 6 months after order? I am > > really confused, all our inquires have gotten the same result, NO S3E > > available until end of the year. And now S3E boards announced? I guess > Memec > > will just take orders and ship whenever they get the chips. What means > that > > there is no reason to order from Memec as better boards may be announced > > before Memec is actually shipping any S3E based board. > > > > Similar story was with V4, I ordered the very first announced 'orderable' > V4 > > kit (from Avnet) but before that kit was shipped a lot of more better > value > > V4 kits did become available. So I would wait with S3E order from Memec, > > specially the price wonders me, the S3E kit special is $295, while normal > > price is $885 !!!! 900 box for the eval board for the lowest cost FPGA > > ever?? Good way to go Memec!! > > > > Ok the price I figured out, memec is not selling the board, but is selling > > the board and ISE-baseX so at xfest they drop baseX price, that is the > board > > is not actually at special price at all, you just get ISE baseX as bonus. > > > > haha, I checked Memec prices > > S3E kit alone 99 USD > > S3E kit + ise BaseX 695 USD > > > > orders can be placed now! > > but... beware in the memec reference design centre there are no docs on > the > > S3E boards yet, and I am guessing memec can not ship immediatly any S3E > > boards, but at $99 price it makes sense to place order of course! > > and yes on the Product brief of the S3E board the marking on the S3E chip > is > > not readable at all, even though I think it might be readable at the given > > JPEG resolution, so either the chip is 'blurred' or the JPEG compression > > ratio was choosen so that the marking is not readable. > > > > poor guys who order the board of $99 value Xfest special for $295 !! (I > mean > > those who do not need BaseX otherwise the deal would be ok) > > > > Antti > > PS > > > > > >Article: 82273
<randomdude@gmail.com> schrieb im Newsbeitrag news:1113116098.971629.81660@l41g2000cwc.googlegroups.com... > While browsing ebay I came across this - > > http://cgi.ebay.co.uk/ws/eBayISAPI.dll?ViewItem&category=11223&item=5766178884&rd=1 > > Its a Spartan xl on a PCI board, and thats about all I know about it. > It has no dedicated PCI interface IC, and I'm *really* not up to > writing my own, so I thought I'd post it here for the benefeit of > anyone who fancies a play around with one of these. > I couldn't find much info about them, and the seller didnt bother > emailing me back when I asked him for some, so yeah. I suppose it might > be good for some of the hobbyists on here. Spartan XL is not supported any more by Xilinx (not from the mainline tools) so while $49 is good price for PCI-FPGA board bying anythign with spartan-XL means that you need to use antique software for development, and that all does not make sense any more. cheapest PCI-FPGA board (and a very nice board) is MAX2 Starterkit from Altera that board costs $150 and has lot more than just PCI on board and comes with full documentation and sure can be used with latest Altera Software AnttiArticle: 82274
leexiaofat@eyou-dot-com.no-spam.invalid (leexiaofat) writes: > is there anybody knows? You can order it from Xilinx.
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