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Messages from 82100

Article: 82100
Subject: Re: Single Event Functional Interrupts (SEFI) in Virtex
From: Austin Lesea <austin@xilinx.com>
Date: Wed, 06 Apr 2005 14:14:27 -0700
Links: << >>  << T >>  << A >>
Praveen,

You have the paper, and the modes discovered, and the work-arounds.

There is a lot of work on-going by the mil/aero community on radiation 
testing.  Perhaps your company would consider joining the radiation 
effects consortium that we sponsor (if you have need for this)?

Austin

Article: 82101
Subject: LVDS PCI card is needed
From: "soos" <marcsok@yahoo.com>
Date: 6 Apr 2005 14:17:43 -0700
Links: << >>  << T >>  << A >>
Hello,

As a part of a project I am looking for a FPGA on PCI that has 8 LVDS
channels and the driver of this card that enables all the 8 channels of
read and write.

Total data transfer capacity is 200-400 Mbps.

Questions are:

1.Is this data rate achievable?
2.Can anyone point a solution for this design?

Any help will be appreciated,
Thanks in advance,
Marc.


Article: 82102
Subject: Re: LVDS PCI card is needed
From: Austin Lesea <austin@xilinx.com>
Date: Wed, 06 Apr 2005 14:42:12 -0700
Links: << >>  << T >>  << A >>
Marc,

http://www.acromag.com/parts.cfm?Model_ID=313&Product_Function_ID=5&Category_ID=4&Group_ID=1

Sells a number of PCI cards with Virtex II FPGAs which have LVDS IO for 
user access.

The LVDS IO in Virtex II will do 800 Mbs with DDR on one LVDS IO pair.

A 33 MHz 32 bit PCI bus is ~ 1Gbs of data transfer bandwidth.

I think what you ask is pretty easy (on the hardware side).

Now on the software driver side, that is what would scare me.

Austin

Article: 82103
Subject: Re: CPLD: collapse
From: "Jan Bruns" <post@abnuto.de>
Date: Thu, 7 Apr 2005 00:14:25 +0200
Links: << >>  << T >>  << A >>
"Kar":
> By looking at your code. It is an synchronous design. CPLD will not
> gives good performance for asynchronous design because of their
> architectures.

> If possible, you should try clock enable signal instead of directly
> drive the register's clk.


Hmja. 

clk = ATA udma_in_dev_strobe && ATA_PIO_in_strobe;
ce = strobeenable;  // ATA udma_in_dev_strobe is multiplexed with "IORDY"

is not exactly what I planned to implement, but solved the problem.

Gruss

Jan Bruns


Article: 82104
Subject: Xilinx ISE 7.1i / stuck down XCR3064 outputs
From: "Alex" <alex@dnlnk.com>
Date: 6 Apr 2005 15:21:35 -0700
Links: << >>  << T >>  << A >>
Hi,

I'm trying to use Xilinx ISE 7.1 on Linux to target an XCR3064.
What seemed to happen was any pin configured as an output was stuck
down to ground (able to draw 30mA) This happens even if the pins are
internally connected (thru an obuf) to VCC or set to 1 in the design.
Pins configured as input seems to work correctly.. high impedance and
doing a sort of a floating latch behavior.

I assumed the chip was blown (dead bug wired VQ44), and get a Digilent
XCR demo board.  Works great with the program it came with, no go with
anything I try to create.  I load the JEDEC I extracted from it, back
into it by way of Impact... works fine.

Their example code (xcrdemo.vhd and xcrdemo.ucf from
https://www.digilentinc.com/Data/Products/DXCR/DXCR-demo.zip)  compiles
and fits fine, programs and verifies fine, but no lights/doesn't work!

Their example code compiles and fits fine on a Windows machine with
ISE4.2WPO.  I take the JEDEC file created on the 4.2 machine back to
Impact on the Linux/ISE7.1 machine, and I've got lights again.

If I take the .ngd file from 7.1 Linux and try to generate a .jed file
on the 4.2 Windows, I get weird "can't read memory" errors.

If I take the .ngd file from 4.2 Windows and generate a .jed file on
the Linux machine, it seems fine, but NO LIGHTS!

This ISE 7.1/Linux machine generates working .bit files for a XC2S200E
FPGA.

Thanks for any help,

Alex

alex at dee en el en kay dot com


Article: 82105
Subject: Re: Open PowerPC Core?
From: Jeremy Stringer <jeremy@_NO_MORE_SPAM_endace.com>
Date: Thu, 07 Apr 2005 11:23:03 +1200
Links: << >>  << T >>  << A >>
Alex Freed wrote:
> Not being a top authority on soft core I'll still observeve that:
> 
> 1. Implementing a CISC CPU is much more resource consuming than implementing
> a RISC core.
> 2. x86 is way crazy because of the need to maintain compatibility with the
> 8086's real mode.
> 
> In late 80's Intel made a special version of 386 (385 if I remember right)
> that was basically a 368 without  the real mode.
> It was much cheaper than a 386 but there were no takers: x86 is used so much
> only because of the huge volume of written code,
> not because it is a good architecture.

I wonder whether an x86 type replacement could be done in a different 
way - instead of implementing an x86, implement a simpler RISC type 
architecture, and translate the code off line in software.  At least 
some of the x86 family used microcode AFAIK, so this could be feasible.

If the code is well written (no self modifying code), this might 
actually do what a x86 soft-core would actually want to do.

Mind you, still a lot of functionality where that wouldn't work, but 
from a purely instruction set point of view, this could maybe work.

Just an idea.

Jeremy

Article: 82106
Subject: Re: Xilinx ISE 7.1i / stuck down XCR3064 outputs
From: "Ross Marchant" <rossm@NOexcelSPAMtech.com.auSTRALIA>
Date: Thu, 7 Apr 2005 09:24:49 +1000
Links: << >>  << T >>  << A >>
"Alex" <alex@dnlnk.com> wrote in message
news:1112826095.036718.103170@l41g2000cwc.googlegroups.com...
> Hi,
>
> I'm trying to use Xilinx ISE 7.1 on Linux to target an XCR3064.
> What seemed to happen was any pin configured as an output was stuck
> down to ground (able to draw 30mA) This happens even if the pins are
> internally connected (thru an obuf) to VCC or set to 1 in the design.
> Pins configured as input seems to work correctly.. high impedance and
> doing a sort of a floating latch behavior.
>
> I assumed the chip was blown (dead bug wired VQ44), and get a Digilent
> XCR demo board.  Works great with the program it came with, no go with
> anything I try to create.  I load the JEDEC I extracted from it, back
> into it by way of Impact... works fine.
>
> Their example code (xcrdemo.vhd and xcrdemo.ucf from
> https://www.digilentinc.com/Data/Products/DXCR/DXCR-demo.zip)  compiles
> and fits fine, programs and verifies fine, but no lights/doesn't work!
>
> Their example code compiles and fits fine on a Windows machine with
> ISE4.2WPO.  I take the JEDEC file created on the 4.2 machine back to
> Impact on the Linux/ISE7.1 machine, and I've got lights again.
>
> If I take the .ngd file from 7.1 Linux and try to generate a .jed file
> on the 4.2 Windows, I get weird "can't read memory" errors.
>
> If I take the .ngd file from 4.2 Windows and generate a .jed file on
> the Linux machine, it seems fine, but NO LIGHTS!
>
> This ISE 7.1/Linux machine generates working .bit files for a XC2S200E
> FPGA.
>
> Thanks for any help,
>
> Alex
>
> alex at dee en el en kay dot com
>

I have a problem where ISE 7.1.01i inverts all the outputs on my XC95108. I
opened a web case and Xilinx said that it was an issue with the jedec
generation and to go back to ISE 6.3.

Ross



Article: 82107
Subject: Re: EDK-Creating new peripheral
From: "beeraka@gmail.com" <beeraka@gmail.com>
Date: 6 Apr 2005 16:34:16 -0700
Links: << >>  << T >>  << A >>
Hi,
     The only way I guess that you can write to your own IP is through
registers..When u invoke the Create/Import Peripheral Wizard ..It gives
you an option of creating few User Registers ..U can write to these
registers ..and after u do some computation ..u can also read back from
these registers ...And regarding the drivers that u were talking about
..they are automatically genereated in case u r using EDK 6.3 ( I dunno
about other versions ..) .. In case if ur r using EDK ..When u say
Generate Libraries after ur core included in the EDK ..then there will
be a folder called "drivers" in ur project directory ... in that u will
have simple functions to read and write to registers ...or else u can
write your own code to read and write registers that's not a big deal
at all.. So I guess I can u give u all the steps to add your own core
in EDK ..but I am assuming that u have already done that ..So let me
know in case u have any questions ..

--
Parag Beeraka


Article: 82108
Subject: Re: Modelsim simulations without ISE
From: "Jim Wu" <nospam@nospam.com>
Date: Wed, 6 Apr 2005 19:58:05 -0400
Links: << >>  << T >>  << A >>

"gallen" <arlencox@gmail.com> wrote in message
news:1112815463.918393.31960@g14g2000cwa.googlegroups.com...
> I'm trying to do some simulations in modelsim that use one of the
> xilinx libraries (Specificially the RAMB4_S4_S4), but when I don't
> include the source to that I get an error:
>
> C:/Modeltech_xe_starter6/xilinx/verilog/src/unisims/RAMB4_S4_S4.v(651):
> Unresolved reference to 'glbl' in glbl.GSR
>
> I know that the file glbl.v exists (in my case it's in
> C:\Modeltech_xe_starter6\xilinx\verilog\src\glbl.v), but I don't know
> how to make modelsim aware of this file and to use it so that I can
> simulate the block RAMs.  Does anyone elase know how to make modelsim
> work without having initiated it from within ISE?

vlog glbl.v
vsim work.your_test_bench work.glbl

HTH,
Jim
jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips



Article: 82109
Subject: Re: Modelsim simulations without ISE
From: "Praveen" <sams235@gmail.com>
Date: 6 Apr 2005 17:17:05 -0700
Links: << >>  << T >>  << A >>
I did similar kind of thing a few years back with NCLaunch. what you
need to do is compile the package file (in your case the glbl.v) file
in to your work directory. Then refer to those files from your file
(like use work.all).


Article: 82110
Subject: Re: Modelsim simulations without ISE
From: "Praveen" <sams235@gmail.com>
Date: 6 Apr 2005 17:49:47 -0700
Links: << >>  << T >>  << A >>
This doc has it all..

http://www.sital.co.il/pdf/Xilinx_Vlg_gtl_HDS.pdf

cant believe I used the same doc 4 yrs back!


Article: 82111
Subject: Hey Xilinx
From: Quiet Desperation <nospam@nospam.com>
Date: Wed, 06 Apr 2005 17:52:32 -0700
Links: << >>  << T >>  << A >>
Any chance of there ever being an FPGA where one or more of the
SelectRAM blocks is nonvolatile?

I design a lot of stuff that is programmable and reconfigurable beyond
the FPGAs. I commonly need to store the setting of digital delay chips
and switch settings and other control lines so that a unit powers up
with everything in the state desired by the end user. 

Currently I use little automotive serial EEPROMs, but, dang but it'd be
nice to have a little EEPROM inside an FPGA. Just one 18Kbit block
would do wonders.

Article: 82112
Subject: Re: VHDL to schematic conversion
From: "Robert" <schop@veritools.com>
Date: 6 Apr 2005 17:52:35 -0700
Links: << >>  << T >>  << A >>
I assume what you are looking for is a tool that will take RTL and
create a schematic at the RTL level, or at the gate level with a
netlist, without a synthesis step. If you synthesize it, it will look
totally different then a RTL schematic of the same circuit. You can use
the Undertow Suite source code debugging set of software to do this.
This software is also a fraction of the cost of a synthesis tool, and
is very easy to use. The Undertow Suite will display a schematic of
Verilog, VHDL, mixed Verilog and VHDL and SystemVerilog. You can
download this software from www.veritools.com, and get a no cost
license at request@veritools.com.

Robert Schopmeyer/Veritools, Inc.


khansa wrote:
> Please mention a tool that can accepts VHDL code and converts it into
> a circuit schematic(preferably at the register transfer level or gate
> level). Does ORCAD have such an option?


Article: 82113
Subject: Re: Xilinx ISE 7.1i / stuck down XCR3064 outputs
From: "Alex" <alex@dnlnk.com>
Date: 6 Apr 2005 18:04:29 -0700
Links: << >>  << T >>  << A >>
Thanks...
Wow.  I hope they make a fix availiable.  Can anyone point me to a way
to easily run a working fitter from linux?

I tried out their "webfitter"  It works.. it even makes my design work.
 But I need more control over the software if I'm going to bet my
design future on their parts.

Alex


Article: 82114
Subject: Re: LVDS PCI card is needed
From: "cwoodring" <cwoodring@cox.net>
Date: Wed, 6 Apr 2005 21:17:37 -0400
Links: << >>  << T >>  << A >>
I'm using a PMC module from Transtech DSP that comes with an LVDS buffer 
module. Not cheap but I am using up to 50 LVDS lines as input/output so I 
figured it was better to use a known good buffering/ connector solution. The 
FPGA01, 2, and 3 are pretty good solutions if not exactly cheap.
CTW

"soos" <marcsok@yahoo.com> wrote in message 
news:1112822263.272498.155130@l41g2000cwc.googlegroups.com...
> Hello,
>
> As a part of a project I am looking for a FPGA on PCI that has 8 LVDS
> channels and the driver of this card that enables all the 8 channels of
> read and write.
>
> Total data transfer capacity is 200-400 Mbps.
>
> Questions are:
>
> 1.Is this data rate achievable?
> 2.Can anyone point a solution for this design?
>
> Any help will be appreciated,
> Thanks in advance,
> Marc.
> 



Article: 82115
Subject: Re: Hey Xilinx
From: "Teo" <themarenas@comcast.net>
Date: 6 Apr 2005 18:36:51 -0700
Links: << >>  << T >>  << A >>
There already exists a solution for you.  Lattice has an sram+flash
fpga called the XP.  It has embedded 9k bit block rams that you can
store their entire contents in flash, so when the part starts up it can
be initialized with whatever data you want.
http://www.latticesemi.com/products/fpga/xp/index.cfm


Article: 82116
Subject: xilinx appnote 636
From: "cwoodring" <cwoodring@cox.net>
Date: Wed, 6 Apr 2005 21:39:56 -0400
Links: << >>  << T >>  << A >>
Hi,
    I've been fooling around with the example vhdl for the Xilinx appnote 
636 concerning pipelineing a multiplier. The pdf file accompanying the app 
note is a bit vague on exactly what to do with the example code. I'm having 
an issue with the ucf file in that if I synthesize the top level wrapper 
module for the floorplanned multiplier, and then try to P&R it, I get errors 
in the translate process that claim the wrapped_instantiation  instance is 
not found.
This is the sample file:
l
ibrary ieee;
use ieee.std_logic_1164.all;

entity SAMPLE_WRAPPER_MULT18X18S_PLUS is
 port( A_INPUT, B_INPUT:in std_logic_vector(17 downto 0);
 CLK, RST, CE: in std_logic;
 P_OUTPUT: out std_logic_vector(35 downto 0));
end SAMPLE_WRAPPER_MULT18X18S_PLUS;

architecture SAMPLE_WRAPPER_MULT18X18S_PLUS_BEHAVIOR of 
SAMPLE_WRAPPER_MULT18X18S_PLUS is
component MULT18X18S_PLUS
 port( A_INPUT, B_INPUT:in std_logic_vector(17 downto 0);
 CLK, RST, CE: in std_logic;
 P_OUTPUT: out std_logic_vector(35 downto 0));
end component;

begin

wrapped_instantiation : MULT18X18S_PLUS port map(A_INPUT => A_INPUT, B_INPUT 
=> B_INPUT, CLK => CLK, RST => RST, CE => CE, P_OUTPUT => P_OUTPUT);

end SAMPLE_WRAPPER_MULT18X18S_PLUS_BEHAVIOR;


    When I look at the RTL viewer I see the correct registers and multiplier 
and it all looks right. There are location constraints in the vhdl for the 
SAMPLE_WRAPPER_MULT18X18S_PLUS and the pipelined registers are rloc'ed in 
the ucf file. Well when I ignore the give ucf file and P&R the placement of 
the pipelined registers is nowhere near what the app note shows.

Here is what NgdBuild prints:
Reading NGO file
"C:/Xilinx/myprojects/app636/sample_wrapper_mult18x18s_plus.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file 
"SAMPLE_WRAPPER_MULT18X18S_PLUS.ucf"
...
ERROR:NgdBuild:753 - Line 1 in 'SAMPLE_WRAPPER_MULT18X18S_PLUS.ucf': Could 
not
   find instance(s) 'wrapped_instantiation' in the design.  To suppress this
   error specify the correct instance name or remove the constraint.

and here is what is in the beginnig  of the ucf file:
`
INST "wrapped_instantiation" RLOC_ORIGIN=X2Y0;
INST "wrapped_instantiation/test_mult18x18s" LOC = "MULT18X18_X0Y0";

If I remove the ucf file and do the P&R and then look at the design in the 
FPGA editor, I see the wrapped_instantiation of the multipllier in the 
component list.

      wrapped_instantiation_a_wire<0> SLICE_X6Y6 SLICE 6 15
      wrapped_instantiation_a_wire<2> SLICE_X6Y7 SLICE 6 15
      wrapped_instantiation_a_wire<4> SLICE_X6Y8 SLICE 6 15
      wrapped_instantiation_a_wire<6> SLICE_X6Y9 SLICE 6 15
      wrapped_instantiation_a_wire<8> SLICE_X6Y10 SLICE 6 15
      wrapped_instantiation_a_wire<10> SLICE_X6Y11 SLICE 6 15
      wrapped_instantiation_a_wire<12> SLICE_X6Y12 SLICE 6 15
      wrapped_instantiation_a_wire<14> SLICE_X6Y13 SLICE 6 15
      wrapped_instantiation_a_wire<16> SLICE_X5Y13 SLICE 6 15
      wrapped_instantiation_b_wire<0> SLICE_X8Y6 SLICE 6 15
      wrapped_instantiation_b_wire<2> SLICE_X8Y7 SLICE 6 15
      wrapped_instantiation_b_wire<4> SLICE_X8Y8 SLICE 6 15
      wrapped_instantiation_b_wire<6> SLICE_X8Y9 SLICE 6 15
      wrapped_instantiation_b_wire<8> SLICE_X8Y10 SLICE 6 15
      wrapped_instantiation_b_wire<10> SLICE_X8Y11 SLICE 6 15
      wrapped_instantiation_b_wire<12> SLICE_X8Y12 SLICE 6 15
      wrapped_instantiation_b_wire<14> SLICE_X8Y13 SLICE 6 15
      wrapped_instantiation_b_wire<16> SLICE_X5Y12 SLICE 6 15
      wrapped_instantiation_test_mult18x18s MULT18X18_X0Y1 MULT18X18 75 15


I am new to the FPGA editor and trying to get a handle on how it can be 
used.  Is this happening because the instantiation is in a behaviorial 
architecture?  I figured since the ucf names the wrapped_instantiation as an 
INST I could just use the file the way it was and synthesize it?

Any comments appreciated.

Thanks

CTW 



Article: 82117
Subject: Re: ISA vs. patent/trademark
From: "JJ" <johnjakson@yahoo.com>
Date: 6 Apr 2005 18:58:14 -0700
Links: << >>  << T >>  << A >>
Thanks for clarification, thats okay then!

Perhaps it worth inventing/patenting same idea for exactly 3 & 4 & 5
instructions too:-)

johnjakson at usa dot com
transputer2 at yahoo dot com


Article: 82118
Subject: Re: 80x86 verilog (not complete!) sources released
From: "vax, 9000" <vax9000@gmail.com>
Date: Wed, 06 Apr 2005 22:48:06 -0400
Links: << >>  << T >>  << A >>
Antti Lukats wrote:

> http://gforge.openchip.org/projects/a86/
> 
> I had some working demos for ML300, but the project was iced oct'2004
> the core is not nearly finished, only a subset of commands is working,
> just releasing as it is/was

I didn't find document/readme about the project. Do you have that? Thanks.

vax, 9000

> 
> antti


Article: 82119
Subject: Re: Xilinx ISE 7.1i / stuck down XCR3064 outputs
From: Jim Granville <no.spam@designtools.co.nz>
Date: Thu, 07 Apr 2005 16:10:46 +1200
Links: << >>  << T >>  << A >>
Alex wrote:
> Thanks...
> Wow.  I hope they make a fix availiable.  Can anyone point me to a way
> to easily run a working fitter from linux?
> 
> I tried out their "webfitter"  It works.. it even makes my design work.
>  But I need more control over the software if I'm going to bet my
> design future on their parts.

  These 'school boy' issues with the more mature CPLDs certainly makes 
their testing program look thin/non-existant.
  Perhaps it is all a ploy to move designs to the latest "hot new
thing" - or maybe they have too many ex-microsoft employees ?:)

-jg


Article: 82120
Subject: Re: x86 Core?
From: Tommy Thorn <foobar@nowhere.void>
Date: Thu, 07 Apr 2005 04:31:32 GMT
Links: << >>  << T >>  << A >>
Jeremy Stringer wrote:
> I wonder whether an x86 type replacement could be done in a different 
> way - instead of implementing an x86, implement a simpler RISC type 
> architecture, and translate the code off line in software.  At least 
> some of the x86 family used microcode AFAIK, so this could be feasible.
> 
> If the code is well written (no self modifying code), this might 
> actually do what a x86 soft-core would actually want to do.
> 
> Mind you, still a lot of functionality where that wouldn't work, but 
> from a purely instruction set point of view, this could maybe work.

Many have attempted off-line translation of x86 with varing degree of 
success.  IMHO it's too limited to be useful.

Using dynamic translation a la Transmeta is probably the best way, but 
writing the dynamic translator system is a vast undertaking.

If the goal is to implement a moderate x86 on an FPGA, I suggest 
implementing the subset of 32-bit x86 (or maybe even AMD64) big enough 
to completely run a x86 interpreter, such as Borch, and then trap 
unimplemented instruction and modes and let the interpreter handle them. 
  As long as all of the frequently instructions are handled directly 
performance should be resonable (for a scalar FPGA implementation) and 
the implementation would be vastly simpler than a full x86.

Just another idea,
Tommy

Article: 82121
Subject: Re: Reverse engineering ASIC into FPGA
From: "Neo" <zingafriend@yahoo.com>
Date: 6 Apr 2005 21:50:18 -0700
Links: << >>  << T >>  << A >>
<quote> How do you go about quoting that, or is it by the hour?
If it's by the hour, how do you even give a vague estimate? </quote>
No I dont think its by the hour, more like a package deal with a
ceratain time frame. it dosent have the time to market urgency of a new
product.


Article: 82122
Subject: Re: 80x86 verilog (not complete!) sources released
From: "Antti Lukats" <antti@openchip.org>
Date: Thu, 7 Apr 2005 08:25:19 +0200
Links: << >>  << T >>  << A >>
"vax, 9000" <vax9000@gmail.com> schrieb im Newsbeitrag
news:d326na$nb3$1@charm.magnus.acs.ohio-state.edu...
> Antti Lukats wrote:
>
> > http://gforge.openchip.org/projects/a86/
> >
> > I had some working demos for ML300, but the project was iced oct'2004
> > the core is not nearly finished, only a subset of commands is working,
> > just releasing as it is/was
>
> I didn't find document/readme about the project. Do you have that? Thanks.
>
> vax, 9000
>
> >
> > antti
>
unfortunatly no
there are some simulation testbenches included and scripts to generate fpga
test version, but no real documentation. i should have on other variant that
was actually used on ML300 board, I will add that too, but there isnt much
docu either just an schematic toplevel that binds the cpu core with
peripherals.

antti



Article: 82123
Subject: Re: ISA vs. patent/trademark
From: David <david.nospam@westcontrol.removethis.com>
Date: Thu, 07 Apr 2005 08:51:27 +0200
Links: << >>  << T >>  << A >>
On Wed, 06 Apr 2005 09:23:30 -0700, jsavard wrote:

> I'm sad to hear that there is a patent on the ARM Thumb instruction set
> that extends to the general principle, because something like it is
> what the PowerPC architecture desperately needs - so that people can
> use it the way IBM wants, without compromising the architecture.
> 
> John Savard

There are Freescale (formerly Motorola) PowerPC microcontrollers with code
compression (look for the MPC562 on the Freescale website, for example). 
The do not use an alternative instruction set like the Thumb - instead, it
is a more dynamic compression.  Software utilities compress your
executable and generate tables which you must load into the decompressor's
lookup table ram on startup.  The decompressor is part of the instruction
pre-fetch burst controller, which passes fully decompressed instructions
on to the main cpu core.  This makes it more flexibile than the Thumb
technique, and you get the full power of the core rather than a subset,
but it's more of a hassle to configure (and probably awkward for debugging).


Article: 82124
Subject: Sdram controller on the Altera Cyclone board!
From: "kingkang" <305liuzg@163.net>
Date: Thu, 7 Apr 2005 16:17:10 +0800
Links: << >>  << T >>  << A >>
Hi
I wrote a sdram controller which has pass the RTL simulation.
But when it come to the Altera cyclone board,the read/write
data were wrong.I have written sdram with some data,and then
I read the data from sdram.But found the data is not equal to
what have been written into the sdram.One or Some bits have
wrong.It is random bit error!I don't know what's wrong.About
the clock? or board delay? or else?Please help me out!
Thanks and Regards!





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