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I am not exactly sure what you are suggesting. Are you proposing that there is one boundary-scan TAP connection that goes through the PROM to the FPGA and another that goes directly to the FPGA without involving the PROM? If that this the case, since there is in actuality only one physical TAP on the FPGA, that means there will only be one set of TMS and TCK connections which means that if you are trying to access the FPGA-only TAP you will have the PROM traversing through its state machine and when you try to shift data into the FPGA the PROM TDO will be active and shifting, as well. I suppose you could add some extra control logic to guarantee safe operation of the two TAPs but in the end, why would you? If you have a single chain of a PROM followed by an FPGA you can address either device by BYPASSing the other. You can program the FPGA with a bitstream file with the PROM in BYPASS or program the PROM with an mcs or exo file with the FPGA in BYPASS. Does that help? fpgavhdl@gmail.com wrote: > Can an FPGA have two JTAG ports for programming an FPGA chip? > > One is conected thro XCf02s to the FPGA and the other is directly > connected to the FPGA (XC3S400). > > What is the significance of having two ports? > > What files are used for programming this FPGA thro each of those ports? >Article: 82026
Kai Harrekilde-Petersen wrote: > Eric DELAGE <"eric UNDERSCORE delage AT yahoo DOT fr"> writes: > > >>>Now, that doesnt mean the lawers want come after you, they can try at least. >>>But by being VERY VERY Careful it is possible to make the case a 'no case' >>>for the lawers. But you really have to have a 'clean implementation' - and >>>you have to withstand any pressure from the lawers who try to prove the >>>opposite. >> >>The keypoint, I think, is: are we talking about 1) patents (but the >>ARM ISA is full of instructions developped before it appears) 2) >>trademarks (but as long as no mention/no claim regarding the original >>names are done, would it be ok?) 3) copyright (but if an ISA is a >>language, an someone copyright it?) > > > > Point 1: As for MIPS, the unaligned load/store instructions (i think) > are covered by patents. In order to implement these, you must obtain a > license from MIPS technologies. > > Point 2: For trademark reasons you cannot call a processor for MIPS > compatible or compliant, without implementing the full ISA. Goto > point 1. See also the ST7 family from ST, and the Motorola HC05 series..... > (Infinite loop exception, program aborted). > > That hasn't stopped people from implementing processors with the MIPS > ISA, *except* for the patented instructions. But the people doing > this are very careful about not calling the processor for anything > related to MIPS... I heard that the NIOS II is 'very similar' to MIPS - can anyone who knows both cores in detail comment ? -jgArticle: 82027
Q If some processor that is not any way MIPs like can otherwise perform a register ld/st for a word on any byte boundary is that a problem, or only if the rest of it is MIPs like too. If a processor has a general move n bytes ie mv rd,rs,4 and works on any boundary and any length into memory locations that are also a register, a problem?. Am I not mistaken that most all cpus allowed unaligned ld/st till the RISC religion took over. Guess I will have to look at the patent. johnjakson at usa dot comArticle: 82028
I've got a design using Select Map mode to program a Xilinx V2-Pro part. Many of the boards work, but one has stopped accepting the bit file download. Everything seems to proceed properly, but the DONE signal is never asserted. I can download via JTAG to the part just fine, but it just won't accept the Select Map download. When my code asserts the PGM pin, DONE goes away and INIT is asserted. After a bit, I release PGM, then INIT goes away. All correct so far. I send down the data, but DONE is not asserted at the end. All voltage levels look OK, timing looks fine, plenty of setup/hold time on the data going into the V2-Pro. This board used to work, but at some point decided to be a problem. Also - if I load the FPGA via JTAG, I can run a set of diagnostics using the same 8 bit data bus and the diagnostics pass, ie, my data bus looks to be properly connected. As far as I can tell, the FPGA appears to work perfectly EXCEPT it doesn't like to be downloaded via Select Map. Has anyone else seen problems like this? Is it likely that the FPGA couls be damaged such that it can't accept download data but that the same data pins work fine after the part is programmed via JTAG? The exact same .bit files work fine on other boards. Suggestions? Thanks! John PArticle: 82029
Hallo,
in an CPLD-Design (XC95??XL), I have 2 data-strobe signals,
and a data-stobe-select-signal.
The selected strobe should clock 2*16 input regs:
input [15:0] pinoekels;
reg [15:0] di1;
reg [15:0] di2;
wire strobe = (ssel && s1) || (ssel && s2);
always @(posedge strobe) begin
di1 <= pinoekels;
end
always @(negedge strobe) begin
di2 <= pinoekels;
end
The problem is that "strobe" shouldn't be implemented as
a feedback-signal (too much delay).
It needs to be implemented as 2*16*2 product terms (2 for any single reg).
// synthesis attribute collapse of strobe is yes
doesn't help ("strobe" gets an tool-generated name, that's all).
I'v even tried to explicitly setup the 32FD, 32OR, 64AND2,
using various constraint-combinations and optimisation-goals,
because I felt, the "di" were implemented as FD16-macros somewhere.
No matter waht I've tried, the "strobe" was always implemented
as a feedback-path (or even worse: *many* feedback paths).
Any further ideas?
Isn't there an "XDL for CPLD" somewhere?
Gruss
Jan Bruns
Article: 82030v wrote: > What if you route an IBUFG input pin to a regular BUF?...will the tools > still treat it as global clock? > > No, this net will be routed on local resources. The IBUFGs feed a routing box near the top center and bottom center of the chip, these have connections to the local resources (HEX lines, etc) and these get used. I accidentally ended up doing this once, saw the problem in FPGA editor, then fixed it. If you want to get a clock out of the FPGA, configure the output buffer as a DDR Flip Flop, tie D0 high, D1 low, give your clock to C0 and an inverted version to C1. See XAPP462 for details, it's a very good document on the capabilities of the DCM. -JimArticle: 82031
Manish, There is a option in DCM to release FPGA done once the DCM stabilize. You can use this option also. Even i donot see any problem if LOCK is used as FPGA internal reset. Have fun working, Thanks and Regards PraveenArticle: 82032
"Jan Bruns": > in an CPLD-Design (XC95??XL), These device have only one "product term" for clocks. Sorry. Gruss Jan BrunsArticle: 82033
"Eric DELAGE" <"eric UNDERSCORE delage AT yahoo DOT fr"> wrote in message news:4252c3dc$0$3114$8fcfb975@news.wanadoo.fr... > Hi, > > Are ISA covered by patents or trademarks? Is it allowed to develop a > processor core for a popular ISA as long as no reference is made to any of > the original company trademarks? Many thanks for your comments. > Trademarks cover only product *names*. ISA names can indeed be trademarked, hower that would not prevent anyone from copying/using the architecture. It would only prevent them from selling/promoting/advertising it under the same name as the original. dkArticle: 82034
"johnp" <johnp3+nospam@probo.com> wrote in news:1112744398.572710.3530 @z14g2000cwz.googlegroups.com: > I've got a design using Select Map mode to program a Xilinx V2-Pro > part. Many of the boards work, but one has stopped accepting the > bit file download. Everything seems to proceed properly, but the > DONE signal is never asserted. I can download via JTAG to the > part just fine, but it just won't accept the Select Map download. > > When my code asserts the PGM pin, DONE goes away and INIT is asserted. > After a bit, I release PGM, then INIT goes away. All correct so far. > I send down the data, but DONE is not asserted at the end. Is INIT pulled low at the end? Are the CS, WR and CCLK signals correct during downloading? Are the mode pins set correctly? (These are all inputs and would not be tested by your bus diagnostic.) > > All voltage levels look OK, timing looks fine, plenty of setup/hold > time on the data going into the V2-Pro. This board used to work, > but at some point decided to be a problem. > > Also - if I load the FPGA via JTAG, I can run a set of diagnostics > using the same 8 bit data bus and the diagnostics pass, ie, my > data bus looks to be properly connected. > > As far as I can tell, the FPGA appears to work perfectly EXCEPT it > doesn't like to be downloaded via Select Map. > > Has anyone else seen problems like this? Is it likely that the > FPGA couls be damaged such that it can't accept download data but > that the same data pins work fine after the part is programmed > via JTAG? > > The exact same .bit files work fine on other boards. > > Suggestions? > > Thanks! > > John P > -- ---------------------------------------------------------------- Dave Van den Bout XESS Corp. PO Box 33091 Raleigh NC 27636 Phn: (919) 363-4695 Fax: (801) 749-6501 devb@xess.com http://www.xess.comArticle: 82035
johnp wrote:
> I've got a design using Select Map mode to program a Xilinx V2-Pro
> part. Many of the boards work, but one has stopped accepting the
> bit file download. Everything seems to proceed properly, but the
> DONE signal is never asserted. I can download via JTAG to the
> part just fine, but it just won't accept the Select Map download.
> [...]
> time on the data going into the V2-Pro. This board used to work,
> but at some point decided to be a problem.
> [...]
> Has anyone else seen problems like this? Is it likely that the
> FPGA couls be damaged such that it can't accept download data but
> that the same data pins work fine after the part is programmed
> via JTAG?
>
> The exact same .bit files work fine on other boards.
Howdy John,
You may have already tried this, but the first thing that jumps to my
mind is the problem I had a few years ago: make sure you toggle CCLK a
number of times *AFTER* DONE goes high. Turns out DONE means "you're
almost DONE," or "clock CCLK several more times, then you'll be DONE,",
or maybe "you just thought you were DONE." :-) Unreliable things can
happen if CCLK isn't toggled several more times.
Good luck!
Marc
Article: 82036In comp.arch larwe@larwe.com wrote: > > > > Are ISA covered by patents or trademarks? Is it allowed to develop a > > processor core for a popular ISA as long as no reference is made to > any > > Depends on the ISA. ARM, for instance, is covered by thick IP > protection layers, and is vigorously defended. 8051, not so much :) > Are you sure? A lot of the layers appear to be camoflage and not actual protection. The ARM business case appears to be: 1) milk money from people who buy ARM IP 2) if you see somebody else making ARMs, sue 3) try to get an out of court settlement at all costs 4) including by paying the "offender" lots of cash to go away, stop making ARMs and being quiet about the whole business -- Sander +++ Out of cheese error +++Article: 82037
"JJ" <johnjakson@yahoo.com> skrev i meddelandet news:1112742200.599044.301840@g14g2000cwa.googlegroups.com... > Q > If some processor that is not any way MIPs like can otherwise perform a > register ld/st for a word on any byte boundary is that a problem, or > only if the rest of it is MIPs like too. > > > If a processor has a general move n bytes ie mv rd,rs,4 and works on > any boundary and any length into memory locations that are also a > register, a problem?. > > Am I not mistaken that most all cpus allowed unaligned ld/st till the > RISC religion took over. Guess I will have to look at the patent. > > johnjakson at usa dot com > The Series 32000 definitely had that capability and that was available already in 1982. This was a microcoded machine, but I do not know if the unaligned functions was implemented in microcode. All machines had 32 bit datapaths and registers, and the NS32032 had a 32 bit bus already in 1985. Dont know the background of the invention. In 1985 there was It is very hard to invent new things -- Best Regards Ulf Samuelsson ulf@atmel.com Atmel Nordic AB Mail: Box 2033, 174 02 Sundbyberg, Sweden Visit: Kavallerivägen 24, 174 58 Sundbyberg, Sweden Phone +46 (8) 441 54 22 Fax +46 (8) 441 54 29 GSM +46 (706) 22 44 57 Technical support when I am not available: AT89 C51 Applications Group: mailto:micro@nto.atmel.com AT90 AVR Applications Group: mailto:avr@atmel.com AT91 ARM Applications Group: mailto:at91support@atmel.com FPSLIC Application Group: mailto:fpslic@atmel.com Best AVR link: www.avrfreaks.netArticle: 82038
Markus Blank wrote: > Lets assume we run a C program on the FPGA. This program contains a loop > which executes EXACTLY n times. How can I make sure that this value n isnt > changed in the memory by an attacker? Is there something like temper > resistant memory available? Or what other suggestions come into question? Your question doesn't seem to make a lot of sense - an FPGA is essentially a bunch of logic gates with configurable routing between them, whereas usually C is targeted towards a processor - a thing that takes a sequence of instructions and performs actions based on those instructions. You can "run" a C program on an fpga in the following ways - a) By implementing a soft-processor in the FPGA. The C code is then not really "running" on the FPGA then, but on a processor that happens to be implemented in the FPGA. c) By converting what the C program is intended to do into a digital logic design and then loading that configuration into the FPGA. In that case, the "program" isn't really a program any more - it's a piece of digital logic. Secondly - memory. An FPGA works by storing the configuration of the logic and routing in configuration memory cell. It may also have embedded RAM for use in datapaths. It may be interfaced to an external memory. You need to specify what type of memory you are talking about - this question could have many answers, and many dependancies. If you are talking about memory as in physical configuration then if you have an unencrypted bitstream then an attacker could theoretically modify the bitstream. The capability to modify the bitstream could also be used to change any memory internal or external to the device. Some FPGAs have the capability to load encrypted bitstreams, and some don't. Anything going out of the chip can be tampered with as well. JeremyArticle: 82039
Dan Koren wrote: > "Eric DELAGE" <"eric UNDERSCORE delage AT yahoo DOT fr"> wrote in message > news:4252c3dc$0$3114$8fcfb975@news.wanadoo.fr... > >>Hi, >> >>Are ISA covered by patents or trademarks? Is it allowed to develop a >>processor core for a popular ISA as long as no reference is made to any of >>the original company trademarks? Many thanks for your comments. >> > > > > Trademarks cover only product *names*. > > ISA names can indeed be trademarked, > hower that would not prevent anyone > from copying/using the architecture. > > It would only prevent them from > selling/promoting/advertising it > under the same name as the original. > There is a case of this years ago: The Zilog Z80 used the Intel 8080/8085 instruction set and extended it, but used different mnemonics for nearly all instructions. -- Tauno Voipio tauno voipio (at) iki fi'Article: 82040
> Can DCM's LOCKED o/p signal be used as reset within FPGA? > is this scheme feasible :- We use the LOCKED signal as async reset for our XC2V and XC3S designs. In case we have several cascaded DCMs, the 1st one rst the 2nd one, which in turn rst the 3rd one, till the last one which rst the complete design. EricArticle: 82041
On Wed, 06 Apr 2005 11:08:53 +1200, Jim Granville wrote: > > I heard that the NIOS II is 'very similar' to MIPS - can anyone who > knows both cores in detail comment ? > > -jg I don't know the MIPS in detail (long ago, I read a book on the R2000/R3000 architecture which I picked up in a second-hand bookshop), but there are certainly some fundamental similarities. Each is a 32-bit RISC core, with 32x32-bit registers, orthogonal instruction set, etc. The NIOS II is a little odd (IMHO) in that it has some registers with dedicated purposes and supervisor-only access. I think, however, that quite a lot of 32-bit RISC architectures (ARM, Microblaize) would be "very similar" at this level. The Nios I was a very different beast, and used sliding register windows in the manner of Sparc. Perhaps the comment you heard was more on the lines of "The NIOS II, unlike the original NIOS, is more of a standard RISC core, such as MIPS" ? mvh., DavidArticle: 82042
"Ulf Samuelsson" <ulf@NOSPAMatmel.com> writes: > > The basis of the patent is the "ARM Ltd discovery" that less code is better > than more code. > Code compression for RISC is mentioned already in the original RISC paper by > Katevenis. Original RISC paper by Katevenis? While I was able to find a 1983 paper by him, near as I can tell the original RISC paper is still the one by Patterson amd Ditzel in 1980. -- Joseph J. Pfeiffer, Jr., Ph.D. Phone -- (505) 646-1605 Department of Computer Science FAX -- (505) 646-1002 New Mexico State University http://www.cs.nmsu.edu/~pfeifferArticle: 82043
By looking at your code. It is an synchronous design. CPLD will not
gives good performance for asynchronous design because of their
architectures.
If possible, you should try clock enable signal instead of directly
drive the register's clk.
"Jan Bruns" <post@abnuto.de> wrote in message news:<d2vc7c$svj$1@online.de>...
> Hallo,
>
> in an CPLD-Design (XC95??XL), I have 2 data-strobe signals,
> and a data-stobe-select-signal.
> The selected strobe should clock 2*16 input regs:
>
> input [15:0] pinoekels;
> reg [15:0] di1;
> reg [15:0] di2;
> wire strobe = (ssel && s1) || (ssel && s2);
>
> always @(posedge strobe) begin
> di1 <= pinoekels;
> end
> always @(negedge strobe) begin
> di2 <= pinoekels;
> end
>
> The problem is that "strobe" shouldn't be implemented as
> a feedback-signal (too much delay).
>
> It needs to be implemented as 2*16*2 product terms (2 for any single reg).
>
> // synthesis attribute collapse of strobe is yes
> doesn't help ("strobe" gets an tool-generated name, that's all).
>
> I'v even tried to explicitly setup the 32FD, 32OR, 64AND2,
> using various constraint-combinations and optimisation-goals,
> because I felt, the "di" were implemented as FD16-macros somewhere.
>
> No matter waht I've tried, the "strobe" was always implemented
> as a feedback-path (or even worse: *many* feedback paths).
>
> Any further ideas?
>
> Isn't there an "XDL for CPLD" somewhere?
>
> Gruss
>
> Jan Bruns
Article: 82044Ico Doornekamp <ico@pruts.nl> wrote: > Hi all, > Up to now i've been using ISE 6.3 together with gplcver for simulation. Some > things seem to have changed with ISE 7.1, since gplcver doesn't seem to like > the simulation verilog modules of some components. For example, when > simulating the DCM, cver tells me the following : > **/opt/xilinx/verilog/src/unisims/DCM.v(43) ERROR** [1044] instance/gate "MAXPERCLKIN" type "localparam" connection list expected - = read > **/opt/xilinx/verilog/src/unisims/DCM.v(44) ERROR** [1044] instance/gate "MAXPERPSCLK" type "localparam" connection list expected - = read > **/opt/xilinx/verilog/src/unisims/DCM.v(46) ERROR** [1044] instance/gate "SIM_CLKIN_CYCLE_JITTER" type "localparam" connection list expected - = read > **/opt/xilinx/verilog/src/unisims/DCM.v(47) ERROR** [1044] instance/gate "SIM_CLKIN_PERIOD_JITTER" type "localparam" connection list expected - = read > **/opt/xilinx/verilog/src/unisims/DCM.v(356) ERROR** [753] instance i_max_clkin pound parameter maximum_period (pos. 1) expression MAXPERCLKIN only parameters and constants - is parameter from other module? > **/opt/xilinx/verilog/src/unisims/DCM.v(357) ERROR** [753] instance i_max_psclk pound parameter maximum_period (pos. 1) expression MAXPERPSCLK only parameters and constants - is parameter from other module? > (sorry for the unwrapped long lines, but that's just the output) > I must admit I haven't looked into much details about what might be causing the errors, > I first wanted to check if anybody else ran into this, and if there's a (simple) solution. > Any hints ? Did you talk to Andrew or Steve about the problem? Best is to create a small test case and send it to the authors. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 82045
Ray Andraka <ray@andraka.com> writes: > Karl wrote: > > >Here is a solution for your noise, > > > >http://www.zalman.co.kr/eng/product/view.asp?idx=151&code=020 > > > >The cost could not be the issue if you start using Altera devices :-) > > > > > that doesn't address the disk drive noise. 15000 rpm SCSI drives are > pretty noisy. > Do you need a 15k rpm drive for this sort of work? If you're swapping you need more RAM, surely? The reading of files from the disk has not been a bottleneck in my experience, although I'm not targetting the very biggest devices out there... My Barracuda is almost silent, even in standard mountings - its the PSU fan that annoys me now! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 82046
"JJ" <johnjakson@yahoo.com> writes: <snip> > There is another way to have it both ways and that is to use a folding > text editor, click on the 1 liner and see the the 1 or 5 or 100 lines > it represents. Pretty much a schematic thing to do to when you could > push down into sub sheets. > > Does anyone actually use such a thing, recomendations esp Windows, > I used to use CodeWright - dunno if it even still exists, but that did folding IIRC. > I half suspect Emacs can do it but never took to it. > :-) Yes, I use folding-mode a lot in my VHDL - the emacs VHDL-mode is the reason I finally took the plunge with emacs! I don't think the verilog-mode is as fully-featured - so maybe it won't suit you so much... Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 82047
> > That hasn't stopped people from implementing processors with the MIPS > > ISA, *except* for the patented instructions. But the people doing > > this are very careful about not calling the processor for anything > > related to MIPS... > > I heard that the NIOS II is 'very similar' to MIPS - can anyone who > knows both cores in detail comment ? It's (NIOS II) a 32-bit, 32 register RISC, but.. Different exception mechanism, different way of doing multiplies (no special registers), smaller instruction set, no branch delay slots, no unaligned load/stores, no fpu, no load-locked/store-conditional, no coprocessors, no 16-bit isa. So not really. Cheers, JonArticle: 82048
XAPP176 defines how to read back the configuration file but doesn't state whether this can be done while the device is operating normally? AnthonyArticle: 82049
Hi, Marc makes some excellent points about the provision of information. If you're targeting V4 then you are targeting one of our SX or LX devices and you are using 7.1.01i. If you provide accurate switching information (and an important element of that is simulation information from a VCD or XAD file) then your estimation for V4 devices should be within 50% of the actual measurement. If you run a series of designs you can expect your average design error to be within 25%. Feel free to send any other queries my way, Brendan Xilinx Power Tools parity wrote: > Hello, > > i'm from germany and just registered to this forum. Hello to everybody > out there. > > I'm working on very small FPGA Designs which are size-comparable > (about 4-40 Look-up-Tables on a VIRTEX FPGA) to 4 Bit-adders and 4 > Bit-multipliers. I use them just for testing some things. The problem > is that I use XPower to calculate the power consumption of the designs > and the power values are not what i expected. > > I have a testbench, an input stimuli and the placed and routed design. > Whenever i put stimulis to the design it delivers (like expected) the > "mW" values. But if i change the stimuli to other ones, which are > nearly the same, the power consumption raises to the double or stays > the same. (after subtracting the quiescent part). There's (in most > cases) nothing between them. > > Does anybody know this problem? Have I reached the smallest possible > XPower value, or what is it? > > Oh, and does anybody know, how accurate XPower should be. Is there a > chance to get some information about it? > > Thanks for all answers, > > parity
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