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Hi Nial, >> > If I obtain another license >>> with the correct ethernet card number I have, will this license be valid >>> when I don't really have ethernet connection? >>> Too tired today to do the experiment. I will appreciate it if you have >>> a >>> quick answer. Otherwise I will have to do the experiment and report the >>> result here. >> >> The problem is that when the network card isn't plugged in, and is set to >> get an IP address over DHCP, it doesn't give out a valid ethernet >> address. > > I don't think this is relevant Ben, the license file is generated against > the 12 hex digit MAC address of the ethernet card, not the IP address. This is partly true. If an IP address hasn't been set through DHCP, the interface gets an 169.x.y.z IP address. However, at the same time, the MAC address for the interface can for some reason not reliably be obtained anymore - at least not by FlexLM. Best regards, BenArticle: 81076
Is there a way to search past posts to comp.arch.fpga to find previous answers to perennial questions? http://groups-beta.google.com/groups?as_q=picoblaze+compiler&num=10 > "icegray" <usrdr@yahoo.co.uk> wrote in message > news:1111057041.605063.112170@o13g2000cwo.googlegroups.com... > are there c compiler for picoblaze? how can i load program FPGA or ROM? > JTAG??? >Article: 81077
Yesterday was another loss. > In attempting to reproduce the problem, are you testing in an actual > system with all boards and I/O connected in the usual configuration, > or in the lab with just the problematic board on a bench supply? All of the testing is being done with the real hardware. > > A few of the parts have problems when the power is > > not brought up correcly. > > > Does that result in any symptoms like your FPGA config problem, > or is everything so locked up that you can't tell ? No, it could result in device failure. But not on this board. > Without the power-up sequencing, do you get destructive failures? Based on textbook data, yes. Have I seen a problem, no. Again, a lot of care was taken to ensure this could not happen. > If not a destructive failure mode, can you briefly disconnect > (not clamp) the +5.0 V supply to the board, with -5.2V present, > and see what level the +5.0V plane on the board goes to? I did several tests with the supplies yesterday. No damage to the board it would appear, but I also was not able to reproduce the problem. > Or, intentionally disable/break the supply sequencer and power cycle. I tried drop out testing on all supplies in every combination. The ECL seemed to have little problem with the testing I did. > Do you have an AC disturbance/brownout generator to see how > the supply sequencer for the +5.0 and -5.2 rails behaves during > a brief AC dropout ? Yes we do, and again we have done a lot of testing like this and have not seen any problems like the one I am describing. > Hmmm, that also rings some faint old warning bells- I seem to > recall having problems once after I redesigned a card to replace > some obsolete translators with either the '602 or '603. Symptoms > were field returns with either a failed bit or two on the '60x, > or occasionally a part that looked it like had undergone some sort > of latchup/runaway and self destructed. I am VERY surprized that I have not seen a destructive failure with all the testing I have done. If I were to make a guess, it's like the Xilinx device goes into sleep mode somehow and won't wake back up. But again, while testing the power down pin I was not able to replicate the problem. No word from Xilinx yet.Article: 81078
Hello, I have problems with gateways in System generator 6.1.1, ISE 6.103, Matlab 6.5.1. I use a XtremeDSP Development Kit II With Virtex 2 XC2V3000-4fg676 and want to connect the AD and DA-converters, but this failes. So I made a simple test file, only 1 line, type boolean, between 2 Gateways. I can generate the ISE project. In ISE I try to implement, but the 2 signal names of the gateways cannot be found. Since gateways are the only way to connect pins with the circuit, no pins can be connected at all in Virtex 2? This cannot be possible, what is wrong there? Xilinx hotline seems to have holiday :-(. Regards, WinfriedArticle: 81079
Where to find Tutorials for using Xilinx FPGA? How to learn about Xilinx FPGAs, use ISE 6.3i and EDK 6.3i tools? Folks, I am trying to learn how to program Spartan II (XC2S100-5PQ208C) and Spartan 3 (XC3S400-4PQ208C) Xilinx FPGAs. I looked at the data sheets for these parts, and the more I do the more mystified I get. I have never done this before. I come from a software background, but have dabbled in hardware a little. I would like to learn how to program, design, and add external hardware to FPGAs. What is the best way to go about this? I have looked at some of the documents related to ISE and EDK, but have not been able to understand a great deal because of the different terminology and concepts they use (e.g. OPB v2.0 bus, Slices, Pulse Width Modulation). These ideas have little meaning to me having never seen them before. I did see the training classes on the web, but don't have $20K to shell out to take them all, being a broke chump and all. Anyway I have the ISE and EDK 6.3i tools, and have been trying to read the documentation, but again I have the same issues. Based on these descriptions, about how long does it take to write simple VHDL programs that work, or become fluent enough to know a good design from a chip fryer? Thanks, -HTArticle: 81080
The basic problem is that the user is trying to use a license created for a different NICID than what the computer running Quartus has. Quartus does not require the card to be plugged into the network to check the license. A new license should be issued for correct NICID. The easiest way to get a license is to connect your computer running Quartus to the network, go to Tools->License-Setup and do a Web License Update. Hope this helps, Subroto Datta Altera Corp. "vax, 9000" <vax9000@gmail.com> wrote in message news:d1aud6$bf2$1@charm.magnus.acs.ohio-state.edu... > Hi list, > I don't have ethernet connection though I do have an ethernet card > installed. My computer can boot either with linux or win XP. I have dial > up > connection under linux only. I downloaded ALTERA software version 4.2 > (yeah, overnight dialup), obtained the license (with an arbitrary ethernet > number), and copied the files to windows partition and installed. > The problem is now that under XP, when I run the software it does not > think the license is a valid one. My question is whether I really need > ethernet connection under XP to run ALTERA. If I obtain another license > with the correct ethernet card number I have, will this license be valid > when I don't really have ethernet connection? > Too tired today to do the experiment. I will appreciate it if you have a > quick answer. Otherwise I will have to do the experiment and report the > result here. > > vax, 9000Article: 81081
On 16 Mar 2005 23:30:44 -0800, litv@fromru.com wrote:
>>1.I have some problems in my design with "loop back".
>>I inserted "Use explicit sample period" for all components in loop.
>>But in simulation i have :
>>"The Relational Block received data in an indeterminate ("don't care")
>>state" .
I have encountered this problem. Trying to remember how I solved
it ... I think that I had to create a Valid Out port on the
"source" component, connected to the Enable input port on the
"destination" component.
>>2. Who have good experience with Xilinx System Generator ?
>>I need in your opinion. Is this Soft equal to new funny toy or real CAD
>>product ?
I have created some incredibly complex designs with it. I know
signal processing, not VHDL, so I can say that it allowed me to do
things that I could not otherwise do without a tremendous
investment in time and effort.
Greg
Article: 81082On Thu, 17 Mar 2005 15:15:25 +0100, Winfried Salomon <salomon@uni-wuppertal.de> wrote: >>So I made a simple test file, only 1 line, type boolean, between 2 >>Gateways. I can generate the ISE project. In ISE I try to implement, but >>the 2 signal names of the gateways cannot be found. When you double-click on an output gateway, does "Translate into Output Port" have a checkmark by it? If not, then the port, and everything connected to it, is removed by the optimizer. GregArticle: 81083
pasacco wrote: > dear > > I need to implement the following. > > 2 microblazes and 2 Data BRAMs (assumeing 1 Instruction BRAM for both > ). Both of Data BRAMS range 0x0000 - 0x3fff and each belongs to each > microblaze. What is important for me is to share the data memory, such > that the programmer write ONE program and considers the memory as ONE > global memory with 0x0000 - 7fff. > > I expect that MMU (address translation) unit is necessary. I wonder if > this is possible with one (shared) with 1 OPB. Problem is I have no > experience on this. Is these possible? If yes, how? :) If someone gives > me some hint or suggestion, it will greatly appreciated. > Hi, I don't think you can have a shared memory with cover 0x0000 - 0x3fff and make it so that the processors sees it as 0x0000 - 0x7fff. That would double the amount of memory available. GöranArticle: 81084
and what is the price of this board?? Regards , Alexis PS: comme c'est pour une societe francaise je peut parler en francais : corriger les mauvais liens sur votre site par exemple à la page http://alse-fr.com/tornado, il y a un lien vers http://alse-fr.com/products.html qui renvoit sur une erreur404... "Bert Cuzeau" <_no_spa_m_info_no_underscore_@alse-fr___.com> a écrit dans le message de news: 423932b6$0$28009$626a14ce@news.free.fr... > Hello, > > We have designed a Cyclone-based FPGA board which is handy in two > situations : > - Quick prototyping for industrial control and robotics systems > - Education (even self-) > > You can find a description of the Education KIt (and of the board) at : > http://alse-fr.com/Tornado/Torn_Educ_us.pdf > > Feedback (like ideas about more Labs) are welcome, but orders too :-) > The board (& kit) is available on-shelf. > > Best regards, > > Bert >Article: 81085
"Herb T" <oth3ll0@hotmail.com> wrote in news:1111071427.730695.188390 @f14g2000cwb.googlegroups.com: > Where to find Tutorials for using Xilinx FPGA? > How to learn about Xilinx FPGAs, use ISE 6.3i and EDK 6.3i tools? > > Folks, > I am trying to learn how to program Spartan II (XC2S100-5PQ208C) and > Spartan 3 (XC3S400-4PQ208C) Xilinx FPGAs. I looked at the data sheets > for these parts, and the more I do the more mystified I get. I have > never done this before. I come from a software background, but have > dabbled in hardware a little. I would like to learn how to program, > design, and add external hardware to FPGAs. What is the best way to go > about this? > > I have looked at some of the documents related to ISE and EDK, but have > not been able to understand a great deal because of the different > terminology and concepts they use (e.g. OPB v2.0 bus, Slices, Pulse > Width Modulation). These ideas have little meaning to me having never > seen them before. I did see the training classes on the web, but don't > have $20K to shell out to take them all, being a broke chump and all. If you are just learning about FPGAs and want to implement a few simple designs using the ISE, then take a look at this tutorial: http://www.xess.com/appnotes/webpack-6_3-xsa.pdf We don't have a tutorial that covers the EDK, yet. > > Anyway I have the ISE and EDK 6.3i tools, and have been trying to read > the documentation, but again I have the same issues. > > Based on these descriptions, about how long does it take to write > simple VHDL programs that work, A couple of hours if you use the VHDL language templates found in ISE. > or become fluent enough to know a good > design from a chip fryer? I still can't do that. > > Thanks, > -HT > > -- ---------------------------------------------------------------- Dave Van den Bout XESS Corp. PO Box 33091 Raleigh NC 27636 Phn: (919) 363-4695 Fax: (801) 749-6501 devb@xess.com http://www.xess.comArticle: 81086
Hi Doug, Tommy: > Strange. Our DSE guys are equally confused. Things are working fine for us... For us to be able to completely debug your issues we need see your design, or at least the full DSE output logs (*.dse.rpt) with the -debug flag on. We tried using seeds in the form n1-n2 and it seemed to work fine for us on 4.2 SP1. Maybe you can try separating your seeds with commas in case there is something weird there. Another possibility is that your base compile has an error or no-fit, which causes compilation to halt in a similar way to what you describe. Regards, Paul Leventis Altera Corp.Article: 81087
lecroy7200@chek.com wrote: > Yesterday was another loss. > > >>In attempting to reproduce the problem, are you testing in an actual >>system with all boards and I/O connected in the usual configuration, >>or in the lab with just the problematic board on a bench supply? > > > All of the testing is being done with the real hardware. Have you done aggressive field (impulse & RF burst) testing yet ? This would be on as near a real field-install as practical. Do you have a stats map, of the failure count/installed unit/site/time ? [ ie these are truly random failures ?] When all else fails, you can always blame Alpha particles ? ( see this highly selective test http://www.actel.com/company/press/2005pr/RadiationReliability.html ) -jgArticle: 81088
The implementation will looks like above.
uBLAZE1 uBLAZE2
| |
MMU (switch) MMU (switch)
| |
|---------------------OPB--------------------------|
| |
BRAM 1 (16kB) BRAM 2 (16kB)
The assembly programmer should see the memory as 32 KB global memory.
The role of MMU will be to translate the address and decides which (one
of both) memory should be accessed. It does not matter the address
range of each memory. I need some help. Thankyou very much for some
hint on how to realize this....
Article: 81089I am probably opening a can of worms, but why are FPGAs so slow? The CPU cores at www.opencore.org represent an ever growing number of excellent and very practical, but slow processor implementations. What I mean is 240-500Mhz FPGAs, when market CPUs are in the 3Ghz range. Surely there must be 1 or 2 Ghz FPGAs available with sub nano second gate switch/propagation times. Or possibly it is a verilog, vhdl or synthesis problem with the designs? Should I just use mass manufactured high speed CPUs and relegate the other discrete logic to CPLD/FPGAs?? Lastly, how fast is NIOSII?Article: 81090
If you need huge processing speeds, "just use mass manufactured high speed CPUs." If you want processing to augment your FPGA logic, consider adding a processor that adds functionality, not necessarily silicon-optimized speed. After all, how many DMIPs do you need? Consider the 450 MHz PPC core in the Xilinx devices. That PPC405 core is running about as fast as you can get in any other PPC405 implementation. It *is* optimized silicon. The Intels and AMDs of this world typically produce designs that run in the 10s of watts. I want to run my FPGAs much cooler. Modern FPGAs aren't slow. The processors you think of as "normal" speeds are just highly optimized. "dave" <dave@dave.dave> wrote in message news:d1cobl$rs6$1@news8.svr.pol.co.uk... > I am probably opening a can of worms, but why are FPGAs so slow? > > The CPU cores at www.opencore.org represent an ever growing number of > excellent and very practical, but slow processor implementations. What I > mean is 240-500Mhz FPGAs, when market CPUs are in the 3Ghz range. > > Surely there must be 1 or 2 Ghz FPGAs available with sub nano second > gate switch/propagation times. > > Or possibly it is a verilog, vhdl or synthesis problem with the designs? > > Should I just use mass manufactured high speed CPUs and relegate the > other discrete logic to CPLD/FPGAs?? > > Lastly, how fast is NIOSII?Article: 81091
I quite agree with John_H its a mistake to compare FPGA functionality and CPU functionality,they are just fundamentaly different things.I also think its a mistake to implement a CPU in a FPGA but I'll prolly get flamed for saying that.Article: 81092
Mentre io pensavo ad una intro simpatica "Stephan Neuhold" scriveva: > Nemesis, > > You can find all supported IP for Coregen 7.1i at the following site > http://www.xilinx.com/ipcenter/coregen/coregen_iplist_71i.htm Thanks, that's exactly what I was looking for. -- Brain dysfunction detected... |\ | |HomePage : http://nem01.altervista.org | \|emesis |XPN (my nr): http://xpn.altervista.orgArticle: 81093
Well I'm not really sure but this is what i think about your question: 1. the first reason is that fpga are made to do all sort of design so you have route and interconnexion that consume time, in the case of a cpu you have a specific architecture so it can go faster (look at integrated multiplier in fpga go faster than if you implemented one in a fpga with lut and gate) 2.If you implement a specific algorithm in a fpga it will go faster than in a cpu because you can make hardware optimisation and where you could use 10 cycle with cpu it will need only 1 cycle in a fpga , and you could also implement many other processing unit, thing you could'nt do in a cpu I remember that during my courses of image processing that some algorithm in fpga @100MHz could process 1000*faster than a P4@2GHz Frequency is not always the key look at AMD and Intel they are not running at the same frequency but they are both powerfull equivalent. And there is many other kind of CPU and also DSP. 3.I think Fast CPU instruction take also more cycle than soft CPU because of pipeline, so you go faster but you need more time(should i say cycle) to have your result , and in recursive computation it's a really annoying thing. 4. If you run faster you also consume more current so for many application (as embedded) going faster is not an interesting 5. comparing fpga and cpu is useless because they are not made for doing the same thing , CPU embedded in FPGA are more made to control other process and other task that don't need too much computation power comparing FPGA and CPU is like comparing plane and car Regards <dave@dave.dave> a écrit dans le message de news: d1cobl$rs6$1@news8.svr.pol.co.uk... >I am probably opening a can of worms, but why are FPGAs so slow? > > The CPU cores at www.opencore.org represent an ever growing number of > excellent and very practical, but slow processor implementations. What I > mean is 240-500Mhz FPGAs, when market CPUs are in the 3Ghz range. > > Surely there must be 1 or 2 Ghz FPGAs available with sub nano second gate > switch/propagation times. > > Or possibly it is a verilog, vhdl or synthesis problem with the designs? > > Should I just use mass manufactured high speed CPUs and relegate the other > discrete logic to CPLD/FPGAs?? > > Lastly, how fast is NIOSII?Article: 81094
Hi All, If anyone knows of a bit rounding algorithm, please forward the information to me. I am trying to round-off 24 bits to 12-bits. Thanks MORPHEUS p.s. the 24 bits is the result of an additing between two 24 bit numbers. I need to round off the result and feed it to a 12-bit DAC. THNXArticle: 81095
"Whoa there, hold your horses Tex!" What I consider "normal" speeds?!!? I work with DSPs & parallel computers, however my home PCs max out at 700Mhz! It was a simple question, put your sword away. You're correct. After all, why would Xilinx create a 450Mhz PPC core. Highly optimized to achieve..... Anyway FPGAs are not for implementing processors. Bad idea right. They are just for combining discrete logic in a smaller space. <pause> Contrary to what you may think there is a market for Ghz speed flexible FPGAs. But hey, what do I know, I am just a HDL newbie. FlameOn buddy.... John_H wrote: > If you need huge processing speeds, "just use mass manufactured high speed > CPUs." > > If you want processing to augment your FPGA logic, consider adding a > processor that adds functionality, not necessarily silicon-optimized speed. > After all, how many DMIPs do you need? > > Consider the 450 MHz PPC core in the Xilinx devices. That PPC405 core is > running about as fast as you can get in any other PPC405 implementation. It > *is* optimized silicon. > > The Intels and AMDs of this world typically produce designs that run in the > 10s of watts. I want to run my FPGAs much cooler. > > Modern FPGAs aren't slow. The processors you think of as "normal" speeds > are just highly optimized. > > > "dave" <dave@dave.dave> wrote in message > news:d1cobl$rs6$1@news8.svr.pol.co.uk... > >>I am probably opening a can of worms, but why are FPGAs so slow? >> >>The CPU cores at www.opencore.org represent an ever growing number of >>excellent and very practical, but slow processor implementations. What I >>mean is 240-500Mhz FPGAs, when market CPUs are in the 3Ghz range. >> >>Surely there must be 1 or 2 Ghz FPGAs available with sub nano second >>gate switch/propagation times. >> >>Or possibly it is a verilog, vhdl or synthesis problem with the designs? >> >>Should I just use mass manufactured high speed CPUs and relegate the >>other discrete logic to CPLD/FPGAs?? >> >>Lastly, how fast is NIOSII? > > >Article: 81096
Would you be willing to assist me in my MBA class project? I have a short survey online for engineers with questions about how you use search engines. Only 11 questions and it is completely anonymous. If you would be willing to help me, please take five minutes and go to: http://www.surveymonkey.com/s.asp?u=76406916462 Thank you very much ... I really do appreciate it. Lori Ann Clark Danville Signal A struggling Stats MBA StudentArticle: 81097
Ahhh! An answer that values my newbie-ness. Ok, I think HDL and FPGA/CPLD is worth a look. Once again, thanks. KCL wrote: > Well I'm not really sure but this is what i think about your question: > > 1. the first reason is that fpga are made to do all sort of design so you > have route and interconnexion that consume time, in the case of a cpu you > have a specific architecture so it can go faster (look at integrated > multiplier in fpga go faster than if you implemented one in a fpga with lut > and gate) > > 2.If you implement a specific algorithm in a fpga it will go faster than in > a cpu because you can make hardware optimisation and where you could use 10 > cycle with cpu it will need only 1 cycle in a fpga , and you could also > implement many other processing unit, thing you could'nt do in a cpu > I remember that during my courses of image processing that some algorithm in > fpga @100MHz could process 1000*faster than a P4@2GHz > > Frequency is not always the key look at AMD and Intel they are not running > at the same frequency but they are both powerfull equivalent. And there is > many other kind of CPU and also DSP. > > 3.I think Fast CPU instruction take also more cycle than soft CPU because of > pipeline, so you go faster but you need more time(should i say cycle) to > have your result , and in recursive computation it's a really annoying > thing. > > 4. If you run faster you also consume more current so for many application > (as embedded) going faster is not an interesting > > > 5. comparing fpga and cpu is useless because they are not made for doing the > same thing , CPU embedded in FPGA are more made to control other process and > other task that don't need too much computation power > comparing FPGA and CPU is like comparing plane and car > > Regards > > <dave@dave.dave> a écrit dans le message de news: > d1cobl$rs6$1@news8.svr.pol.co.uk... > >>I am probably opening a can of worms, but why are FPGAs so slow? >> >>The CPU cores at www.opencore.org represent an ever growing number of >>excellent and very practical, but slow processor implementations. What I >>mean is 240-500Mhz FPGAs, when market CPUs are in the 3Ghz range. >> >>Surely there must be 1 or 2 Ghz FPGAs available with sub nano second gate >>switch/propagation times. >> >>Or possibly it is a verilog, vhdl or synthesis problem with the designs? >> >>Should I just use mass manufactured high speed CPUs and relegate the other >>discrete logic to CPLD/FPGAs?? >> >>Lastly, how fast is NIOSII? > > >Article: 81098
Jezwold wrote: > I quite agree with John_H its a mistake to compare FPGA functionality > and CPU functionality,they are just fundamentaly different things.I > also think its a mistake to implement a CPU in a FPGA but I'll prolly > get flamed for saying that. > Honest question, why is it a mistake?Article: 81099
Ghz speed FPGAs with sub ns are seriously expensive,but as you say there must be a market otherwise they wouldnt make them. Ive just never come across anyone who used them to implement a general purpose CPU
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