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Broaddown2 has headers that are spaced on multiples of 0.1 inch (2.54 mm) and can accept prototying materials such as stripboard. From these headers 3.3V/2.5V/1,8V and 0V can also be supplied to power your add-on. Failing that Broaddown2 has a nimber of supplies including negative rails that can be connected via flying lead. Headers are fitted on Broaddown2 for such cases. Of course if you University has the facilities you can also make a simple custom PCB to fit these headers as well. Usually a 1 or 2 layer PCB will cover many interfacing requirements. This is what we do when we produce either a new standard add-on module or customer paid for custom modules. The only word of caution is that anything connected to the headers, and hence the Spartan-3, should not have a voltage higher than nominal 3.3V (4.05V limit) otherwise you will damage the Spartan-3. If you need to use 5V logic then level translate use a bus switch device or other suitable device. You can see an example of these devices on a picture of Broaddown2 down near the PCI connector. 3 x 20 way devices are to be seen there and they level shift PCI and the 5V oscillator outputs. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "niggu" <n.s@datacomm.ch> wrote in message news:d0sfu0$i2k$1@news.hispeed.ch... > > This Boards sounds interesting (the price also). What I din't get is how > to add on the 1394 interface so we could plug in our cam. Is it to find > a chip and solder ourself? > Your project with a 1394 add-on board sounds interesting to. But the > time of our project is already running therefore this would probably be > to late for us. > > Nicolas Schwarzentrub > > John Adair wrote: > > Our Broaddown2 has the PCI and the capability to add on the 1394. There are > > discounts for students but if that would make it cheap enough I don't know. > > We have a project that may give a 1394 add-on board but I don't have a > > launch date for this yet. If you are looking at MicroBlaze as a processor > > then Broaddown2 currently comes with a $100 discount voucher for EDK that > > can be used at one of our partners in the UK. > > > > We also have a product coming that is aimed at students and is going to be > > aimed at the cheap end of the market. It will be PCI based and should be > > capable of supporting some of Broaddown2's DIL header add-ons. > > > > More details of all of this should appear on our website upgrade in 2/3 > > weeks time. > > > > John Adair > > Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development > > Board. > > http://www.enterpoint.co.uk > > > > > > "Nicolas Schwarzentrub" <schwn@hta-bi.bfh.ch> wrote in message > > news:d0pg8u$nco$1@news.hispeed.ch... > > > >>Hi everybody, > >> > >>we're two students looking for a low cost developer board for our > >>diploma work. we intend to plug a camera to the pci board via 1394 and > >>process the images throug the fpga and get the processed images from > >>fpga via pci. The camera we will use, uses DCAM /IICD > >>Now we have several problems: > >>-we don't have a high budget, so it should be a low cost solution. > >> > >>-we have not jet found a board that fits our need, does anybody know > >>something cheep that could fit our needs? > >> > >>-there would be several possibility to solve the connectivity problems: > >> > >>* best would be to find a board that fits our need, means have at least > >>pci, fpga and 1394 on it? any suggestions ont htat? > >> > >>* if the above point can't be reached we could probably solder our 1394 > >>interface ourself on a board. What would then be best for our purpose? > >>We could probably use a TSB12LV32 chip from ti if we don't find a board > >>with firewire. > >>(http://focus.ti.com/docs/prod/folders/print/tsb12lv32.html)? does > >>anybody know this? would it then be possible to implement the dcam in > >>the fpga? > >> > >>Thanks to everbody > > > > > >Article: 80901
A Beaujean wrote: > OK. Well, there follows a link with a very interesting paper on > potential problems with (too) simple asynchronous resets. > > http://www.sunburst-design.com/papers/CummingsSNUG2003Boston_Resets.pdf > > Having acknowledged the potential dangers described in that paper, I > now systematically create for my VHDL designs a synced reset per clock > domain and uses those synced resets as async reset inputs on all > registers of the design. I just let the synthesis and PAR tool operate > as usual, giving no special directive, and got not problem until now. Hi Beaujean, do the registers which are used to sync the external reset have an asynchronous reset input ? If yes, what signal does feed these reset inputs ? Thanks for all posts. Best Rgds AndrésArticle: 80902
steve wrote: > I want to graphically create and edit waveforms for documentation purpose. > ... > A guy here uses some commercial spreadsheet...;-) please tell me what do > you use! I've never done this, but you might look at either some combination of gtkwave and either icarus or ghdl; or the Latex timing package, see e.g. pg 39 of http://www.edsko.net/latex/netsoc-part3.pdf I guess it depends how complex the diagram is, and whether you want to generate it from a testbench. I've just seen this: http://www-verimag.imag.fr/~remond/SIM2CHRO/ but have never heard of it before, and it doesn't look to be open source. MartinArticle: 80903
Mac wrote: > On Sat, 12 Mar 2005 21:01:31 +0000, newman wrote: > > > > > "Mac" <foo@bar.net> wrote in message > > news:pan.2005.03.12.19.14.14.656152@bar.net... > >> On Sat, 12 Mar 2005 18:52:24 +0000, newman wrote: > >> > >>> In ISE 6.2i, I compile a design off a mapped drive at a foreign site(ie I > >>> did not install the software and do not have administrative privileges). > >>> For example, I try to run Map, sometimes it completes with a green check > >>> mark, and sometimes it completes with no green check mark. Sometimes > >>> when > >>> it compiles with a green check mark, and I hit the Map Report, it reruns > >>> all > >>> the tools again (like xst, ngcbuild, map) as though a source hdl file had > >>> been changed. but no source files have been changed. Its maybe like the > >>> filesystems are running off two different timestamp clocks? > >>> > >>> Any ideas? > >>> > >>> -Newman > >> > >> The timestamp thing can be a problem for make-based dependency checking > >> (which ISE uses). > >> > >> But if all the design files are stored on the same computer, I would think > >> that the timestamp would be consistent across all of them. > >> > >> As a practical matter, would it be possible for you to simply check the > >> time on all relevant computers? The first step to corrective action is to > >> determine what the problem is. Inconsistent time is one hypothesis, now > >> you should test it. If the time is consistent, then you will have to come > >> up with a new hypothesis. > >> > >> --Mac > >> > > Well, the files are stored on a remote computer. Looking at the file > > timestamps in an explorer window, I did notice that when I refreshed the > > window, some of the working files were later than the time displayed on the > > local computer (where the compilation takes place). I did bump up the local > > time by a couple of minutes in order to guess an approximate equal time for > > both computers, but I still experienced the same problem. > > > > -Newman > > If you want to solve this problem, here is what I suggest. First, devise a > simple, repeatable test which identifies the problem. > > Then, formulate a hypothesis about what is causing the problem, and take > appropriate steps (according to the hypothesis) to make the problem go > away. Then perform the simple repeatable test to see if the problem is > fixed. If it is fixed, then, just to be sure, undo the fix, and perform > the test again to make sure the problem comes back. Sometimes I go back > and forth like this several times to really convince myself that I have > solved the problem. > > If the potential solution doesn't work, undo it, and try another potential > solution. And so on. > > In this case, the question you should ask yourself is, did you synchronize > the clocks or not? Do you feel that you have ruled out clock > differences as a potential cause of the behavior you are seeing or > not? If you haven't ruled it out, then keep messing around until you can. > > I would think the one thing you DON'T want to have, is files with > modification times in the future, so if you can't sync the clocks exactly, > at least try to make the clock on the system running the compiler slightly > faster than the one storing the data. > > Good luck. > > --Mac There's another possible problem, if your systems are not set up for the same time zone. In this case if the computers have the same time the file system will think the dates are off by the time zone differential. Also I know it's a pain but the simplest workaround is to right click on the report file in the process window and "open without updating". If you need to generate a new report or re-synthesize you can use the right-click "rerun" or "rerun all" to force a new build. Good Luck GaborArticle: 80904
Piotr Wyderski wrote:
> Hello,
>
> I would like to start a serious adventure in FPGA development,
> so which HDL would you recommend me? I can restrict myself
> to a single chip vendor (i.e. Altera, because their chips are quite
> cheap and very easy to obtain in small quantities in Poland),
> thus the spectrum of alternatives should be wider. The most
> important thing is good support of genericity, for instance:
>
> generic type vector{N} where {const N : positive} is group of N
bits
> x : vector(32); -- x : std_logic_vector(31 downto 0)
>
> or even constants:
>
> generic const square{N} : type of N where {const N} is N*N;
> const nine : int is square{3};
>
> The languages I know about are:
>
> VHDL: very disappointing, the nicest part of Ada has ben removed.
> No support for anonymous types, stiff and annoying syntax, weak
> interface inference (needs explicit component specifications).
>
> Verilog: same as above + lack of generate statements, so how
> does one specify generic pipelines (very useful e.g. in parallel
> CORDIC specifications)?
>
Verilog 2001 does support generate. It also supports arrays of
instances which are often easier to use than generate for many
applications. Verilog is also very popular in the U.S. although
it has fewer followers elsewhere. If you already know VHDL the
more concise nature of Verilog may not be a big win, nor Verilog's
similarity to C.
Another thing to remember about Verilog is that it is less rigid
about type-checking. For example you can build designs where the
size of a vector applied to a module port doesn't match the size
in the module. This will only generate a warning - not an error,
and warnings are easy to miss when the tools produce 100's of them.
Just my 2 cents.
Gabor
> AHDL: I don't know much about it, because I can't find a good manual.
>
> Best regards
> Piotr Wyderski
Article: 80905design wrote: > Hi all, > I am developing my first circuit board with FPGA. > Trying to make a circuit board without PROM for FPGA programming so > just using the FPGA, hence cutting down the cost as well for security. > Planning on using the JTAG method where the bit file is used to > directly program the FPGA. > In this case since the FPGA needs to be programmed every time on > powerup, is there a cache in the FPGA which stores the bitstream and > configures the FPGA each time on powerup. No. There is only static RAM in the FPGA for storage, nothing that can last beyond power cycling. > Or does the bitstream need to be downloaded each time when the FPGA is > powered up unlike the PROM method where the FPGA gets configured from > the PROM. Yes. But I wouldn't say its "unlike" the PROM method. At the FPGA the bitstream is loaded after each power cycle in either instance. In the case of the PROM, the bitstream is on-board. With JTAG it comes from your computer. > I couldnt find any documentation on Xilinx website for these questions. > So any help with this is greatly appreciated. > Many of the Xilinx FPGA's have both a datasheet and a user guide. There is much more detailed information about configuration (and other topics) in the user guides than in the datasheets. > Thanks & regardsArticle: 80906
Jezwold wrote: > Apart from behavioral languages such as systemC thats about > it,vhdl,verilog,ahdl is rarely used now, so VHDL is about your best > bet,its not perfect but its better than a poke in the eye with a sharp > stick.. > I thought VHDL was a poke in the eye with a sharp stick :->Article: 80907
Hi there, I still can't find a UK supplier for a low quantity (8) of XCF01 memory. Memec don't reply to my messages, and the only supplier in the states I found (nuhorizons) were charging $75 to ship to me! Can anyone give me a pointer as to (a) somewhere I can get the in the UK, or (b) somewhere that will ship to me at a normal cost. Thanks, Andy.Article: 80908
Thanks for all your ideas on this matter. There is no JTAG support on this device. All devices are programmed from an external computer using the Done/Prg', Reset, Data and Clock pins using the slave serial mode. The traces are daisy chained to each device and then terminated at the end of the bus. All devices are loaded with the same core using slave serial mode. Even if the loading state machine were some how stuck, needing more clock cycles to flush it, the programming does this upon each load sequence. Also, if you have the data sheet, on page 7-19, you will notice that during configuration, if the Reset pin is active, the configuration will abort and the init. sequence will start over. The following is from the data sheet for the 3000: "To initiate a re-programming cycle, the dual-function pin DONE/PROG must be given a High-to-Low transition. To reduce sensitivity to noise, the input signal is filtered for two cycles of the FPGA internal timing generator." All of these pins are hard wired together. And once in the "locked" state, the device remains with the pin released. So, I am still able to pull the pin low to start a new download. Once the device is in the mode, it is almost like it behaves like it is no longer in the circuit. I am able to program all other devices in the chain. The following is from the data sheet for the 3000: "The FPGA tests for the absence of an external active Low RESET before it makes a final sample of the mode lines and enters the Configuration state. An external wired-AND of one or more INIT pins can be used to control configuration by the assertion of the active-Low RESET of a master mode device or to signal a processor that the FPGAs are not yet initialized. If a configuration has begun, a re-assertion of RESET for a minimum of three internal timer cycles will be recognized and the FPGA will initiate an abort, returning to the Clear state to clear the partially loaded configuration memory words. The FPGA will then resample RESET and the mode lines before re-entering the Configuration state. During configuration, the XC3000A, XC3000L, XC3100A, and XC3100L devices check the bit-stream format for stop bits in the appropriate positions. Any error terminates the configuration and pulls INIT Low."Article: 80909
Strike that last bit about the Done/Prg' being hardward wired. They are seperate signals, so yes, it is very possible the the Done could be held low in the locked state. lecroy7200@chek.com wrote: > Thanks for all your ideas on this matter. > > There is no JTAG support on this device. All devices are programmed > from an external computer using the Done/Prg', Reset, Data and Clock > pins using the slave serial mode. The traces are daisy chained to each > device and then terminated at the end of the bus. All devices are > loaded with the same core using slave serial mode. Even if the loading > state machine were some how stuck, needing more clock cycles to flush > it, the programming does this upon each load sequence. Also, if you > have the data sheet, on page 7-19, you will notice that during > configuration, if the Reset pin is active, the configuration will abort > and the init. sequence will start over. > > The following is from the data sheet for the 3000: > > "To initiate a re-programming cycle, the dual-function pin > DONE/PROG must be given a High-to-Low transition. To > reduce sensitivity to noise, the input signal is filtered for two > cycles of the FPGA internal timing generator." > > All of these pins are hard wired together. And once in the "locked" > state, the device remains with the pin released. So, I am still able > to pull the pin low to start a new download. Once the device is in the > mode, it is almost like it behaves like it is no longer in the circuit. > I am able to program all other devices in the chain. > > > > The following is from the data sheet for the 3000: > > "The FPGA tests > for the absence of an external active Low RESET before it > makes a final sample of the mode lines and enters the Configuration > state. An external wired-AND of one or more INIT > pins can be used to control configuration by the assertion of > the active-Low RESET of a master mode device or to signal > a processor that the FPGAs are not yet initialized. > If a configuration has begun, a re-assertion of RESET for a > minimum of three internal timer cycles will be recognized > and the FPGA will initiate an abort, returning to the Clear > state to clear the partially loaded configuration memory > words. The FPGA will then resample RESET and the mode > lines before re-entering the Configuration state. > During configuration, the XC3000A, XC3000L, XC3100A, > and XC3100L devices check the bit-stream format for stop > bits in the appropriate positions. Any error terminates the > configuration and pulls INIT Low."Article: 80910
On Mon, 2005-03-14 at 14:56 +0000, Andy Main wrote: > Hi there, > > I still can't find a UK supplier for a low quantity (8) of XCF01 memory. > Memec don't reply to my messages, and the only supplier in the states > I found (nuhorizons) were charging $75 to ship to me! > > Can anyone give me a pointer as to (a) somewhere I can get the in the > UK, or (b) somewhere that will ship to me at a normal cost. Andy, Have you checked with a local Xilinx FAE? My local FAE has helped me with this type of issue in the past. I'm not sure if that is normal behaviour but its worth a try. Also, Digikey may have them and I believe they have a European office now although I could be wrong about that. Cheers.Article: 80911
Philip wrote: > > The solution may involve changes to your power supply, such that if > the voltage ever dips below say 4.5V, you make sure it goes all the > way down to 0V, for maybe 100 mS, before it comes back up. > I also have vague recollections of this problem ( needing to completely shut off power to 0V recover ) Some googling turned up this copy of an old Xilinx answer record #134 (watch line breaks on the link): http://www.nalanda.nitc.ac.in/industry/appnotes/xilinx/documents/techdocs/134.htm BrianArticle: 80912
Andy Main wrote: > Hi there, > > I still can't find a UK supplier for a low quantity (8) of XCF01 memory. > Memec don't reply to my messages, and the only supplier in the states I > found (nuhorizons) were charging $75 to ship to me! > > Can anyone give me a pointer as to (a) somewhere I can get the in the > UK, or (b) somewhere that will ship to me at a normal cost. > > Thanks, > > Andy. try to call MEMEC ( www.memec.com -> UK ) Laurent ------------ And now a word from our sponsor ------------------ Do your users want the best web-email gateway? Don't let your customers drift off to free webmail services install your own web gateway! -- See http://netwinsite.com/sponsor/sponsor_webmail.htm ----Article: 80913
James Morrison wrote: > On Mon, 2005-03-14 at 14:56 +0000, Andy Main wrote: > >>Hi there, >> >>I still can't find a UK supplier for a low quantity (8) of XCF01 memory. >> Memec don't reply to my messages, and the only supplier in the states >>I found (nuhorizons) were charging $75 to ship to me! >> >>Can anyone give me a pointer as to (a) somewhere I can get the in the >>UK, or (b) somewhere that will ship to me at a normal cost. > > > Andy, > > Have you checked with a local Xilinx FAE? My local FAE has helped me > with this type of issue in the past. I'm not sure if that is normal > behaviour but its worth a try. > > Also, Digikey may have them and I believe they have a European office > now although I could be wrong about that. > > Cheers. > Digikey didn't have them last time I checked, plus they have an annoying minimum order penalty which adds $20 straight away, very annoying. Then there is shipping, which seems to be internationally priced. Andy.Article: 80914
> > try to call MEMEC ( www.memec.com -> UK ) I'll give them a call, however I don't anticipate much help from them. I've sent them 2 emails and filled out one web form so far! Its sad but ebay has been my best source so far! I know we are an extremely small minority, but being a hobbiest is hard work! Andy.Article: 80915
Xilinx have started selling some stuff direct. I don't know if XCF01s are on list, or if there are any problems, or costs, in getting UK delivery but have a look. Alternatively try both halves of Memec with the franchaise. They are technically in competition. I would use the telephone for maximum result. If after trying all that you still have a problem give me a call and I'll try and assist. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Andy Main" <a.s.main@gmail.com> wrote in message news:4235a5b2$0$26724$cc9e4d1f@news.dial.pipex.com... > Hi there, > > I still can't find a UK supplier for a low quantity (8) of XCF01 memory. > Memec don't reply to my messages, and the only supplier in the states > I found (nuhorizons) were charging $75 to ship to me! > > Can anyone give me a pointer as to (a) somewhere I can get the in the > UK, or (b) somewhere that will ship to me at a normal cost. > > Thanks, > > Andy.Article: 80916
Thanks. I read the note and agree that the problem could be related to some kind of transient. If the Done/Program pin were stuck in the low state it appears that the device will still reset by monitoring the state of the Reset pin. "A re-program is initiated.when a configured XC3000 series device senses a High-to-Low transition and subsequent >6 us Low level on the DONE/PROG package pin, or, if this pin is externally held permanently Low, a High-to-Low transition and subsequent >6 us Low time on the RESET package pin." The note to your link suggests that setting Reset high for > 6us then setting it and the Prog/Done pin low for > 6us will bring the device back to the clear configuration state. Looking at the loader code, this is pretty much what is being done on every load. The Reset normally idles high and it along with the Program pin are pulled low for 7.5us. I verified this as well. Doing this does not make the device exit this strange mode. So far, the only thing that seems to clear it from this state is a hard power down. As a test, I forced the Prog pin low on one device in the chain. The pin latches low as expected. I then forced a few clock cycles to get the device into some mid data stream mode. I then pulled the reset low and started a normal configuration. The part did recover, releasing the Prog. pin at the end of the programming cycle. So, at least this all seems to work. My next step is to conduct noise onto the supply to see if I can replicate the problem. Because this happens so infrequent, it is next to impossible to find any other clues. Brian Davis wrote: > Philip wrote: > > > > The solution may involve changes to your power supply, such that if > > the voltage ever dips below say 4.5V, you make sure it goes all the > > way down to 0V, for maybe 100 mS, before it comes back up. > > > > I also have vague recollections of this problem ( needing to > completely shut off power to 0V recover ) > > Some googling turned up this copy of an old Xilinx > answer record #134 (watch line breaks on the link): > > http://www.nalanda.nitc.ac.in/industry/appnotes/xilinx/documents/techdocs/134.htm > > > BrianArticle: 80917
I tried a few different tests. I first reduced the supply votage on the Xilinx devices by 500mV and ran the system as normal, but saw no problems. I then reduced the supply voltage until I started to see problem with the function of the devices (this was around 3.5 volts), but as soon as the supply was returned to normal the parts would function normal as well. Using a bias T I then injected a sinewave onto the supply line. I ran the supply at 4.5 volts and injected a 500mV signal. I did multiple sweeps from 100KHz up to a bit over a GHz and saw no problems. I then ran the same test with the supply at 5 volts and again saw no problems. So far, it would appear the problem is not related to the supply voltage or operating temperature.Article: 80918
I find Verilog a heck of a lot easier and results in more compact code vs. VHDL. Verilog-2001 seems to have what was missing between the last version and VHDL (generate, configurations, good file I/O, lots of other new stuff). AHDL was the easiest to write, but supported only by Altera, therefore no coded testbenching. -- PeteArticle: 80919
In article <42352513@clear.net.nz>, Jim Granville wrote: > Eric Smith wrote: >> >> Some of the fancier UARTs (e.g., some Motorola/Freescale microcontrollers) >> take samples at 7, 8, and 9 clocks into the bit cell, and will report noise >> if they are not all equal. > > Another example : The 80C51 UART sampled 3 times, in mid-bit, and does a > majority vote. It does not flag any errors on this. > > Some UARTs start looking for a START egde, at the END > of the Stop bit. As an excercise, consider if this is a good idea, and > if not, what would be better ? On a slightly different note, does anyone know why most serial protocols use simple voltage levels to denote a logic 0 or 1? I admit I'm no expert but I recall from my A-level electronics an edge-triggered system where a '0' would be (say) low-followed-by-high whereas a '1' would be high-followed-by-low. Yes, this means _at_least_ twice as many voltage transitions per bit but I would have thought that given its greater resilience mismatched clocks or any stray capacitance it would be worth the trade off. Just curious... -- Andrew Smallshaw andrews@sdf.lonestar.orgArticle: 80920
Gabor wrote:
> Verilog 2001 does support generate. It also supports arrays of
> instances which are often easier to use than generate for many
> applications.
So I'll have a look at it.
> Another thing to remember about Verilog is that it is less rigid
> about type-checking.
Yes, this is a big disadvantage.
Best regards
Piotr Wyderski
Article: 80921Hi, Has anyone successfully used the playxsvf501b.exe utility yet? In IMPACT, I went into the file mode and create SVF file, then use svf2xsvf502.exe to create the SVF file. But when I use the playxsvf501b, its give me an unfinite loop, TCK toggle every line, and TMS and TDI are '0' on every line. I don't see a TDO output. All I want is to create an XSVF file that will program my Xilinx Spartan3 chip. Thanks, AnnArticle: 80922
Georg Acher wrote:
> Hm, you can define components in packages and just "use" them. So
> you don't need to cut'n'paste the interface into each architecture.
Thanks, I didn't know about that. Looks like one of my problems has been
solved.
Best regards
Piotr Wyderski
Article: 80923Sorry for not being prompt in replying to your mail. I was out for town for a week. The MK 2069 generates a 27 MHz clock. The 27 MHz clock generated by 2069 is locked to the Hsync, but when no Hsync it still generates a 27 Mhz clock..which is a little wierd. Well I the clock generated by the PLL (after it is locked to the Hsync) is not exactly a 50 % duty cycle square wave. Can I use a square wave shaper? Will I lose the locked information if I do that. BTW its my hobby to design projects for Televison Broadcasting applications....well if it works it might go commercial Really appreciate ur helpArticle: 80924
design wrote: > Hi all, > I am developing my first circuit board with FPGA. > Trying to make a circuit board without PROM for FPGA programming so > just using the FPGA, hence cutting down the cost as well for security. > Planning on using the JTAG method where the bit file is used to > directly program the FPGA. > In this case since the FPGA needs to be programmed every time on > powerup, is there a cache in the FPGA which stores the bitstream and > configures the FPGA each time on powerup. > Or does the bitstream need to be downloaded each time when the FPGA is > powered up unlike the PROM method where the FPGA gets configured from > the PROM. > I couldnt find any documentation on Xilinx website for these questions. > So any help with this is greatly appreciated. > > Thanks & regards Don't know what size fpga you need, but you can forget about the boot prom if you want by using the XP fpga. It is sram + flash on the same die. http://www.latticesemi.com/products/fpga/xp/index.cfm
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