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Threads Starting Dec 2000
27641: 00/12/01: Recruit Express: Off subject-WIRELESS H/W S/W - pre IPO - San Jose
27642: 00/12/01: frank johson: jtag for fpga
27645: 00/12/01: Marc Roche: Re: jtag for fpga
27652: 00/12/01: Rick Filipkiewicz: Re: jtag for fpga
27774: 00/12/07: <harveytwyman@my-deja.com>: Re: jtag for fpga
27830: 00/12/11: Jamie Lokier: Re: jtag for fpga
27904: 00/12/14: <harveytwyman@my-deja.com>: Re: jtag for fpga
28013: 00/12/19: Steven Zedeck: Re: jtag for fpga
28014: 00/12/19: Steven Zedeck: Re: jtag for fpga
28012: 00/12/19: Steven Zedeck: Re: jtag for fpga
28059: 00/12/20: <harveytwyman@my-deja.com>: Re: jtag for fpga
27650: 00/12/01: chsw: glbl
27668: 00/12/01: Paulo Dutra: Re: glbl
27683: 00/12/02: chsw: Re: glbl
27687: 00/12/03: Srinivasan Venkataramanan: Re: glbl
27688: 00/12/02: chsw: Re: glbl
27653: 00/12/01: Dan: DLLs driving DLLs in Virtex.
27658: 00/12/01: Keith R. Williams: Re: DLLs driving DLLs in Virtex.
27663: 00/12/01: Ray Andraka: Re: DLLs driving DLLs in Virtex.
27682: 00/12/01: Vikram Pasham: Re: DLLs driving DLLs in Virtex.
27656: 00/12/01: Nisreen Taiyeby: fpga: 32 bit parity generation in 4 ns for virtexE
27657: 00/12/01: Nisreen Taiyeby: fpga: 32 bit parity generation in 4 ns for virtexE
27759: 00/12/06: Walter Haas: Re: fpga: 32 bit parity generation in 4 ns for virtexE
27828: 00/12/11: David Hawke: Re: fpga: 32 bit parity generation in 4 ns for virtexE
27831: 00/12/11: Duane: Re: fpga: 32 bit parity generation in 4 ns for virtexE
27661: 00/12/01: Nicolas Matringe: Xilinx's www down again?
27666: 00/12/01: Olivier Regnault: Re: Xilinx's www down again?
27664: 00/12/01: Guibert, Martin: xilinx NGDanno
27667: 00/12/01: Tim Jaynes: Re: xilinx NGDanno
27669: 00/12/01: InGenius Engineering: Hey there anybody!!
27679: 00/12/02: Muzaffer Kal: Re: Hey there anybody!!
27690: 00/12/03: Rick Filipkiewicz: Re: Hey there anybody!!
27695: 00/12/04: S. Ramirez: Re: Hey there anybody!!
27802: 00/12/09: Hal Murray: Re: Hey there anybody!!
27681: 00/12/02: chris.wei: pcmcia host controller ??
27684: 00/12/02: <peter_raeth@juno.com>: Column on FPGAs
27689: 00/12/03: Rick Collins: Issues with Spartan II
27691: 00/12/03: Nial Stewart: Re: Issues with Spartan II
27696: 00/12/03: Rick Collins: Re: Issues with Spartan II
27698: 00/12/04: Nial Stewart: Re: Issues with Spartan II
27708: 00/12/04: Muzaffer Kal: Re: Issues with Spartan II
27712: 00/12/04: Nial Stewart: Re: Issues with Spartan II
27714: 00/12/04: Muzaffer Kal: Re: Issues with Spartan II
27692: 00/12/03: Muzaffer Kal: Re: Issues with Spartan II
27697: 00/12/04: Rick Collins: Re: Issues with Spartan II
27706: 00/12/04: Dan: Spartan II poor avaiablility. Strategic decision or technical problems ?
27711: 00/12/04: Peter Alfke: Re: Issues with Spartan II
27715: 00/12/04: Rick Filipkiewicz: Re: Issues with Spartan II
27717: 00/12/04: Andy Peters: Re: Issues with Spartan II
27722: 00/12/05: <kolja@prowokulta.org>: Re: Issues with Spartan II
27734: 00/12/05: Eric Smith: Re: Issues with Spartan II
27741: 00/12/05: <kolja@prowokulta.org>: Re: Issues with Spartan II
27742: 00/12/05: Rick Filipkiewicz: Re: Issues with Spartan II
27890: 00/12/13: Andy Peters: Re: Issues with Spartan II
27894: 00/12/14: Rick Filipkiewicz: Re: Issues with Spartan II
27738: 00/12/05: Austin Franklin: Re: Issues with Spartan II
27753: 00/12/06: Gary Watson: Re: Issues with Spartan II
27755: 00/12/06: John Janssen: Re: Issues with Spartan II
27773: 00/12/07: Stuart J Adams: Re: Issues with Spartan II
27694: 00/12/03: <gazit@my-deja.com>: which I/O pin belongs to each bank
27710: 00/12/04: Andy Peters: Re: which I/O pin belongs to each bank
27724: 00/12/05: <gazit@my-deja.com>: Re: which I/O pin belongs to each bank
27743: 00/12/05: Rick Filipkiewicz: Re: which I/O pin belongs to each bank
27803: 00/12/09: Hal Murray: Re: which I/O pin belongs to each bank
27713: 00/12/04: John Ayer: Re: which I/O pin belongs to each bank
27729: 00/12/05: <gazit@my-deja.com>: Re: which I/O pin belongs to each bank
27718: 00/12/05: Chuck Woodring: ORCAD EXPRESS / Synplicity (feeling stuck)
27731: 00/12/05: Greg Neff: Re: ORCAD EXPRESS / Synplicity (feeling stuck)
27747: 00/12/06: Rick Collins: Re: ORCAD EXPRESS / Synplicity (feeling stuck)
27719: 00/12/04: Arrigo Benedetti: getting 100% timing path coverage
27723: 00/12/05: <xiaoqiang@my-deja.com>: test
27727: 00/12/05: Jamie Sanderson: Route/Logic delay ratio
27730: 00/12/05: Muzaffer Kal: Re: Route/Logic delay ratio
27728: 00/12/05: Jonas Weiss: ALTERA MAX PLUS LPM FIFOs
27746: 00/12/06: Kenneth Porter: Re: ALTERA MAX PLUS LPM FIFOs
27749: 00/12/06: Jonas Weiss: Re: ALTERA MAX PLUS LPM FIFOs
27748: 00/12/06: Jean Nicolle: Re: ALTERA MAX PLUS LPM FIFOs
27791: 00/12/08: Jonas Weiss: Re: ALTERA MAX PLUS LPM FIFOs
27733: 00/12/05: Gary Spivey: Gate Level Simulation Questions
27736: 00/12/05: Tim Jaynes: Re: Gate Level Simulation Questions
27744: 00/12/05: Rick Filipkiewicz: Re: Gate Level Simulation Questions
27751: 00/12/06: <eml@riverside-machines.com.NOSPAM>: Re: Gate Level Simulation Questions
27735: 00/12/06: Dean Armstrong: Using CPLD to configure SpartanII from parallel ROM.
27737: 00/12/05: Mike: Re: Using CPLD to configure SpartanII from parallel ROM.
27739: 00/12/05: Mike: Re: Using CPLD to configure SpartanII from parallel ROM.
27757: 00/12/07: Dean Armstrong: Re: Using CPLD to configure SpartanII from parallel ROM.
27740: 00/12/06: bliss: Title:Interfacing between ECL and LVDS?
27745: 00/12/06: Saqib: ADAPTIVE FILTER
27762: 00/12/06: Vikram Pasham: Re: ADAPTIVE FILTER
27889: 00/12/13: Andy Peters: Re: ADAPTIVE FILTER
27752: 00/12/06: chsw: what's meaning?
27756: 00/12/06: Srinivasan Venkataramanan: Re: what's meaning?
27754: 00/12/06: Bassem: FPGA starter kit
27758: 00/12/06: John Tasgal: Re: FPGA starter kit
27770: 00/12/07: Wolfgang Loewer: Re: FPGA starter kit
27911: 00/12/14: Bassem: Re: FPGA starter kit
27934: 00/12/15: emanuel stiebler: Re: FPGA starter kit
27781: 00/12/08: Tony Burch: Re: FPGA starter kit
27795: 00/12/08: Olivier REGNAULT: Re: FPGA starter kit
27801: 00/12/08: Rick Filipkiewicz: Re: FPGA starter kit
27760: 00/12/06: Jerry Pongstaporn: dual port ram for altera
27761: 00/12/06: <quittj@my-deja.com>: Re: dual port ram for altera
27811: 00/12/09: Ray Andraka: Re: dual port ram for altera
27839: 00/12/12: <alexkarpel@my-deja.com>: Re: dual port ram for altera
27842: 00/12/12: Magnus Homann: Re: dual port ram for altera
27848: 00/12/12: Ray Andraka: Re: dual port ram for altera
27868: 00/12/13: Karpel Alex: Re: dual port ram for altera
27961: 00/12/18: <bobdittmar@my-deja.com>: Re: dual port ram for altera
27975: 00/12/18: Peter Alfke: Re: dual port ram for altera
27991: 00/12/19: <bobdittmar@my-deja.com>: Re: dual port ram for altera
27995: 00/12/18: Peter Alfke: Re: dual port ram for altera
27996: 00/12/19: Jamie Lokier: Re: dual port ram for altera
28015: 00/12/19: <bobdittmar@my-deja.com>: Re: dual port ram for altera
28044: 00/12/19: Peter Alfke: Re: dual port ram for altera
28053: 00/12/20: Hal Murray: Re: dual port ram for altera
28075: 00/12/20: Peter Alfke: Re: dual port ram for altera
28083: 00/12/20: Philip Freidin: Re: dual port ram for altera
28084: 00/12/20: Peter Alfke: Re: dual port ram for altera
28091: 00/12/20: Ray Andraka: Re: dual port ram for altera
28100: 00/12/21: Hal Murray: Metastability rant (was Re: dual port ram for altera)
28114: 00/12/21: Peter Alfke: Re: Metastability rant (was Re: dual port ram for altera)
28117: 00/12/21: Peter Alfke: Re: Metastability rant (was Re: dual port ram for altera)
28155: 00/12/23: Rick Filipkiewicz: Re: Metastability rant (was Re: dual port ram for altera)
27764: 00/12/06: <Veteran_NYC_Shopper@qudumi.org>: Attention NYC Shoppers & Visitors - Beware of Rip-off SY Stores!!! ...... slNZc2N54
27765: 00/12/07: V Ram: FPGA Express & VHDL files
27769: 00/12/07: Kent Orthner: Re: FPGA Express & VHDL files
27888: 00/12/13: Andy Peters: Re: FPGA Express & VHDL files
27767: 00/12/07: anup: Need help regarding Partial reconfiguration
27771: 00/12/07: John Ayer: Re: Need help regarding Partial reconfiguration
27785: 00/12/08: anup: Re: Need help regarding Partial reconfiguration
27797: 00/12/08: Phil James-Roxby: Re: Need help regarding Partial reconfiguration
27817: 00/12/10: anup: Re: Need help regarding Partial reconfiguration
27768: 00/12/06: Joe Wetstein: verilog and arch
27772: 00/12/07: Ramanathan: Test Bench
27775: 00/12/07: Muzaffer Kal: Re: Test Bench
27887: 00/12/13: Andy Peters: Re: Test Bench
27776: 00/12/07: Paul Taylor: XC9500/9500XL CPLD Clocks
27779: 00/12/07: Rick Filipkiewicz: Re: XC9500/9500XL CPLD Clocks
27784: 00/12/07: Bob Doyle: Re: XC9500/9500XL CPLD Clocks
27780: 00/12/08: S. Ramirez: Re: XC9500/9500XL CPLD Clocks
27782: 00/12/08: Hal Murray: Re: XC9500/9500XL CPLD Clocks
27783: 00/12/08: Sherdyn: IP for De-interleaver
27786: 00/12/08: Dan: Mistake - I was trying to send elsewhere
27787: 00/12/08: <nhduong@my-deja.com>: PLCC adapter
27790: 00/12/08: Leon Heller: Re: PLCC adapter
27794: 00/12/09: Tony Burch: Re: PLCC adapter
27788: 00/12/08: Rick Collins: Altera free development tools
27796: 00/12/08: Nial Stewart: Re: Altera free development tools
27798: 00/12/08: Olivier R: Re: Altera free development tools
27824: 00/12/11: fred: Re: Altera free development tools
27837: 00/12/12: <bob_42690@my-deja.com>: Re: Altera free development tools
27789: 00/12/08: Kent Orthner: Spartan-II & Vertex Pin compatability.
27792: 00/12/08: <harveytwyman@my-deja.com>: Re-Reverse-engineering FPGA's"
27800: 00/12/08: Randy Nachtrieb: FS: ADVICE RTOS In Circuit Emulator
27806: 00/12/09: Hal Murray: Linear Regulator troubles
27809: 00/12/09: Philip Freidin: Re: Linear Regulator troubles
27812: 00/12/10: Hal Murray: Re: Linear Regulator troubles
27810: 00/12/09: Austin Lesea: Re: Linear Regulator troubles
27813: 00/12/09: Peter Alfke: Re: Linear Regulator troubles
27816: 00/12/09: Eric Smith: Re: Linear Regulator troubles
27819: 00/12/11: Hal Murray: Re: Linear Regulator troubles
27820: 00/12/10: Austin Lesea: Re: Linear Regulator troubles
27821: 00/12/10: Austin Lesea: Re: Linear Regulator troubles
27822: 00/12/11: Philip Freidin: Re: Linear Regulator troubles
27823: 00/12/11: Rick Filipkiewicz: Re: Linear Regulator troubles
27835: 00/12/11: Hal Murray: Re: Linear Regulator troubles
27840: 00/12/12: Hal Murray: Re: Linear Regulator troubles
27844: 00/12/12: Nial Stewart: Re: Linear Regulator troubles
27814: 00/12/09: Peter Alfke: Re: Linear Regulator troubles
27815: 00/12/09: Peter Alfke: Re: Linear Regulator troubles
27807: 00/12/09: Nguyentule: Consultant needed. Xilinx Spartan 2.
27808: 00/12/09: Nguyentule: WTB 500-1000 Xilinx Spartan1 XSC30 or XCS40 chips
27825: 00/12/11: Marc Reinert: Cannot get chip's information from Synopsys
27827: 00/12/11: Kent Orthner: Re: Cannot get chip's information from Synopsys
27826: 00/12/11: Tesisti DSPLab: ERROR: The net has more than one driver?
27886: 00/12/13: Andy Peters: Re: ERROR: The net has more than one driver?
27919: 00/12/14: Qian Zhang: Re: ERROR: The net has more than one driver?
27829: 00/12/11: Nisreen Taiyeby: Fpga:How can I specify RLOC constraint in Leonardo
28216: 01/01/01: arb name: Re: Fpga:How can I specify RLOC constraint in Leonardo
27832: 00/12/11: EuroEDA Information: VHDL Studio for Linux
27833: 00/12/11: Dave Nadler: VHDL technique for synchronizer ?
27834: 00/12/11: Peter Alfke: Re: VHDL technique for synchronizer ?
27913: 00/12/14: Jamie Sanderson: Re: VHDL technique for synchronizer ?
27836: 00/12/12: Nick: ActelDeskTop Macro fanout problem
27843: 00/12/12: rk: Re: ActelDeskTop Macro fanout problem
27858: 00/12/12: John Eaton: Re: ActelDeskTop Macro fanout problem
27838: 00/12/12: Barry Schneider: Verilog and VHDL people wanted!!
27841: 00/12/12: Damir Danijel Zagar: Xilinx CPLD capable of driving LEDs
27852: 00/12/12: PeteD: Re: Xilinx CPLD capable of driving LEDs
27854: 00/12/12: Peter Alfke: Re: Xilinx CPLD capable of driving LEDs
27845: 00/12/12: Michael Boehnel: Synplify PRO 6.1 + Foundation 3.1i
27846: 00/12/12: Magnus Homann: Re: Synplify PRO 6.1 + Foundation 3.1i
27847: 00/12/12: Nial Stewart: Re: Synplify PRO 6.1 + Foundation 3.1i
27849: 00/12/12: Michael Boehnel: Re: Synplify PRO 6.1 + Foundation 3.1i
27850: 00/12/12: Joel Kolstad: Re: Synplify PRO 6.1 + Foundation 3.1i
27853: 00/12/12: Michael Boehnel: Re: Synplify PRO 6.1 + Foundation 3.1i
27860: 00/12/13: Kent Orthner: Re: Synplify PRO 6.1 + Foundation 3.1i
27866: 00/12/13: Michael Boehnel: Re: Synplify PRO 6.1 + Foundation 3.1i
27851: 00/12/12: Nial Stewart: Re: Synplify PRO 6.1 + Foundation 3.1i
27856: 00/12/12: Ray Andraka: Re: Synplify PRO 6.1 + Foundation 3.1i
27872: 00/12/13: <eml@riverside-machines.com.NOSPAM>: Re: Synplify PRO 6.1 + Foundation 3.1i
27881: 00/12/13: Nial Stewart: Re: Synplify PRO 6.1 + Foundation 3.1i
27898: 00/12/13: Phil Hays: Re: Synplify PRO 6.1 + Foundation 3.1i
27855: 00/12/12: Joel Smith: Fpga Newbie
27857: 00/12/12: Terry Hicks: Re: Fpga Newbie
27859: 00/12/12: Qian Zhang: TWo CLOKS in VHDL synthesis
27861: 00/12/13: Kent Orthner: Re: TWo CLOKS in VHDL synthesis
27862: 00/12/12: Qian Zhang: Re: TWo CLOKS in VHDL synthesis
27863: 00/12/13: Kent Orthner: Re: TWo CLOKS in VHDL synthesis
27864: 00/12/13: Kirk A Daley: Synthesis Tools
27865: 00/12/12: Nisreen Taiyeby: fpga :CLB locking prevents flops to be in IOB's
27867: 00/12/13: Andreas Doering: Re: fpga :CLB locking prevents flops to be in IOB's
27869: 00/12/13: <mark4415@my-deja.com>: Hold time constraint in Xilinx?
27870: 00/12/13: Mark Russell: Hold time constraints in virtex?
27874: 00/12/13: Rick Filipkiewicz: Re: Hold time constraints in virtex?
28005: 00/12/19: Mark Russell: Re: Hold time constraints in virtex?
28036: 00/12/19: Peter Alfke: Re: Hold time constraints in virtex?
28042: 00/12/19: Hal Murray: Re: Hold time constraints in virtex?
27871: 00/12/13: Ralph Friedrich: Configuration : XC4000
27873: 00/12/13: Marcel Melters: Dual-ported RAM instantiation in Virtex-E ?
27875: 00/12/13: Vikram Pasham: Re: Dual-ported RAM instantiation in Virtex-E ?
27877: 00/12/13: Colm Clancy: Re: Dual-ported RAM instantiation in Virtex-E ?
27879: 00/12/13: Marcel Melters: Re: Dual-ported RAM instantiation in Virtex-E ?
27897: 00/12/14: Kent Orthner: Re: Dual-ported RAM instantiation in Virtex-E ?
27909: 00/12/14: Colm Clancy: Re: Dual-ported RAM instantiation in Virtex-E ?
27910: 00/12/14: Marcel Melters: Re: Dual-ported RAM instantiation in Virtex-E ?
27899: 00/12/14: Assaf Sarfati: Re: Dual-ported RAM instantiation in Virtex-E ?
27936: 00/12/15: Newsbrowser: Re: Dual-ported RAM instantiation in Virtex-E ?
27876: 00/12/13: Nicolas Matringe: Setup violation
27882: 00/12/13: Peter Alfke: Re: Setup violation
27883: 00/12/13: Nicolas Matringe: Re: Setup violation
27920: 00/12/15: Michael Randelzhofer: Re: Setup violation
27931: 00/12/15: <eml@riverside-machines.com.NOSPAM>: Re: Setup violation
27937: 00/12/15: Rick Filipkiewicz: Re: Setup violation
27965: 00/12/18: Ray Andraka: Re: Setup violation
27979: 00/12/18: Peter Alfke: Re: Setup violation
27981: 00/12/18: Ray Andraka: Re: Setup violation
27988: 00/12/19: Greg Neff: Re: Setup violation
27994: 00/12/18: Peter Alfke: Re: Setup violation
28006: 00/12/19: Søren A.Møller: Re: Setup violation
28023: 00/12/19: Peter Alfke: Re: Setup violation
28018: 00/12/19: Greg Neff: Re: Setup violation
28026: 00/12/19: Peter Alfke: Re: Setup violation
28051: 00/12/19: Philip Freidin: Re: Setup violation
27982: 00/12/18: Hal Murray: Re: Setup violation
27984: 00/12/18: Rick Filipkiewicz: Re: Setup violation
27985: 00/12/18: Peter Alfke: Re: Setup violation
27878: 00/12/13: Franz Hollerer: Programming Altera and Xilinx FPGAs with JTAG
27880: 00/12/13: Etienne Racine: Re: Programming Altera and Xilinx FPGAs with JTAG
27884: 00/12/13: Theron Hicks: really fast counter in SpartanXL?
27896: 00/12/13: Peter Alfke: Re: really fast counter in SpartanXL?
28055: 00/12/20: Hal Murray: Re: really fast counter in SpartanXL?
28072: 00/12/20: Theron Hicks: Re: really fast counter in SpartanXL? THANKS!
28076: 00/12/20: Peter Alfke: Re: really fast counter in SpartanXL?
28085: 00/12/20: Peter Alfke: Re: really fast counter in SpartanXL?
28110: 00/12/21: <eml@riverside-machines.com.NOSPAM>: Re: really fast counter in SpartanXL?
28126: 00/12/22: Jim Granville: Re: really fast counter in SpartanXL?
28141: 00/12/22: Magnus Homann: Re: really fast counter in SpartanXL?
28187: 00/12/27: Kevin Neilson: Re: really fast counter in SpartanXL?
28168: 00/12/23: markp: Re: really fast counter in SpartanXL?
28170: 00/12/23: Peter Alfke: Re: really fast counter in SpartanXL?
28176: 00/12/24: Simon Bacon: Re: really fast counter in SpartanXL?
28191: 00/12/27: Peter Alfke: Re: really fast counter in SpartanXL?
28199: 00/12/28: markp: Re: really fast counter in SpartanXL?
28201: 00/12/28: Peter Alfke: Re: really fast counter in SpartanXL?
28232: 01/01/03: Hal Murray: Re: really fast counter in SpartanXL?
28202: 00/12/28: Hal Murray: Re: really fast counter in SpartanXL?
28827: 01/01/25: Scott Taylor: Re: really fast counter in SpartanXL?
28838: 01/01/25: Peter Alfke: Re: really fast counter in SpartanXL?
28858: 01/01/26: Ray Andraka: Re: really fast counter in SpartanXL?
28866: 01/01/26: Peter Alfke: Re: really fast counter in SpartanXL?
27891: 00/12/13: Martin Heimlicher: How do I specify clock skew in the Altera Quartus tool ?
27892: 00/12/13: Martin Heimlicher: Multicycle timing requirements in Altera Quartus
27935: 00/12/15: Wolfgang Loewer: Re: Multicycle timing requirements in Altera Quartus
27893: 00/12/13: Martin Heimlicher: Is it necessary to synchronize the reset signal in an FPGA ?
27895: 00/12/14: Jonas Thor: Re: Is it necessary to synchronize the reset signal in an FPGA ?
27914: 00/12/14: Jamie Sanderson: Re: Is it necessary to synchronize the reset signal in an FPGA ?
27998: 00/12/19: Hal Murray: Re: Is it necessary to synchronize the reset signal in an FPGA ?
28093: 00/12/20: <eml@riverside-machines.com.NOSPAM>: Re: Is it necessary to synchronize the reset signal in an FPGA ?
28099: 00/12/21: Hal Murray: Re: Is it necessary to synchronize the reset signal in an FPGA ?
28111: 00/12/21: <eml@riverside-machines.com.NOSPAM>: Re: Is it necessary to synchronize the reset signal in an FPGA ?
28134: 00/12/22: Hal Murray: Re: Is it necessary to synchronize the reset signal in an FPGA ?
28156: 00/12/23: Rick Filipkiewicz: Re: Is it necessary to synchronize the reset signal in an FPGA ?
27918: 00/12/14: Philip Freidin: Re: Is it necessary to synchronize the reset signal in an FPGA ?
27980: 00/12/18: Peter: Re: Is it necessary to synchronize the reset signal in an FPGA ?
28078: 00/12/20: Andrew Ince: Re: Is it necessary to synchronize the reset signal in an FPGA ?
28104: 00/12/21: <pinhas@my-deja.com>: synchronize and split reset
27900: 00/12/14: Damir Danijel Zagar: Verilog or VHDL
27908: 00/12/14: Jason A. Daughenbaugh: Re: Verilog or VHDL
27912: 00/12/14: Eduardo Augusto Bezerra: Re: Verilog or VHDL
27966: 00/12/18: Victor Schutte: Re: Verilog or VHDL
27915: 00/12/14: Jamie Sanderson: Re: Verilog or VHDL
27921: 00/12/15: Rick Filipkiewicz: Re: Verilog or VHDL
27933: 00/12/15: <eml@riverside-machines.com.NOSPAM>: Re: Verilog or VHDL
27938: 00/12/15: Rick Filipkiewicz: Re: Verilog or VHDL
27940: 00/12/15: Kim Gunnar Enkovaara: Re: Verilog or VHDL
27943: 00/12/15: x-guy@hotmail.com: Re: Verilog or VHDL
27945: 00/12/16: Rick Filipkiewicz: Re: Verilog or VHDL
27948: 00/12/16: Srinivasan Venkataramanan: Re: Verilog or VHDL
27949: 00/12/16: Kim Gunnar Enkovaara: Re: Verilog or VHDL
27955: 00/12/17: Srinivasan Venkataramanan: Re: Verilog or VHDL
28203: 00/12/29: <jaime.aranguren@ieee.org>: Re: Verilog or VHDL
28218: 01/01/01: Joel Kolstad: Re: Verilog or VHDL
27977: 00/12/18: Jamie Sanderson: Re: Verilog or VHDL
28046: 00/12/20: Rick Filipkiewicz: Re: Verilog or VHDL
28094: 00/12/20: <eml@riverside-machines.com.NOSPAM>: Re: Verilog or VHDL
27917: 00/12/14: glen herrmannsfeldt: Re: Verilog or VHDL
27924: 00/12/15: S. Ramirez: Re: Verilog or VHDL
27964: 00/12/18: Ray Andraka: Re: Verilog or VHDL
27990: 00/12/19: S. Ramirez: Re: Verilog or VHDL
27960: 00/12/18: <bobdittmar@my-deja.com>: Re: Verilog or VHDL
27973: 00/12/18: Andy Peters: Re: Verilog or VHDL
28174: 00/12/24: Kim Gunnar Enkovaara: Re: Verilog or VHDL
28179: 00/12/24: Srinivasan Venkataramanan: Re: Verilog or VHDL
28182: 00/12/25: Kim Gunnar Enkovaara: Re: Verilog or VHDL
27901: 00/12/14: Jerry: Spartan configuration : Why Done returns to Low?
27902: 00/12/14: Jerry: Re: Spartan configuration : Why Done returns to Low?
27907: 00/12/14: Thomas Karlsson: Re: Spartan configuration : Why Done returns to Low?
27916: 00/12/14: Philip Freidin: Re: Spartan configuration : Why Done returns to Low?
27923: 00/12/14: Jerry: Re: Spartan configuration : Why Done returns to Low?
27971: 00/12/18: Jerry: Re: Spartan configuration : Why Done returns to Low?
27974: 00/12/18: Rick Filipkiewicz: Re: Spartan configuration : Why Done returns to Low?
27903: 00/12/14: Damir Danijel Zagar: Decoding output from incremental encoder...
27905: 00/12/14: Klaus Falser: Re: Decoding output from incremental encoder...
27906: 00/12/14: Damir Danijel Zagar: Re: Decoding output from incremental encoder...
27922: 00/12/15: Dean Armstrong: Providing a configuration header for Spartan II
27925: 00/12/15: Saqib: CSD OR DISTRIBUTED ARITHMETIC?
27963: 00/12/18: Ray Andraka: Re: CSD OR DISTRIBUTED ARITHMETIC?
27926: 00/12/14: Sachin Vaish: Exemplar: max_load=1 gives me fanout=75
27932: 00/12/15: <eml@riverside-machines.com.NOSPAM>: Re: Exemplar: max_load=1 gives me fanout=75
27927: 00/12/15: Martin.J Thompson: Re: Altera free development tools
27969: 00/12/18: Nial Stewart: Re: Altera free development tools
27928: 00/12/15: Ludovic Lemenuel: Semiconductor process engineers needed
27941: 00/12/15: Andy Peters: Re: Semiconductor process engineers needed
27929: 00/12/15: Ludovic Lemenuel: Semiconductor process engineers needed
27930: 00/12/15: Jianyong Niu: kalman filter
27939: 00/12/15: Muzaffer Kal: Re: kalman filter
27942: 00/12/15: Andy Krumel: Help configuring Spartan II using processor
27950: 00/12/16: John Larkin: Re: Help configuring Spartan II using processor
27953: 00/12/17: Joel Kolstad: Re: Help configuring Spartan II using processor
27987: 00/12/18: Andy Krumel: Re: Help configuring Spartan II using processor
27986: 00/12/18: Andy Krumel: Re: Help configuring Spartan II using processor
27944: 00/12/16: Guido Pohl: questions regarding external setup & hold time considerations
27957: 00/12/17: Peter Alfke: Re: questions regarding external setup & hold time considerations
27946: 00/12/16: <hchenry@comsoc.com>: FPGA to ASIC conversion
27947: 00/12/16: Muzaffer Kal: Re: FPGA to ASIC conversion
28472: 01/01/14: <pineji@my-deja.com>: Re: FPGA to ASIC conversion
28952: 01/01/31: ed: Re: FPGA to ASIC conversion
27951: 00/12/16: futurebots: WTB: SAB82258, or R82258 in a PLCC package or PGA package
27952: 00/12/16: rob: async interface
27958: 00/12/17: Peter Alfke: Re: async interface
27970: 00/12/18: Martin Heimlicher: Re: async interface
28473: 01/01/14: <pineji@my-deja.com>: Re: async interface
27954: 00/12/17: Axel Jantsch: 4 associate professor/professor positions in System-on-Chip design
27956: 00/12/17: Swift: ActiveHDL 4.1?
27959: 00/12/18: Kent Orthner: Re: ActiveHDL 4.1?
27962: 00/12/18: Ray Andraka: Re: ActiveHDL 4.1?
27989: 00/12/19: S. Ramirez: Re: ActiveHDL 4.1?
28172: 00/12/24: Hien Pham: Re: ActiveHDL 4.1?
27967: 00/12/18: Daniel =?iso-8859-1?Q?Ha=F1czewski?=: JTAG protocol
27976: 00/12/18: Alain Cloet: Re: JTAG protocol
27997: 00/12/19: Klaus Falser: Re: JTAG protocol
28002: 00/12/19: <sulimma@my-deja.com>: Re: JTAG protocol
27968: 00/12/18: Rick Filipkiewicz: Virtex and metastability
27978: 00/12/18: Peter Alfke: Re: Virtex and metastability
28049: 00/12/20: Jonas Thor: Re: Virtex and metastability
28080: 00/12/20: Peter Alfke: Re: Virtex and metastability
28142: 00/12/22: bob elkind: Re: Virtex and metastability
28144: 00/12/23: Jim Granville: Re: Virtex and metastability
28145: 00/12/22: Ron Cline: Re: Virtex and metastability
28246: 01/01/03: bob elkind: Re: Virtex and metastability
27972: 00/12/18: Javier SERRANO: Help with encoder/decoder
28096: 00/12/20: <eml@riverside-machines.com.NOSPAM>: Re: Help with encoder/decoder
28105: 00/12/21: Ben Franchuk: Re: Help with encoder/decoder
28112: 00/12/21: <eml@riverside-machines.com.NOSPAM>: Re: Help with encoder/decoder
28107: 00/12/21: markp: Re: Help with encoder/decoder
28109: 00/12/21: S. Ramirez: Re: Help with encoder/decoder
28118: 00/12/21: markp: Re: Help with encoder/decoder
28119: 00/12/21: S. Ramirez: Re: Help with encoder/decoder
28120: 00/12/21: Greg Neff: Re: Help with encoder/decoder
28124: 00/12/21: <eml@riverside-machines.com.NOSPAM>: Re: Help with encoder/decoder
27983: 00/12/18: John Schewel: Reconfigurable Technology CFP
27992: 00/12/19: <hoyte@ucsu.colorado.edu>: FPGA and Board for Microprocessor Design?
28003: 00/12/19: Dave Vanden Bout: Re: FPGA and Board for Microprocessor Design?
28009: 00/12/20: Tony Burch: Re: FPGA and Board for Microprocessor Design?
28032: 00/12/19: Ben Franchuk: Re: FPGA and Board for Microprocessor Design?
28062: 00/12/20: <sulimma@my-deja.com>: Re: FPGA and Board for Microprocessor Design?
28088: 00/12/20: Neil Franklin: Re: FPGA and Board for Microprocessor Design?
28101: 00/12/21: Tony Burch: Re: FPGA and Board for Microprocessor Design?
28047: 00/12/20: Simon Gornall: Re: FPGA and Board for Microprocessor Design?
28064: 00/12/20: <harveytwyman@my-deja.com>: Re: FPGA and Board for Microprocessor Design?
28123: 00/12/21: M. Simon: Re: FPGA and Board for Microprocessor Design?
27993: 00/12/19: <xiaoqiang@my-deja.com>: simulation with ActiveHDL
27999: 00/12/19: Nial Stewart: 3V -> 5V clock signal level conversion
28001: 00/12/19: Tomppa: Re: 3V -> 5V clock signal level conversion
28007: 00/12/19: Nial Stewart: Re: 3V -> 5V clock signal level conversion
28011: 00/12/19: Søren A.Møller: Re: 3V -> 5V clock signal level conversion
28024: 00/12/19: Peter Alfke: Re: 3V -> 5V clock signal level conversion
28045: 00/12/20: Garry Allen: Re: 3V -> 5V clock signal level conversion
28016: 00/12/19: Robert: Re: 3V -> 5V clock signal level conversion
28020: 00/12/19: Jason Daughenbaugh: Re: 3V -> 5V clock signal level conversion
28028: 00/12/19: Nial Stewart: Re: 3V -> 5V clock signal level conversion
28021: 00/12/19: Greg Neff: Re: 3V -> 5V clock signal level conversion
28027: 00/12/19: Robert: Re: 3V -> 5V clock signal level conversion
28030: 00/12/19: Nial Stewart: Re: 3V -> 5V clock signal level conversion
28031: 00/12/19: Greg Neff: Re: 3V -> 5V clock signal level conversion
28033: 00/12/19: Robert: Re: 3V -> 5V clock signal level conversion
28037: 00/12/19: Greg Neff: Re: 3V -> 5V clock signal level conversion
28038: 00/12/19: Peter Alfke: Re: 3V -> 5V clock signal level conversion
28034: 00/12/19: Robert: Re: 3V -> 5V clock signal level conversion
28039: 00/12/19: Nial Stewart: Re: 3V -> 5V clock signal level conversion
28041: 00/12/19: Greg Neff: Re: 3V -> 5V clock signal level conversion
28052: 00/12/20: Nial Stewart: Re: 3V -> 5V clock signal level conversion
28048: 00/12/20: Kent Orthner: Re: 3V -> 5V clock signal level conversion
28050: 00/12/19: Jim Pennell: Re: 3V -> 5V clock signal level conversion
28086: 00/12/20: Peter Alfke: Re: 3V -> 5V clock signal level conversion
28092: 00/12/20: Ray Andraka: Re: 3V -> 5V clock signal level conversion
28103: 00/12/21: Nial Stewart: Re: 3V -> 5V clock signal level conversion
28128: 00/12/22: Robert: Re: 3V -> 5V clock signal level conversion
28090: 00/12/20: markp: Re: 3V -> 5V clock signal level conversion
28095: 00/12/20: Peter Alfke: Re: 3V -> 5V clock signal level conversion
28098: 00/12/21: markp: Re: 3V -> 5V clock signal level conversion
28115: 00/12/21: Andy Peters: Re: 3V -> 5V clock signal level conversion
28122: 00/12/21: Marc Klingelhofer: Parallel clock termination (Was: 3V -> 5V clock signal level conversion)
28000: 00/12/19: <xiaoqiang@my-deja.com>: how to bind xilinx lib to activeHDL?
28004: 00/12/19: <bfredc@my-deja.com>: Methodology
28043: 00/12/19: Rick Filipkiewicz: Re: Methodology
28153: 00/12/23: Hal Murray: Re: Methodology
28154: 00/12/23: Joel Kolstad: Re: Methodology
28157: 00/12/23: Rick Filipkiewicz: Re: Methodology
28158: 00/12/23: Dave Vanden Bout: Re: Methodology
28195: 00/12/27: <iglasner@zumanetworks.com>: Re: Methodology
28196: 00/12/27: <eml@riverside-machines.com.NOSPAM>: Re: Methodology
28397: 01/01/11: Petter Gustad: Re: Methodology
28008: 00/12/20: Tony Burch: New 200K gate, low cost FPGA proto kit
28010: 00/12/19: Pascal C.: Question about Xilinx pins at high-frequency
28019: 00/12/19: Greg Neff: Re: Question about Xilinx pins at high-frequency
28022: 00/12/19: Pascal C.: Re: Question about Xilinx pins at high-frequency
28029: 00/12/19: Andy Peters: Re: Question about Xilinx pins at high-frequency
28035: 00/12/19: David Hawke: Re: Question about Xilinx pins at high-frequency
28057: 00/12/20: fred: Re: Question about Xilinx pins at high-frequency
28067: 00/12/20: Andrew Ince: Re: Question about Xilinx pins at high-frequency
28079: 00/12/20: David Hawke: Re: Question about Xilinx pins at high-frequency
28069: 00/12/20: Pascal C.: Re: Question about Xilinx pins at high-frequency
28081: 00/12/20: David Hawke: Re: Question about Xilinx pins at high-frequency
28089: 00/12/20: Andy Peters: Re: Question about Xilinx pins at high-frequency
28125: 00/12/21: David Hawke: Re: Question about Xilinx pins at high-frequency
28108: 00/12/21: Pascal C.: Re: Question about Xilinx pins at high-frequency
28139: 00/12/22: <sulimma@my-deja.com>: Re: Question about Xilinx pins at high-frequency
28152: 00/12/23: Hal Murray: Re: Question about Xilinx pins at high-frequency
28245: 01/01/03: Pascal C.: Re: Question about Xilinx pins at high-frequency
28261: 01/01/04: <hirsch_yoav@hotmail.com>: Re: Question about Xilinx pins at high-frequency
28017: 00/12/19: Karl Olsen: Spartan2 and industrial temperatures
28025: 00/12/19: Peter Alfke: Re: Spartan2 and industrial temperatures
28063: 00/12/20: Karl Olsen: Re: Spartan2 and industrial temperatures
28077: 00/12/20: Peter Alfke: Re: Spartan2 and industrial temperatures
28040: 00/12/20: Dean Armstrong: JTAG port electrical specs
28054: 00/12/20: Akito: Methods to speed up timings by hdl?
28058: 00/12/20: Kent Orthner: Re: Methods to speed up timings by hdl?
28065: 00/12/20: fred: Re: Methods to speed up timings by hdl?
28056: 00/12/20: Saqib: HOT AREAS IN FPGAs
28116: 00/12/21: x-guy@hotmail.com: Re: HOT AREAS IN FPGAs
28061: 00/12/20: <harveytwyman@my-deja.com>: Hand Soldering a PQ208 - It looks tough to do
28102: 00/12/20: Steve W.: Re: Hand Soldering a PQ208 - It looks tough to do
28066: 00/12/20: <zdenko.baksa@zg.tel.hr>: ttl in cpld
28068: 00/12/20: Petter Gustad: 18v04 programming
28070: 00/12/20: Russell Tessier: FPGA'2001 Call for Participation
28071: 00/12/20: Benoît: insert a BUFGP in a SPARTAN with foundation3.1
28073: 00/12/20: Paul Bateson: Samsung SDRAM behavioural models
28087: 00/12/20: Andy Peters: Re: Samsung SDRAM behavioural models
28097: 00/12/20: Duane: Re: Samsung SDRAM behavioural models
28106: 00/12/21: Jon Schneider: Simple clock and reset on an Ikos VLE-5M box
28113: 00/12/22: hiro: testbench generation tool
28133: 00/12/22: Hal Murray: Re: testbench generation tool
28121: 00/12/21: <alexboyer@my-deja.com>: XC18V02 programming with xsvf file
28135: 00/12/22: Etienne Racine: Re: XC18V02 programming with xsvf file
28127: 00/12/21: Hul Tytus: "lo profile" PLCC sockets
28148: 00/12/23: <nishioka@my-deja.com>: Re: "lo profile" PLCC sockets
28129: 00/12/22: Austin Franklin: Synplicity and multiple input IOB flops...how to specify which one goes in the IOB?
28132: 00/12/21: Phil Hays: Re: Synplicity and multiple input IOB flops...how to specify which one
28140: 00/12/22: Frederic RIVOALLON: Re: Synplicity and multiple input IOB flops...how to specify which one
28162: 00/12/23: Austin Franklin: Re: Synplicity and multiple input IOB flops...how to specify which one goes in the IOB?
28146: 00/12/22: Magnus Homann: Re: Synplicity and multiple input IOB flops...how to specify which one goes in the IOB?
28161: 00/12/23: Austin Franklin: Re: Synplicity and multiple input IOB flops...how to specify which one goes in the IOB?
28164: 00/12/23: Magnus Homann: Re: Synplicity and multiple input IOB flops...how to specify which one goes in the IOB?
28184: 00/12/25: Austin Franklin: Re: Synplicity and multiple input IOB flops...how to specify which one goes in the IOB?
28160: 00/12/23: Austin Franklin: Re: Synplicity and multiple input IOB flops...how to specify which one goes in the IOB?
28130: 00/12/21: Qian Zhang: PIN NOT FOUND
28131: 00/12/21: Qian Zhang: Implementation Fatal Error
28136: 00/12/22: Stuart J Adams: driving color VGA from FPGA ??
28137: 00/12/22: Georg Acher: Re: driving color VGA from FPGA ??
28138: 00/12/22: Dave Vanden Bout: Re: driving color VGA from FPGA ??
28143: 00/12/22: Arrigo Benedetti: Re: driving color VGA from FPGA ??
28180: 00/12/24: jdhduighejhvkxjcn: Re: driving color VGA from FPGA ??
28248: 01/01/03: Steve Nordhauser: Re: driving color VGA from FPGA ??
28147: 00/12/23: <longwayhome@my-deja.com>: Question about programming xcv100
28150: 00/12/23: Ray Andraka: Re: Question about programming xcv100
28163: 00/12/23: <longwayhome@my-deja.com>: Re: Question about programming xcv100
28159: 00/12/23: Ben Franchuk: evolving bitstreams
28190: 00/12/27: Phil James-Roxby: Re: evolving bitstreams
28167: 00/12/23: Peter Alfke: Re: Question about programming xcv100
28171: 00/12/24: <longwayhome@my-deja.com>: Re: Question about programming xcv100
28173: 00/12/24: Muzaffer Kal: Re: Question about programming xcv100
28175: 00/12/24: Simon Bacon: Re: Question about programming xcv100
28177: 00/12/24: Philip Freidin: Re: Question about programming xcv100
28178: 00/12/24: Neil Franklin: Re: Question about programming xcv100
28185: 00/12/25: <longwayhome@my-deja.com>: Re: Question about programming xcv100
28200: 00/12/28: Phil James-Roxby: Re: Question about programming xcv100
28188: 00/12/27: Domagoj: Re: Question about programming xcv100
28198: 00/12/28: Philip Freidin: Re: Question about programming xcv100
28229: 01/01/03: Ray Andraka: Re: Question about programming xcv100
28192: 00/12/27: Delon Levi: Re: Question about programming xcv100
28149: 00/12/23: Dan: VGA compatible design for a Xilinx FPGA needed.
28151: 00/12/23: keat3: MAKE LOTS OF MONEY!! NOT A SCAM!! IT REALLY WORKS!!
28166: 00/12/23: R Sefton: spartan-II power supply sequencing problem
28181: 00/12/25: <pinhas@my-deja.com>: Actel DeskTop Design Tool Set
28183: 00/12/25: rk: Re: Actel DeskTop Design Tool Set
28186: 00/12/26: <blueflyer@my-deja.com>: Newbie question on clock timing generation
28189: 00/12/27: Greg Neff: Re: Newbie question on clock timing generation
28193: 00/12/27: <blueflyer@my-deja.com>: Re: Newbie question on clock timing generation
28194: 00/12/27: Peter Alfke: Re: Newbie question on clock timing generation
28197: 00/12/27: <blueflyer@my-deja.com>: Re: Newbie question on clock timing generation
28231: 01/01/03: Hal Murray: Re: Newbie question on clock timing generation
28234: 01/01/03: <eml@riverside-machines.com.NOSPAM>: Re: Newbie question on clock timing generation
28235: 01/01/03: <eml@riverside-machines.com.NOSPAM>: Re: Newbie question on clock timing generation
28471: 01/01/14: <pineji@my-deja.com>: Re: Newbie question on clock timing generation
28204: 00/12/29: <jaimearanguren@my-deja.com>: MAX+Plus II Output. to HEX
28205: 00/12/29: C.Schlehaus: Re: MAX+Plus II Output. to HEX
28206: 00/12/29: <DSL_Warning@wsomwivfc.edu>: DSL Availability In Your Area? .................... OVr9QUZ4ta3v
28207: 00/12/29: Jila Nazari: selecting tools a newbi question.
28208: 00/12/30: Andreas Doering: FFs in IOBs in XC4000
28233: 01/01/03: Jaan Sirp: Re: FFs in IOBs in XC4000
28209: 00/12/30: AlexSeavision: Money for College
28210: 00/12/30: AlexSeavision: Money for College
28211: 00/12/30: LEULATsM: <!-- To use a different cobrand, make sure you have a template for it in /parts/cobrand/ -->
28212: 00/12/30: Bob Doyle: XC9500 and unused inputs
28213: 00/12/31: Paul Taylor: Re: XC9500 and unused inputs
28222: 01/01/01: Bob Doyle: Re: XC9500 and unused inputs
28227: 01/01/02: Andy Peters: Re: XC9500 and unused inputs
28228: 01/01/02: Paul Taylor: Re: XC9500 and unused inputs
28214: 00/12/31: Alun: Re: XC9500 and unused inputs
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