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Hi! Which one is the best technique for implementing FIR/IIR filters in ASICS/FPGAs ?..CSD or Distributed arithmetic?.. -- --saqib yaqub-- Sent via Deja.com http://www.deja.com/Article: 27926
I am specifying a constraint in the vhdl code as attribute preserve_signal : boolean; attribute max_load : real; ATTRIBUTE preserve_signal OF rxcntrl_state : SIGNAL IS true; ATTRIBUTE max_load OF rxcntrl_state : SIGNAL IS 1.0; Now with this constraint rxcntrl_state(1) has fanout=75 for maxload=1. Is max_load the capacitance value or what. If a state machine flop has such a large fanout then what constraint should I give. Why isn't this constraint working. Is the lut_max_fanout constraint in leonardo spectrum the same as the max_load constraint.Does the lut_max_fanout also control the fanout of a flip-flop. Even after assigning this rxcntrl_state(1) net to a lowskewline in virtexE the overall delay is 5.37ns on the net which kills my speed. Can someone help me,please.Article: 27927
Nial wrote: >Note that the Altera tool set is only $2K and for that you get a version of >Modelsim which isn't limited to any size of design (and is 50% quicker than >Modelsim XE) and FPGA Express or Exemplar Spectrum with Quartus and Maxplus2 >which between them allow any Altera device to be targeted. > >It also _isn't_ time base licensed, after a year you don't get any more >free tool updates or suport but all tools (including third party) will >continue to work and new designs can be started. > The Modelsim and Exemplar licenses *are* time based, at least according to my license file. When I queried our supplier about this, apparantly Mentor wanted it this way. :-( The other licenses are, as you say, just limited in how long you can have updates for - which seems fair. Cheers, Martin -- Martin Thompson BEng(Hons) MIEE TRW Automotive Advanced Product Development, Stratford Road, Solihull, B90 4GW. UK Tel: +44 (0)121-627-3569 mailto:martin.j.thompson@trw.com Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27928
Hi, My name is Ludovic Lemenuel. I'm working at Asymptotes witch is a consultancy firm specialized in Search and Recruiting of Engineers and Managers for Industry. I research a process engineers to work in semiconductor manufacturer based in France. You can contact me at 33 (0)1 69 86 98 98 or send me a CV at : asymptotes@asymptotes.fr And you can send this mail to a friend. Thanks in advance, Ludovic LemenuelArticle: 27929
Hi, My name is Ludovic Lemenuel. I'm working at Asymptotes witch is a consultancy firm specialized in Search and Recruiting of Engineers and Managers for Industry. I research a process engineers to work in semiconductor manufacturer based in France. You can contact me at 33 (0)1 69 86 98 98 or send me a CV at : asymptotes@asymptotes.fr And you can send this mail to a friend. Thanks in advance, Ludovic LemenuelArticle: 27930
I am looking for a VHDL/Verilog sample program of Kalman filters. Anybody can help?Article: 27931
On Fri, 15 Dec 2000 00:57:49 +0100, "Michael Randelzhofer" <mrandelzhofer@uumail.de> wrote: >I remarked a very strange metastable situation at my toilet flush. Pushing >it through, it generates a waterpulse of about 2sec duration, then the water >stops. Everything works fine. >When i hit the flush only half or little, sometimes the water doesn't stop >runnung. The weak never ending waterpulse and it's jitter causes unreliable >cleaning operation. The only way to get the flush out of metastability, is >to hit the flush hard again. > >I hope the newer flush systems operate with faster flipflops, so i can save >a lot of water. Hmmmm. I think we need a VHDL simulation for this. Have you got a VITAL model for your toilet? EvanArticle: 27932
On Thu, 14 Dec 2000 22:42:09 -0800, "Sachin Vaish" <sachinv@bangalore.coreel.com> wrote: >I am specifying a constraint in the vhdl code as > >attribute preserve_signal : boolean; >attribute max_load : real; >ATTRIBUTE preserve_signal OF rxcntrl_state : SIGNAL IS true; >ATTRIBUTE max_load OF rxcntrl_state : SIGNAL IS 1.0; > >Now with this constraint rxcntrl_state(1) has fanout=75 for maxload=1. > >Is max_load the capacitance value or what. > >If a state machine flop has such a large fanout then what constraint should I give. > >Why isn't this constraint working. > >Is the lut_max_fanout constraint in leonardo spectrum the same as the max_load constraint.Does the lut_max_fanout also control the fanout of a flip-flop. > >Even after assigning this rxcntrl_state(1) net to a lowskewline in virtexE the overall delay is 5.37ns on the net which kills my speed. > >Can someone help me,please. I had this conversation over a long period with Spectrum support last year. Unfortunately, I haven't got the emails any more, but this is what I put in my synth script file afterwards: set_attribute -net $module.arst_h -name LUT_MAX_FANOUT -value 10000 This prevented duplication of a net that was previously being duplicated, so it seems to work. I'd also try it without PRESERVE_SIGNAL, since this may be interfering with duplication. EvanArticle: 27933
On Fri, 15 Dec 2000 00:05:46 +0000, Rick Filipkiewicz <rick@algor.co.uk> wrote: >VHDL, by contrast, allows complex derived data types and therefore *needs* >strong type checking [Historical question: Which came first, complex types or >strong typing ?]. Historical musing: C has complex derived data types, but K&R C didn't have strong type checking. The IEEE version added more rigorous checking later. The original C, it could be argued, simply got it wrong. As an aside, it always annoys me to see statements that it's easy to learn Verilog if you know C. There are minor similarities, but very little that'll help you learn Verilog. It could even be argued that an understanding of types will help you learn VHDL. As another gratuitous aside, I'd like to know why people who write forewords to Verilog books always see fit to badmouth VHDL. J. Gordon Bell wrote a breathtaking foreword to Moorby's book, in which he stated that Verilog was better than VHDL because it had been written by one person, and VHDL had been designed by a committee. I hope he was around when an IEEE committee decided to add non-blocking statements to Verilog, changing it from an unusable curiosity into a half-usable language. EvanArticle: 27934
Bassem wrote: > > How about XESS student kit? Any good/bad experience with this kit? I got it with the xs40 board. Think it's nice, small and you can have fun with it. Documentation is good, web page & support also. hope it helps ;-)Article: 27935
Martin, you can use TCL to implement your timing assignments. Altera FAEs and distributors can provide you the so called, free TCL Powerkit. >From the Powerkit documentation: ...It will increase the user's efficiency doing Timing Analysis and improving design performance. These TCL scripts are very simple to use, whereby the user copies and pastes examples, rather than having to truly learn low level TCL syntax. These scripts take advantage of the Tcl interface, and are able to probe into the internal Quartus database and powerfully manipulate a design... With these scripts you can easily build hirarchical groups or build groups that contain all registers driven by certain pins and then apply your multicycle assignments. By doing so you won't have problems with changing names between synthesis runs. - Wolfgang /_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/ El Camino GmbH Your Programmable Logic Design House www.elca.de /_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/_/ Martin Heimlicher <heimlicher@scs.ch> wrote in message news:3a37e399@news.datacomm.ch... > Dear all, > > I have the following situation with a Altera 20K200E FPGA: One external data > bus is running at 25 MHz. Internally, I am using a frequency doubled clock > at 50 MHz to sample these signals. > > How do I specify in the Altera Quartus tool that it can allow two cycles > time for all paths starting at these external data bus pins and going to all > internal registers ? > > I find that multicycle timing constraints can only be applied to individual > register instances and not to the complete design. This is disasterous since > the instance names change from one synthesis run to the next. Is there a > better way ? > > Thanks a lot in advance, > Martin Heimlicher, Supercomputing Systems AG, Switzerland > >Article: 27936
On Thu, 14 Dec 2000 07:45:06 +0200, Assaf Sarfati <assaf@FilesXpress.com> wrote: >I had a similar problem a while back when evaluating Leonardo; it >wouldn't infer a DP RAM, but instead implemented it in a bunch of FFs. I >found that this DP RAM design was inferred correctly (sync wr, async >rd): > >entity sync_embedded_RAM is >generic >( > data_width: integer; > adrs_width: integer >); >port >( > clock: in std_ulogic; > write_en: in std_ulogic; > wr_adrs: in unsigned(adrs_width-1 downto 0); > data_in: in std_ulogic_vector(data_width-1 downto 0); > rd_adrs: in unsigned(adrs_width-1 downto 0); > data_out: out std_ulogic_vector(data_width-1 downto 0) >); >end sync_embedded_RAM; > >architecture synth of sync_embedded_RAM is > > type mem_type is array (2**adrs_width downto 0) of > std_ulogic_vector(data_width - 1 downto >0) ; > signal mem: mem_type ; > >begin > > mem_wr_p: process(clock) > begin > if rising_edge(clock) then > if write_en = '1' then > mem(conv_integer(wr_adrs)) <= data_in; > end if; > end if; > end process; > > mem_rd_p: process(mem, rd_adrs) > begin > data_out <= mem(conv_integer(rd_adrs)); > end process; > >end synth; > > <sniP> This is the exact method i used to get dual port ram to work right. Of course, you put a wrapper around this to have separate counters for the write and read addresses. Ralph Watson Return Email Address is: ralphwat dot home at excite dot com just type the address in like it should look likeArticle: 27937
eml@riverside-machines.com.NOSPAM wrote: > On Fri, 15 Dec 2000 00:57:49 +0100, "Michael Randelzhofer" > <mrandelzhofer@uumail.de> wrote: > > >I remarked a very strange metastable situation at my toilet flush. Pushing > >it through, it generates a waterpulse of about 2sec duration, then the water > >stops. Everything works fine. > >When i hit the flush only half or little, sometimes the water doesn't stop > >runnung. The weak never ending waterpulse and it's jitter causes unreliable > >cleaning operation. The only way to get the flush out of metastability, is > >to hit the flush hard again. > > > >I hope the newer flush systems operate with faster flipflops, so i can save > >a lot of water. > > Hmmmm. I think we need a VHDL simulation for this. Have you got a > VITAL model for your toilet? > > Evan Might need to use Handle-P instead.Article: 27938
eml@riverside-machines.com.NOSPAM wrote: > On Fri, 15 Dec 2000 00:05:46 +0000, Rick Filipkiewicz > <rick@algor.co.uk> wrote: > > >VHDL, by contrast, allows complex derived data types and therefore *needs* > >strong type checking [Historical question: Which came first, complex types or > >strong typing ?]. > > Historical musing: C has complex derived data types, but K&R C didn't > have strong type checking. The IEEE version added more rigorous > checking later. The original C, it could be argued, simply got it > wrong. > Yes & I remember a lot of old-fashioned C hackers moaning about the restrictions imposed when C was ANSI-fied, mainly because it exposed a lot of code that really only worked by the grace of the goddess of programmers. > > As an aside, it always annoys me to see statements that it's easy to > learn Verilog if you know C. There are minor similarities, but very > little that'll help you learn Verilog. It could even be argued that an > understanding of types will help you learn VHDL. > Absolutely. The pernicious confusion here is that C might help you to write Verilog but that's several parsecs from learning/understanding it. > > As another gratuitous aside, I'd like to know why people who write > forewords to Verilog books always see fit to badmouth VHDL. J. Gordon > Bell wrote a breathtaking foreword to Moorby's book, in which he > stated that Verilog was better than VHDL because it had been written > by one person, and VHDL had been designed by a committee. I hope he > was around when an IEEE committee decided to add non-blocking > statements to Verilog, changing it from an unusable curiosity into a > half-usable language. > > Evan Yes, a blot on an otherwise excellent book.Article: 27939
"Jianyong Niu" <cop00jn@shef.ac.uk> wrote: >I am looking for a VHDL/Verilog sample program of Kalman filters. Anybody >can help? > Kalman filters are very system dependent. By definition, the system you are trying to filter is embedded in the filter, therefore you need to tell us what type of data you are trying to filter for us to be able to help you. Muzaffer FPGA DSP Consulting http://www.dspia.comArticle: 27940
On Fri, 15 Dec 2000 00:05:46 +0000, Rick Filipkiewicz <rick@algor.co.uk> wrote: >Its interesting that this width thing is always the difference first mentioned >in this VHDL/Verilog discussion and its actually misleading. Verilog, at least >at the synthesisable level, really only has three data types and no ability for >creating any form of structure. ..... >because of this `width' rules can be defined that are very simple. Very >approximately [see LRM for details]: > >if the lhs is wider than the rhs fill the top bits of the lhs with 0's. > >if the lhs is narrower than the rhs only use the ls bits of the rhs. > >if the rhs is some complex expression then its width is the width of the largest >operand. The problem is that it is easy to connect two different sized busses in Verilog and the problems can be very difficult to detect during testing. For example topmost bit missing etc. I have seen too many problems caused by the fact that Verilog doesn't check the bus widths. The errors are easy to make for example when one big bitvector is built from tens of other busses and one width is defined incorrectly. In VHDL the compiler complains immediatly about bus sizes. Those bugs can take days to find in complex designs. >VHDL, by contrast, allows complex derived data types and therefore *needs* >strong type checking [Historical question: Which came first, complex types or >strong typing ?]. Quite few people actually use the data types in synthesizable code altough it is very wise thing to do. One example is the control bus if it is defined as record the compiler immediatly complains if the bus is connected to wrong place. Bit vectors can be by chance same sized and connected incorrectly. >Because Verilog's types are restricted these sort of issues can mostly be taken >care of by some careful self-discipline or formal coding styles. If necessary >you could invest in one of the `lint' style tools [Anyone know if there's a >shareware or GPL'ed one ?]. Try sometimes running lint tools to Verilog designs. For example I tried one working Verilog design with synopsys synthesis linting rules and I got about 20000 violations. Most of them were caused by Verilog coding style where different sized busses are connected together and the designer expects the topmost bits to be 0 etc. -- ============================================================================= Mr. Kim Enkovaara | kim.enkovaara@iki.fi | Microelectronic Riemannian Iirislahdentie 47 E | IRC: embo | curved-space fault in 02230 Espoo,Finland | | write-only file systemArticle: 27941
Ludovic Lemenuel wrote: > > Hi, > My name is Ludovic Lemenuel. I'm working at Asymptotes witch is a > consultancy firm specialized in Search and Recruiting of Engineers and > Managers for Industry. > I research a process engineers to work in semiconductor manufacturer based > in France. > You can contact me at 33 (0)1 69 86 98 98 or send me a CV at : > asymptotes@asymptotes.fr Wrong newsgroup. Grow a clue. > And you can send this mail to a friend. If I do, that person will no longer be a friend. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 27942
To date I have programmed the Spartan II using the MultiLinx cable in slave-serial mode. We are now cutting over to program it using a microcontroller. Can the .bit file generated by bitgen be fed directly into the chip? I am confused because XAPP 098 "The Low-Cost, Efficient Serial Configuration of Spartan FPGAs" on page 8 says a hex file should be generated and then convert that to binary format. Yet XAPP 138 "Vertex FPGA Series Configuration and Readback" does not make any mention of this consideration. Does the XAPP 098 procedure need to be followed? Finally, I assume all the required CRCs are embedded in the generated bitstream. Is that a correct assumption? Thanks, AndyArticle: 27943
I agree. Tools are developed to alleviate the burden and help catch any mistake (even the most experienced guy makes mistakes and particularly get tired, have blurred eyes...). Expecting people to take care lots things is not a good way. Kim Gunnar Enkovaara wrote: > On Fri, 15 Dec 2000 00:05:46 +0000, Rick Filipkiewicz <rick@algor.co.uk> wrote: > > >Its interesting that this width thing is always the difference first mentioned > >in this VHDL/Verilog discussion and its actually misleading. Verilog, at least > >at the synthesisable level, really only has three data types and no ability for > >creating any form of structure. > ..... > >because of this `width' rules can be defined that are very simple. Very > >approximately [see LRM for details]: > > > >if the lhs is wider than the rhs fill the top bits of the lhs with 0's. > > > >if the lhs is narrower than the rhs only use the ls bits of the rhs. > > > >if the rhs is some complex expression then its width is the width of the largest > >operand. > > The problem is that it is easy to connect two different sized busses > in Verilog and the problems can be very difficult to detect during > testing. For example topmost bit missing etc. I have seen too many > problems caused by the fact that Verilog doesn't check the bus widths. > The errors are easy to make for example when one big bitvector is built > from tens of other busses and one width is defined incorrectly. In > VHDL the compiler complains immediatly about bus sizes. Those bugs can > take days to find in complex designs. > > >VHDL, by contrast, allows complex derived data types and therefore *needs* > >strong type checking [Historical question: Which came first, complex types or > >strong typing ?]. > > Quite few people actually use the data types in synthesizable code > altough it is very wise thing to do. One example is the control bus if > it is defined as record the compiler immediatly complains if the bus is > connected to wrong place. Bit vectors can be by chance same sized and > connected incorrectly. > > >Because Verilog's types are restricted these sort of issues can mostly be taken > >care of by some careful self-discipline or formal coding styles. If necessary > >you could invest in one of the `lint' style tools [Anyone know if there's a > >shareware or GPL'ed one ?]. > > Try sometimes running lint tools to Verilog designs. For example I > tried one working Verilog design with synopsys synthesis linting rules > and I got about 20000 violations. Most of them were caused by Verilog > coding style where different sized busses are connected together and > the designer expects the topmost bits to be 0 etc. > > -- > ============================================================================= > Mr. Kim Enkovaara | kim.enkovaara@iki.fi | Microelectronic Riemannian > Iirislahdentie 47 E | IRC: embo | curved-space fault in > 02230 Espoo,Finland | | write-only file systemArticle: 27944
Hello Everybody, I have some questions regarding external setup & hold time considerations. (1) I am just reading the chapter of Xilinx' Development System Reference Guide dealing with their TRACE tool . There I found the following definitions of setup and hold times, respectively: (page 14-21) The external setup time is defined as the setup time of the DATAPAD within an IOB relative to CLKPAD within CLKIOB. (page 14-22) The external hold time is defined as the hold time of the DATAPAD within IOB relative to the CLKPAD within CLKIOB. The external setup and hold times are therefore given in reference to the chip border, i.e. in reference to the input pads. It is not meant in the definitions above that setup and hold times exclusively exist for FFs within IOBs, i.e. only for input FFs, does it? Moreover, setup and hold times exist for buried FFs, i.e. non-input FFs, too. The actual amount of external setup and hold times is influenced by the placement of the FF (routing delays, internal clock skew) and propagation delays through combinatoric logic to the FF's data input. Am I completely wrong up to this point? (2) Now, I have the following scenario: I have an upstream device that is connected to an FPGA. The spec of the upstream device states for an output signal, say A, a minimum and maximum propagation delay in respect to the system clock edge tPDmin = 2 ns and tPDmax = 20 ns. Signal A is an input into the FPGA. For Place&Route I have given a constraint for the PERIOD, namely 40 ns, 50 % duty cycle. Furthermore, I gave a constraint for signal A : NET A OFFSET = IN 20 ns AFTER clk in order to meet tPDmax, which must be taken into account for the setup time of FFs. The datasheet report generated after Place&Route shows that the setup time is met. But a hold time of about 4 ns shows up in the report. This hold time is a problem as far as I understand. Due to the worst case of tPDmin the data on signal A is changed by the upstream device already 2 ns after the clock edge. So it is important that Place&Route keeps the hold time below tPDmin. So, if my train of thought is right, how can I persuade Place&Route to keep the relation tHOLD < tPDmin in mind? Is there any constraint construction for this purpose? I would be glad to have any serious comment to the stated issue. Thanks in advance, sincerely GuidoArticle: 27945
Kim Gunnar Enkovaara wrote: > On Fri, 15 Dec 2000 00:05:46 +0000, Rick Filipkiewicz <rick@algor.co.uk> Try > sometimes running lint tools to Verilog designs. For example I > tried one working Verilog design with synopsys synthesis linting rules > and I got about 20000 violations. Most of them were caused by Verilog > coding style where different sized busses are connected together and > the designer expects the topmost bits to be 0 etc. > > -- The millions of warnings stuff will be familiar to anyone who's used a PCB design systems DRC checkers which insist on complaining about all unconnected pins, or 200 warnings caused by placing a component under the EPROM socket, or ... Usually takes about 20 min to write a rough&ready bit of perl to reduce the warnings by 2 orders of magnitude. Then you pipe that through some flavour of diff to compare it with the previous set, stick everything in makefile, ... There's actually a serious point here. Verilog is a much more exposed language and doesn't presume to try to stop you making a fool of yourself. Coding styles, lint, formal verification and so forth are thing the user defines or imposes his/her self. Set your paranoia level according to taste. In this sense its like C. I suspect that those, like myself, who can live with or even appreciate this `caveat emptor' philosophy will tend to go for Verilog.Article: 27946
Dear all, Does anyone know how to make/steps conversion from FPGA gate-level netlist to ASIC gate-level netlist ? I'm currently triying convert Xilinx FPGA to ASIC's CMOS Technology by using Synopsys Design Compiler. But, some instance was unresolved references such OBUF , DFF ( flip- flop )!! Could anyone share your experiences with me ? Thanks. Sent via Deja.com http://www.deja.com/Article: 27947
On Sat, 16 Dec 2000 03:21:15 GMT, hchenry@comsoc.com wrote: >Dear all, > >Does anyone know how to make/steps conversion from FPGA gate-level >netlist to ASIC gate-level netlist ? > >I'm currently triying convert Xilinx FPGA to ASIC's CMOS Technology by >using Synopsys Design Compiler. >But, some instance was unresolved references such OBUF , DFF ( flip- >flop )!! >Could anyone share your experiences with me ? First of let me ask you why you are trying to convert the gate level netlist. It would be much easier to convert the RTL. Assuming that you really want to do the gate level conversion, you have to make models of all the cells in the netlist. Put them in a library file and include it in your synthesis script. It can be a tedious and error prone process. Muzaffer FPGA DSP Consulting http://www.dspia.comArticle: 27948
Hi, Kim Gunnar Enkovaara wrote: > > On Fri, 15 Dec 2000 00:05:46 +0000, Rick Filipkiewicz <rick@algor.co.uk> wrote: > Quite few people actually use the data types in synthesizable code > altough it is very wise thing to do. One example is the control bus if > it is defined as record the compiler immediatly complains if the bus is > connected to wrong place. Bit vectors can be by chance same sized and > connected incorrectly. > That's an interesting approach. Do you mean to say that use records for control bus ? I am not sure whether low end synthesis tools (don't have a list..) support records. But I would be very much interested in seeing a tiny example - if that doesn't burden you too much :-) > > Try sometimes running lint tools to Verilog designs. For example I > tried one working Verilog design with synopsys synthesis linting rules > and I got about 20000 violations. Most of them were caused by Verilog > coding style where different sized busses are connected together and > the designer expects the topmost bits to be 0 etc. > Well I don't know the tool that you talk about. But IMHO a *GOOD* lint tool MUST be 1.> "configurable" i.e. the user should be able to specify *with ease* new rules 2.> It should be possible to turn the checks ON & OFF with ease On top of these you could use PERL etc. to filter out unwanted stuff. With the above qualities I think a lint tool can be of GREAT help to the design community (especially Verilog). Now if you ask me if I have ever seen such a linter, the answer is YES! I have evaluated LEDA's ProVHDL (Now LEDA is part of Synopsys..) they also have a Verilog version, ProVerilog. Regards, Srini -- Srinivasan Venkataramanan (Srini) ASIC Design Engineer, Chennai (Madras), IndiaArticle: 27949
On Sat, 16 Dec 2000 13:28:07 +0530, Srinivasan Venkataramanan wrote: >Hi, > > > That's an interesting approach. Do you mean to say that use records >for control bus ? I am not sure whether low end synthesis tools (don't >have a list..) support records. But I would be very much interested in >seeing a tiny example - if that doesn't burden you too much :-) For example digital clock is good example. All the numbers can be defined independently in a record and that record can be used in the data bus definition. I think it's easier to say bus.sec than bus[10:15]. The code is much easier to read when the names are used. I got the idea of using records from one VHDL course where the trainer was very experienced VHDL coder and synthesis tool trainer, Those records even synthesized very well. The tools I tried were Synplify Pro 6.0 (or 6.1 but that doesn't matter) and Synopsys Design Compiler so the tools were not low end. I get my net connection up in few days, after that I can give some examples if you want. I have been quite impressed about Synplify also in other codes. It really creates better results than Leonardo or Synopsys FPGA Compiler and it creates the results much faster. The one good thing about leonardo is that it sometimes creates smaller designs and that matters if the chip is 99% full. > Well I don't know the tool that you talk about. But IMHO a *GOOD* >lint tool MUST be > >1.> "configurable" i.e. the user should be able to specify *with ease* >new rules >2.> It should be possible to turn the checks ON & OFF with ease I tried TransEDA VNCheck. I think the tool was excellent and I customized the rules but the Verilog coding style was still the problem. It's difficult for the tool to guess what the designer was thinking when he/she coded something weird. >With the above qualities I think a lint tool can be of GREAT help to >the design community (especially Verilog). I think that without good lint tools coding Verilog is quite difficult. The lint tools do what VHDL compiler does during the compilation. Human errors are just too easy to make, even the best coder can make error at some point. -- ============================================================================= Mr. Kim Enkovaara | kim.enkovaara@iki.fi | Microelectronic Riemannian Iirislahdentie 47 E | IRC: embo | curved-space fault in 02230 Espoo,Finland | | write-only file system
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