Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015Jan2015

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Threads Starting Nov 2000

26850: 00/11/01: ChenSongWei: Reference Design Xapp205.zip
26854: 00/11/01: Ivan Leung: JBits
    26855: 00/11/01: Phil James-Roxby: Re: JBits
    26857: 00/11/01: Nicholas Weaver: Re: JBits
    26863: 00/11/01: Steven Guccione: Re: JBits
26862: 00/11/01: <autumn@osearch.com>: Hardware Engineer position in Pittsburgh
    26869: 00/11/01: S. Ramirez: Re: Hardware Engineer position in Pittsburgh
26872: 00/11/02: Jean-Paul GOGLIO: Bits swapping with XC18V02
26875: 00/11/02: ajd: cryptography/Block ciphers
    26886: 00/11/02: Nicholas Weaver: Re: cryptography/Block ciphers
        26917: 00/11/03: Eric LaForest: Re: cryptography/Block ciphers
    26913: 00/11/03: Michael Strothjohann: Re: cryptography/Block ciphers
        26914: 00/11/03: ajd: Re: cryptography/Block ciphers
    26976: 00/11/06: mozimo: Re: cryptography/Block ciphers
    26977: 00/11/06: mozimo: Re: cryptography/Block ciphers
    26978: 00/11/06: mozimo: Re: cryptography/Block ciphers
26876: 00/11/02: chsw: Block Ram
    26884: 00/11/02: Mujtaba Hamid: Re: Block Ram
26878: 00/11/02: Dan: Pwer supply for a XCV300. Recommendations please.
    26879: 00/11/02: Gunnar Tufte: Re: Pwer supply for a XCV300. Recommendations please.
        26894: 00/11/02: David Forbes: Re: Pwer supply for a XCV300. Recommendations please.
26880: 00/11/02: Peter Dennett: ISO C -> VHDL translator, prefer open source
    26985: 00/11/06: Peter Dennett: Re: ISO C -> VHDL translator, prefer open source
        26992: 00/11/06: Luke Scharf: Re: ISO C -> VHDL translator, prefer open source
        26996: 00/11/07: Jan Gray: Re: ISO C -> VHDL translator, prefer open source
            27014: 00/11/07: Maya: Re: ISO C -> VHDL translator, prefer open source
                27021: 00/11/07: Peter Dennett: Re: ISO C -> VHDL translator, prefer open source
    27001: 00/11/07: Jan Guffens: Re: ISO C -> VHDL translator, prefer open source
    27062: 00/11/09: <timjeno@my-deja.com>: Re: ISO C -> VHDL translator, prefer open source
        27090: 00/11/10: Peter Dennett: Re: ISO C -> VHDL translator, prefer open source
            27161: 00/11/13: <timjeno@my-deja.com>: Re: ISO C -> VHDL translator, prefer open source
26881: 00/11/02: James S.: OT: Xilinx T-Shirt
    26882: 00/11/02: Andy Peters: Re: OT: Xilinx T-Shirt
        26887: 00/11/02: fred: Re: OT: Xilinx T-Shirt
            26901: 00/11/02: Andy Peters: Re: OT: Xilinx T-Shirt
    26883: 00/11/02: Rainer Buchty: Re: OT: Xilinx T-Shirt
        26905: 00/11/03: Rick Filipkiewicz: Re: OT: Xilinx T-Shirt
    26890: 00/11/02: Greg Neff: Re: OT: Xilinx T-Shirt
    26895: 00/11/02: <eml@riverside-machines.com.NOSPAM>: Re: OT: Xilinx T-Shirt
        26896: 00/11/02: Eric Smith: Re: OT: Xilinx T-Shirt
        26902: 00/11/02: Andy Peters: Re: OT: Xilinx T-Shirt
            26910: 00/11/03: <eml@riverside-machines.com.NOSPAM>: Re: OT: Xilinx T-Shirt
        26907: 00/11/03: Bob Perlman: Re: OT: Xilinx T-Shirt
    26897: 00/11/02: Jerry English: Re: OT: Xilinx T-Shirt
    26898: 00/11/02: Richard Chidester: Re: OT: Xilinx T-Shirt
        26900: 00/11/02: Phil James-Roxby: Re: OT: Xilinx T-Shirt
        26906: 00/11/03: Ray Andraka: Re: OT: Xilinx T-Shirt
        26931: 00/11/03: Richard Dungan: Re: OT: Xilinx T-Shirt
            26933: 00/11/03: Richard Chidester: Re: OT: Xilinx T-Shirt
        26938: 00/11/03: Andy Peters: Re: OT: Xilinx T-Shirt
    26899: 00/11/02: S. Ramirez: Re: Xilinx T-Shirt
26885: 00/11/02: Dan: Need a PCB speaker driven by XCV100
    26893: 00/11/02: Peter Alfke: Re: Need a PCB speaker driven by XCV100
    26903: 00/11/02: Ray Andraka: Re: Need a PCB speaker driven by XCV100
    26908: 00/11/02: Phil Hays: Re: Need a PCB speaker driven by XCV100
    26909: 00/11/03: Olaf Birkeland: Re: Need a PCB speaker driven by XCV100
    26923: 00/11/03: Dan: Thanks to all for great input EOM
    26928: 00/11/03: Eric Montreal: Re: Need a PCB speaker driven by XCV100
26888: 00/11/02: Nicolas Matringe: clock multiplication and Spartan2 DLL placement constraints
    26889: 00/11/02: Steven Derrien: Re: clock multiplication and Spartan2 DLL placement constraints
        26891: 00/11/02: Nicolas Matringe: Re: clock multiplication and Spartan2 DLL placement constraints
        26892: 00/11/02: Nicolas Matringe: Re: clock multiplication and Spartan2 DLL placement constraints
        26911: 00/11/03: Nicolas Matringe: Re: clock multiplication and Spartan2 DLL placement constraints
26912: 00/11/03: Gerard: New (worse!) timing parameters in Quartus 2000.09 for APEX devices
    26922: 00/11/03: Marc: Re: New (worse!) timing parameters in Quartus 2000.09 for APEX devices
26918: 00/11/03: Martin Thompson: ACEX1K vs FLEX10K
    26937: 00/11/03: Ashok Chotai: Re: ACEX1K vs FLEX10K
        26947: 00/11/04: Carlhermann Schlehaus: Re: ACEX1K vs FLEX10K
            27554: 00/11/28: Nick Bruty: Re: ACEX1K vs FLEX10K
                27578: 00/11/29: C.Schlehaus: Re: ACEX1K vs FLEX10K
    26948: 00/11/04: Steve Rencontre: Re: ACEX1K vs FLEX10K
        27007: 00/11/07: <timjeno@my-deja.com>: Re: ACEX1K vs FLEX10K
    26955: 00/11/05: S. Ramirez: Re: ACEX1K vs FLEX10K
        26956: 00/11/05: Carlhermann Schlehaus: Re: ACEX1K vs FLEX10K
            26961: 00/11/05: S. Ramirez: Re: ACEX1K vs FLEX10K
        26960: 00/11/05: Steve Rencontre: Re: ACEX1K vs FLEX10K
26919: 00/11/03: Bruce Oakley: High Slice Usage in Virtex-E
    26921: 00/11/03: <eml@riverside-machines.com.NOSPAM>: Re: High Slice Usage in Virtex-E
26924: 00/11/03: Dan: I2C bus driven by Xilinx
    26926: 00/11/03: Mike H.: Re: I2C bus driven by Xilinx
        26944: 00/11/03: John L. Smith: I2C Recieved by Xilinx, was Re: I2C bus driven by Xilinx
26927: 00/11/03: Michael Barr: ANNOUNCE: Memory Test Code/Article
    26930: 00/11/03: robert bristow-johnson: Re: ANNOUNCE: Memory Test Code/Article
26932: 00/11/03: Stuart J Adams: level shifting buffers ??
    26936: 00/11/04: Zoltan Kocsi: Re: level shifting buffers ??
    26995: 00/11/07: Austin Franklin: Re: level shifting buffers ??
26935: 00/11/04: eng: Crosspoint switch in CPLD/FPGA ??
    26990: 00/11/07: Mikeandmax: Re: Crosspoint switch in CPLD/FPGA ??
26946: 00/11/04: Simon Gornall: Spartan2 prototype boards
    26952: 00/11/04: Berni Joss: Re: Spartan2 prototype boards
        26962: 00/11/05: Simon Gornall: Re: Spartan2 prototype boards
    26953: 00/11/05: Rick Filipkiewicz: Re: Spartan2 prototype boards
    26963: 00/11/06: Anthony C: Re: Spartan2 prototype boards
    26967: 00/11/06: Harjo Otten: Re: Spartan2 prototype boards
    26968: 00/11/06: <gazit@my-deja.com>: Re: Spartan2 prototype boards
26964: 00/11/05: Tobin Fricke: ViewLogic ViewDraw questions
    26965: 00/11/06: Dan: Re: ViewLogic ViewDraw questions
        26993: 00/11/07: Austin Franklin: Re: ViewLogic ViewDraw questions
            26997: 00/11/07: Greg Neff: Re: ViewLogic ViewDraw questions
                27031: 00/11/08: Austin Franklin: Re: ViewLogic ViewDraw questions
    27002: 00/11/07: Julian Cox: Re: ViewLogic ViewDraw questions
    27107: 00/11/10: Philip Freidin: Re: ViewLogic ViewDraw questions
    27222: 00/11/16: napier_surf: Re: ViewLogic ViewDraw questions
26970: 00/11/06: Michal Prokes: Encoding of FSMs internal states
    26989: 00/11/07: <yuryws@my-deja.com>: Re: Encoding of FSMs internal states
        27032: 00/11/08: Michal Prokes: Re: Encoding of FSMs internal states
            27050: 00/11/08: Pak K. Chan: Re: Encoding of FSMs internal states
26971: 00/11/06: George Pontis: Need help locking pins for Spartan XL
    26973: 00/11/06: Rascal: Re: Need help locking pins for Spartan XL
    26988: 00/11/07: <yuryws@my-deja.com>: Re: Need help locking pins for Spartan XL
    27005: 00/11/07: Ray Andraka: Re: Need help locking pins for Spartan XL
        27006: 00/11/07: George Pontis: Re: Need help locking pins for Spartan XL
            27010: 00/11/07: Dan: Re: Need help locking pins for Spartan XL
                27243: 00/11/16: Qian Zhang: Re: Need help locking pins for Spartan XL
                    27247: 00/11/16: Ray Andraka: Re: Need help locking pins for Spartan XL
26972: 00/11/06: <alexboyer@my-deja.com>: FPGA programming through XC18V00 eeprom
    26974: 00/11/06: Etienne Racine: Re: FPGA programming through XC18V00 eeprom
        26981: 00/11/06: <alexboyer@my-deja.com>: Re: FPGA programming through XC18V00 eeprom
            26983: 00/11/06: Etienne Racine: Re: FPGA programming through XC18V00 eeprom
                26984: 00/11/06: Dave Vanden Bout: Re: FPGA programming through XC18V00 eeprom
26975: 00/11/06: Hawker: Quick Foundation SPIV install question
    26980: 00/11/06: Curtis Fischaber: Re: Quick Foundation SPIV install question
26982: 00/11/06: <widding@birger.com>: Synario License
26986: 00/11/06: <p25486@my-deja.com>: Coregen instantiation help!!
    26998: 00/11/07: <felix_bertram@my-deja.com>: Re: Coregen instantiation help!!
26994: 00/11/07: Karl Olsen: Spartan2 macros in WebPACK
    27012: 00/11/07: Tim Jaynes: Re: Spartan2 macros in WebPACK
        27029: 00/11/07: Eric Smith: Re: Spartan2 macros in WebPACK
            27046: 00/11/08: Karl Olsen: Re: Spartan2 macros in WebPACK
            27075: 00/11/09: Tim Jaynes: Re: Spartan2 macros in WebPACK
    27068: 00/11/09: Vikram Pasham: Re: Spartan2 macros in WebPACK
26999: 00/11/07: Rainer Becker: Flex10KA RAM Inferencing with Synplify 5.1.5a
    27004: 00/11/07: S. Ramirez: Re: Flex10KA RAM Inferencing with Synplify 5.1.5a
27000: 00/11/07: Rainer Becker: Flex10KA RAM Inferencing with Synplify 5.1.5
27003: 00/11/07: Stefaan Vanheesbeke: unique serial nr
    27015: 00/11/07: Muzaffer Kal: Re: unique serial nr
    27022: 00/11/08: Hal Murray: Re: unique serial nr
        27036: 00/11/08: Gary Watson: Re: unique serial nr
            27070: 00/11/09: Steve Rencontre: Re: unique serial nr
            27083: 00/11/10: Gary Watson: Re: unique serial nr
27008: 00/11/07: Dirk Galda: FFT LogiCore
    27013: 00/11/07: Tim Jaynes: Re: FFT LogiCore
    27103: 00/11/10: Vikram Pasham: Re: FFT LogiCore
27009: 00/11/07: Gary Watson: Embed serial number in a FPGA?
27011: 00/11/07: Michael Barr: ANNOUNCE: New article about Network Processors
    27016: 00/11/07: Gary Watson: Re: ANNOUNCE: New article about Network Processors
    27019: 00/11/07: Jerry Avins: Re: ANNOUNCE: New article about Network Processors
        27026: 00/11/08: Michael Barr: Re: ANNOUNCE: New article about Network Processors
27018: 00/11/07: Jeremy Cooke: Architecture/environment suggestions
    27020: 00/11/07: Mark Sasten: Re: Architecture/environment suggestions
27023: 00/11/08: Frank Z.F Xie: Anything wrong with Xilinx website?
    27033: 00/11/08: Jean-Marie Bussat: Re: Anything wrong with Xilinx website?
    27034: 00/11/08: Mike H.: Re: Anything wrong with Xilinx website?
    27035: 00/11/08: Dirk Galda: Re: Anything wrong with Xilinx website?
    27114: 00/11/11: Robert Sturm: Re: Anything wrong with Xilinx website?
        27172: 00/11/13: Andy Peters: Re: Anything wrong with Xilinx website?
27024: 00/11/07: Qian Zhang: 'event synthesis question
    27027: 00/11/08: Muzaffer Kal: Re: 'event synthesis question
        27030: 00/11/07: Qian Zhang: Re: 'event synthesis question
    27045: 00/11/08: Steve Rencontre: Re: 'event synthesis question
        27056: 00/11/08: Qian Zhang: Re: 'event synthesis question
27028: 00/11/08: Anshuman Sharma: PLL vs DLL
    27042: 00/11/08: Austin Lesea: Re: PLL vs DLL
        27044: 00/11/08: <erika_uk@my-deja.com>: Re: PLL vs DLL
            27053: 00/11/08: Austin Lesea: Re: PLL vs DLL
        27047: 00/11/08: Muzaffer Kal: Re: PLL vs DLL
    27120: 00/11/11: Steve Fair: Re: PLL vs DLL
        27124: 00/11/11: Peter Alfke: Re: PLL vs DLL
            27134: 00/11/12: Steve Fair: Re: PLL vs DLL
                27168: 00/11/13: Peter Alfke: Re: PLL vs DLL
        27263: 00/11/16: J.Niu: can FPGA perform float point calculaton?
            27269: 00/11/16: Jan Gray: Re: can FPGA perform float point calculaton?
            27277: 00/11/16: Eric Smith: Re: can FPGA perform float point calculaton?
    27557: 00/11/28: Nick Bruty: Re: PLL vs DLL
        27561: 00/11/28: Austin Lesea: Re: PLL vs DLL
            27589: 00/11/29: Javier SERRANO: Re: PLL vs DLL
                27594: 00/11/29: Austin Lesea: Re: PLL vs DLL
27037: 00/11/08: Roland Manders: renoir, acex + dpram
    27052: 00/11/08: Georg Berliner: Re: renoir, acex + dpram
27038: 00/11/08: Alex Sherstuk: Boundary Scan fundamentals
    27040: 00/11/08: <dave_bernard@my-deja.com>: Re: Boundary Scan fundamentals
    27043: 00/11/08: Brian Philofsky: Re: Boundary Scan fundamentals
27039: 00/11/08: Wojciech Madejski: WebPack problem
27041: 00/11/08: prc: Global buffers in xc40000xla
    27049: 00/11/08: Andy Peters: Re: Global buffers in xc40000xla
        27059: 00/11/09: prc: Re: Global buffers in xc40000xla
27048: 00/11/08: Simon Bilodeau: problem with XC95288 with PC-104
    27060: 00/11/09: Klaus Falser: Re: problem with XC95288 with PC-104
27051: 00/11/08: Recruit Express: Off subject-WIRELESS H/W S/W - pre IPO - San Jose
27054: 00/11/08: Jon Young: WebPack Problem
27055: 00/11/08: Hal Murray: Linux/Unix code to drive Xilinx download cable
    27079: 00/11/10: Adam Hawes: Re: Linux/Unix code to drive Xilinx download cable
27057: 00/11/08: chsw: Reference Design Xapp205.zip
27058: 00/11/08: <johnb@teachers.org>: WTB: old Digital DEC PDP-8 computer or software
27061: 00/11/09: Georg Heinrich: Expirience with FPSLIC
    27064: 00/11/09: Jan Gray: FPSLIC
27063: 00/11/09: S. Ramirez: Microprocessor Verilog/VHDL Models
    27066: 00/11/09: Andy Peters: Re: Microprocessor Verilog/VHDL Models
        27071: 00/11/09: S. Ramirez: Re: Microprocessor Verilog/VHDL Models
            27078: 00/11/09: Jeremy Cooke: Re: Microprocessor Verilog/VHDL Models
                27097: 00/11/10: Andy Peters: Re: Microprocessor Verilog/VHDL Models
                    27098: 00/11/10: S. Ramirez: Re: Microprocessor Verilog/VHDL Models
27065: 00/11/10: Kang Liat Chuan: Configuring Xilinx FPGA using PIC16F84
    27110: 00/11/11: John Janusson: Re: Configuring Xilinx FPGA using PIC16F84
        27125: 00/11/11: Richard Erlacher: Re: Configuring Xilinx FPGA using PIC16F84
        27126: 00/11/11: Richard Erlacher: Re: Configuring Xilinx FPGA using PIC16F84
    27115: 00/11/11: Berni Joss: Re: Configuring Xilinx FPGA using PIC16F84
27067: 00/11/09: Andrea Sorio: Xilinx PCI Core
    27072: 00/11/09: Mike Treseler: Re: Xilinx PCI Core
    27089: 00/11/10: Newsbrowser: Re: Xilinx PCI Core
        27092: 00/11/10: Andrea Sorio: Re: Xilinx PCI Core
27069: 00/11/09: Steven Derrien: Non routable design
    27073: 00/11/09: Walter Haas: Re: Non routable design
    27076: 00/11/09: Tim Jaynes: Re: Non routable design
        27080: 00/11/10: fred: Re: Non routable design
            27081: 00/11/10: S. Ramirez: Re: Non routable design
            27093: 00/11/10: Tim Jaynes: Re: Non routable design
                27146: 00/11/13: fred: Re: Non routable design
            27101: 00/11/10: Mujtaba Hamid: Re: Non routable design
                27108: 00/11/11: Ray Andraka: Re: Non routable design
                    27116: 00/11/11: Steven Derrien: Re: Non routable design
    27077: 00/11/09: Ray Andraka: Re: Non routable design
        27084: 00/11/10: Steven Derrien: Re: Non routable design
            27086: 00/11/10: Ray Andraka: Re: Non routable design
                27088: 00/11/10: Steven Derrien: Re: Non routable design
                    27091: 00/11/10: Ray Andraka: Re: Non routable design
27074: 00/11/09: Lawrence Peregrim: ChipScope
    27131: 00/11/12: Mark Harvey: Re: ChipScope
27082: 00/11/10: Harry: VHDL: FFS in IOBs
    27095: 00/11/10: Tim Jaynes: Re: VHDL: FFS in IOBs
    27102: 00/11/10: Vikram Pasham: Re: VHDL: FFS in IOBs
27085: 00/11/10: <flavioas@my-deja.com>: Leonardo for Altera
    27100: 00/11/10: Steve Rencontre: Re: Leonardo for Altera
    27106: 00/11/10: Mike Treseler: Re: Leonardo for Altera
    27109: 00/11/11: Georg Berliner: Re: Leonardo for Altera
        27186: 00/11/14: <flavioas@my-deja.com>: Re: Leonardo for Altera
            27189: 00/11/14: <cadmanager@my-deja.com>: Re: Leonardo for Altera
            27208: 00/11/15: <cadmanager@my-deja.com>: Re: Leonardo for Altera
27087: 00/11/10: Jonas: Pull-up
    27096: 00/11/10: Andy Peters: Re: Pull-up
        27099: 00/11/10: Ray Andraka: Re: Pull-up
            27155: 00/11/13: Jonas: Re: Pull-up
            27170: 00/11/13: Andy Peters: Re: Pull-up
            27180: 00/11/13: Jonas: Re: Pull-up
            28165: 00/12/23: rk: Re: Pull-up
27104: 00/11/10: Jamie Sanderson: Virtex 32x1 RAM - Prevent usage
    27105: 00/11/10: Ray Andraka: Re: Virtex 32x1 RAM - Prevent usage
27111: 00/11/10: rickman: CRC, LFSR and scramblers
    27122: 00/11/11: Mohammed Ishaq: Re: CRC, LFSR and scramblers
        27123: 00/11/11: rickman: Re: CRC, LFSR and scramblers
            27127: 00/11/11: Peter Alfke: Re: CRC, LFSR and scramblers
                27128: 00/11/11: rickman: Re: CRC, LFSR and scramblers
                    27129: 00/11/12: Ray Andraka: Re: CRC, LFSR and scramblers
                        27133: 00/11/12: rickman: Re: CRC, LFSR and scramblers
                            27135: 00/11/12: Mohammed Ishaq: Re: CRC, LFSR and scramblers
                            27199: 00/11/14: John L. Smith: Re: CRC, LFSR and scramblers
                                27211: 00/11/15: Peter Alfke: Re: CRC, LFSR and scramblers
                                27370: 00/11/20: Hal Murray: Re: CRC, LFSR and scramblers
                    27136: 00/11/12: Scott Hauck: Re: CRC, LFSR and scramblers
                        27182: 00/11/14: Hal Murray: Re: CRC, LFSR and scramblers
                        27201: 00/11/14: rickman: Re: CRC, LFSR and scramblers
    27176: 00/11/14: <iglasner@zumanetworks.com>: Re: CRC, LFSR and scramblers
    27190: 00/11/14: Catalin: Re: CRC, LFSR and scramblers
27112: 00/11/11: Saqib: Number Format in DSP implementations
    27118: 00/11/11: Ray Andraka: Re: Number Format in DSP implementations
27113: 00/11/11: <jaypt123@my-deja.com>: Webpack 3.2WP3.x from Xilinx is useless
    27153: 00/11/13: Damir Danijel Zagar: Re: Webpack 3.2WP3.x from Xilinx is useless
    27169: 00/11/13: Tim Jaynes: Re: Webpack 3.2WP3.x from Xilinx is useless
        27195: 00/11/15: Rick Filipkiewicz: Re: Webpack 3.2WP3.x from Xilinx is useless
            27206: 00/11/15: Nicolas Matringe: Re: Webpack 3.2WP3.x from Xilinx is useless
27130: 00/11/12: ZEYNEP14: Easy money for the Holidays!
27132: 00/11/12: Hul Tytus: manchester decoder
    27137: 00/11/12: Hal Murray: Re: manchester decoder
        27339: 00/11/19: Cameron Watt: Re: manchester decoder
    27151: 00/11/13: Eduardo Augusto Bezerra: Re: manchester decoder
27138: 00/11/12: Frank Van de Sande: Leon processor core
    27178: 00/11/13: David Foulds: Re: Leon processor core
27139: 00/11/12: WOSTER145: HOW TO TURN $6 INTO $6,000!!!!!!
    27143: 00/11/12: John Larkin: Re: HOW TO TURN $6 INTO $6,000!!!!!!
27140: 00/11/12: Jan Gray: Virtex circuit tricks -- add/mux in one LUT per bit
    27366: 00/11/20: Ray Andraka: Re: Virtex circuit tricks -- add/mux in one LUT per bit
27141: 00/11/13: <haydenso@my-deja.com>: Spartan-II with 5V ISA bus
    27147: 00/11/13: Harjo Otten: Re: Spartan-II with 5V ISA bus
    27148: 00/11/13: fred: Re: Spartan-II with 5V ISA bus
    27149: 00/11/13: Eric Smith: Re: Spartan-II with 5V ISA bus
        27166: 00/11/13: Geoffrey G. Rochat: Re: Spartan-II with 5V ISA bus
            27174: 00/11/13: Eric Smith: Re: Spartan-II with 5V ISA bus
                27253: 00/11/16: Geoffrey G. Rochat: Re: Spartan-II with 5V ISA bus
    27179: 00/11/14: <haydenso@my-deja.com>: Re: Spartan-II with 5V ISA bus
27142: 00/11/12: Nick: OT but important
27144: 00/11/13: V Ram: Config device for Altera 10K10
    27185: 00/11/14: Dmitry Kuznetsov: Re: Config device for Altera 10K10
27145: 00/11/13: Wisut Hantanong: Please guide newbies to real PLD ?
    27194: 00/11/15: Tom: Re: Please guide newbies to real PLD ?
27150: 00/11/13: Richard Meester: LUT and EDIF
    27152: 00/11/13: Steven Derrien: Re: LUT and EDIF
    27162: 00/11/13: Phil James-Roxby: Re: LUT and EDIF
        27183: 00/11/14: Richard Meester: Re: LUT and EDIF
            27191: 00/11/14: Phil James-Roxby: Re: LUT and EDIF
            27367: 00/11/20: Ray Andraka: Re: LUT and EDIF
27156: 00/11/13: Peter Lang: XC4000 maps better than Spartan2
    27159: 00/11/13: Ray Andraka: Re: XC4000 maps better than Spartan2
    27163: 00/11/13: Phil James-Roxby: Re: XC4000 maps better than Spartan2
    27167: 00/11/13: Jan Gray: Re: XC4000 maps better than Spartan2
        27175: 00/11/13: Ray Andraka: Re: XC4000 maps better than Spartan2
27157: 00/11/13: qfwfq: applet for drawing sorting networks
27158: 00/11/13: Steven Derrien: Synopsys VSS and XilinxCorelib weirdness
    27177: 00/11/14: Addie Tang: Re: Synopsys VSS and XilinxCorelib weirdness
    27184: 00/11/14: Steven Derrien: Re: Synopsys VSS and XilinxCorelib weirdness
27160: 00/11/13: Nicolas Matringe: Xilinx WebPack dll problem
27164: 00/11/13: <madisonfff@usa.net>: Clear AND Preset Pins
    27171: 00/11/13: Andy Peters: Re: Clear AND Preset Pins
        27196: 00/11/14: Qian Zhang: Re: Clear AND Preset Pins
            27203: 00/11/15: Muzaffer Kal: Re: Clear AND Preset Pins
27165: 00/11/13: <qianz@my-deja.com>: How to read schematic after synthesis
    27187: 00/11/14: Chris Mc Clements: Re: How to read schematic after synthesis
        27197: 00/11/14: Qian Zhang: Re: How to read schematic after synthesis
27173: 00/11/13: Dan Alley: Conversion of Altera POF file for a new config device
    27294: 00/11/17: <cadmanager@my-deja.com>: Re: Conversion of Altera POF file for a new config device
27181: 00/11/13: Brad Pollard: FPGA designers in the Bay Area (San Jose) - Need a new start?
27188: 00/11/14: Mark Mahoney: Job posting info
    27200: 00/11/15: <husby@my-deja.com>: Re: Job posting info
        27212: 00/11/15: Jan Gray: Re: Job posting info
            27216: 00/11/15: Hal Murray: Re: Job posting info
27192: 00/11/14: <erika_uk@my-deja.com>: reset pulse ?
    27193: 00/11/14: <erika_uk@my-deja.com>: Re: reset pulse ?
        27292: 00/11/17: <erika_uk@my-deja.com>: Re: reset pulse ?
            27307: 00/11/17: Ray Andraka: Re: reset pulse ?
                27315: 00/11/17: <erika_uk@my-deja.com>: Re: reset pulse ?
                    27326: 00/11/18: Ray Andraka: Re: reset pulse ?
                27327: 00/11/18: chris shaw: Re: reset pulse ?
27198: 00/11/14: Qian Zhang: Des warning matter?
    27207: 00/11/15: Michael Strothjohann: Re: Des warning matter?
27202: 00/11/15: frank johson: test test just test
27204: 00/11/15: Utku Ozcan: BUFT conflict with LOC
    27205: 00/11/15: Utku Ozcan: Re: BUFT conflict with LOC
    27213: 00/11/15: Tom Branca: Re: BUFT conflict with LOC
        27219: 00/11/15: Tim Jaynes: Re: BUFT conflict with LOC
            27244: 00/11/16: Utku Ozcan: Re: BUFT conflict with LOC
        27239: 00/11/16: Utku Ozcan: Re: BUFT conflict with LOC
            27259: 00/11/16: Tom Branca: Re: BUFT conflict with LOC
                27275: 00/11/17: Utku Ozcan: Re: BUFT conflict with LOC
        27266: 00/11/16: Philip Freidin: Re: BUFT conflict with LOC
27209: 00/11/15: Richard Rooney: Problem with Endianess in Xilinx Tools.
    27223: 00/11/15: Brian Philofsky: Re: Problem with Endianess in Xilinx Tools.
    27225: 00/11/15: Phil Hays: Re: Problem with Endianess in Xilinx Tools.
27210: 00/11/15: Theron Hicks: .mif and .coe files in coregen vs. green mountain 68hc11
    27220: 00/11/15: Vikram Pasham: Re: .mif and .coe files in coregen vs. green mountain 68hc11
27214: 00/11/15: Ron Proveniers: jobs for FPGA designer (remote)
    27215: 00/11/15: Jamie Lokier: Re: jobs for FPGA designer (remote)
    27480: 00/11/23: Steve Goodwin: Re: jobs for FPGA designer (remote)
27217: 00/11/15: V Ram: Schematics & VHDL
    27233: 00/11/16: Edwin Naroska: Re: Schematics & VHDL
        27250: 00/11/16: V Ram: Re: Schematics & VHDL
            27316: 00/11/17: John Janusson: Re: Schematics & VHDL
            27416: 00/11/21: Rune Baeverrud: Re: Schematics & VHDL
    27248: 00/11/16: Brian Drummond: Re: Schematics & VHDL
    27319: 00/11/17: Greg Neff: Re: Schematics & VHDL
        27321: 00/11/17: Duane: Re: Schematics & VHDL
        27346: 00/11/18: rk: Re: Schematics & VHDL
            27515: 00/11/27: Kip Mussatt: Re: Schematics & VHDL
27218: 00/11/15: Michael Barr: ANNOUNCE: Checksum and CRC Code/Article
    27229: 00/11/15: Donald Gillies: Re: ANNOUNCE: Checksum and CRC Code/Article
        27230: 00/11/16: Dan Kotlow: Re: ANNOUNCE: Checksum and CRC Code/Article
            27231: 00/11/16: Niall Murphy: Re: ANNOUNCE: Checksum and CRC Code/Article
                27237: 00/11/17: David Empson: Re: ANNOUNCE: Checksum and CRC Code/Article
                    27265: 00/11/16: Eric Smith: Re: ANNOUNCE: Checksum and CRC Code/Article
                        27284: 00/11/17: Eric Doenges: Re: ANNOUNCE: Checksum and CRC Code/Article
                        27352: 00/11/19: Dan Kotlow: Re: ANNOUNCE: Checksum and CRC Code/Article
                27242: 00/11/16: Joe Durusau: Re: ANNOUNCE: Checksum and CRC Code/Article
                    27401: 00/11/21: Herman Oosthuysen: Re: ANNOUNCE: Checksum and CRC Code/Article
                    27409: 00/11/21: Paul Keinanen: Re: ANNOUNCE: Checksum and CRC Code/Article
                27283: 00/11/17: Dan Kotlow: Re: ANNOUNCE: Checksum and CRC Code/Article
                    27334: 00/11/18: Dan Kotlow: Re: ANNOUNCE: Checksum and CRC Code/Article
        27676: 00/12/02: Marc Warden: Re: ANNOUNCE: Checksum and CRC Code/Article
    27675: 00/12/02: Marc Warden: Re: ANNOUNCE: Checksum and CRC Code/Article
        27678: 00/12/02: Herman Oosthuysen: Re: ANNOUNCE: Checksum and CRC Code/Article
            27699: 00/12/04: <john_stiekema@my-deja.com>: Re: ANNOUNCE: Checksum and CRC Code/Article
                27701: 00/12/04: Herman Oosthuysen: Re: ANNOUNCE: Checksum and CRC Code/Article
                27716: 00/12/04: <spp@bob.eecs.berkeley.edu>: Re: ANNOUNCE: Checksum and CRC Code/Article
        27704: 00/12/04: Don Bockenfeld: Re: ANNOUNCE: Checksum and CRC Code/Article
            27707: 00/12/04: Don Bockenfeld: Re: ANNOUNCE: Checksum and CRC Code/Article
                27709: 00/12/04: <p.kootsookos@remove.ieee.org>: Re: ANNOUNCE: Checksum and CRC Code/Article
27221: 00/11/15: Qian Zhang: FPGA Pin Nunber
    27256: 00/11/16: Andy Peters: Re: FPGA Pin Nunber
        27282: 00/11/17: <yuryws@my-deja.com>: Re: FPGA Pin Nunber
    27285: 00/11/17: Martin Studach: Re: FPGA Pin Nunber
27224: 00/11/15: djley: Xilinx Foundation Sudent Version 1.5
    27236: 00/11/16: Michael Strothjohann: Re: Xilinx Foundation Sudent Version 1.5
    27270: 00/11/16: Anna Acevedo: Re: Xilinx Foundation Sudent Version 1.5
27226: 00/11/16: Hal Murray: Hidden DLL mode bit - 1x vs 2x feedback
27227: 00/11/16: S. Ramirez: Re: Microprocessor Verilog/VHDL Models
    27257: 00/11/16: Andy Peters: Re: Microprocessor Verilog/VHDL Models
        27278: 00/11/17: S. Ramirez: Re: Microprocessor Verilog/VHDL Models
    27276: 00/11/16: Ulf Samuelsson: Re: Microprocessor Verilog/VHDL Models
        27313: 00/11/17: Andy Peters: Re: Microprocessor Verilog/VHDL Models
    27344: 00/11/18: Terry Hicks: Re: Microprocessor Verilog/VHDL Models
        27345: 00/11/19: <bob_42690@my-deja.com>: Re: Microprocessor Verilog/VHDL Models
27228: 00/11/16: frank johson: mailing list for this newsgroup ?
27232: 00/11/16: Daniel Hanczewski: Basic question on PLD & FPGA
    27235: 00/11/16: Michael Strothjohann: Re: Basic question on PLD & FPGA
    27240: 00/11/16: Steve Fair: Re: Basic question on PLD & FPGA
    27262: 00/11/16: J.Niu: Re: Basic question on PLD & FPGA
        27301: 00/11/17: <cadmanager@my-deja.com>: Re: Basic question on PLD & FPGA
27234: 00/11/16: Christian Reichherzer: Problems wirh JTAG-Configuration of 18V512 and Spartan XCS40
    27246: 00/11/16: Ray Andraka: Re: Problems wirh JTAG-Configuration of 18V512 and Spartan XCS40
    27273: 00/11/16: <chadlamb@my-deja.com>: Re: Problems wirh JTAG-Configuration of 18V512 and Spartan XCS40
27238: 00/11/16: Peter Lang: VHDL & Spartan: How to power-up a Register to '1' ?
    27241: 00/11/16: Keith R. Williams: Re: VHDL & Spartan: How to power-up a Register to '1' ?
        27251: 00/11/16: Ron Proveniers: Re: VHDL & Spartan: How to power-up a Register to '1' ?
            27254: 00/11/16: Olivier Regnault: Re: VHDL & Spartan: How to power-up a Register to '1' ?
            27255: 00/11/16: Andy Peters: Re: VHDL & Spartan: How to power-up a Register to '1' ?
        27286: 00/11/17: Peter Lang: Re: VHDL & Spartan: How to power-up a Register to '1' ?
            27289: 00/11/17: Michael Strothjohann: Re: VHDL & Spartan: How to power-up a Register to '1' ?
                27293: 00/11/17: Peter Lang: Re: VHDL & Spartan: How to power-up a Register to '1' ?
            27312: 00/11/17: Andy Peters: Re: VHDL & Spartan: How to power-up a Register to '1' ?
                27325: 00/11/18: Ray Andraka: Re: VHDL & Spartan: How to power-up a Register to '1' ?
    27295: 00/11/17: Mike H.: Re: VHDL & Spartan: How to power-up a Register to '1' ?
        27309: 00/11/17: Ray Andraka: Re: VHDL & Spartan: How to power-up a Register to '1' ?
27245: 00/11/16: James Buchanan: Actel Compiler errors..... from Synplify?!
    27323: 00/11/17: rk: Re: Actel Compiler errors..... from Synplify?!
27249: 00/11/16: <cottons@concmp.com>: 5v parallel cable with 2.5/3.3v spartan II?
    27252: 00/11/16: Guy Eschemann: Re: 5v parallel cable with 2.5/3.3v spartan II?
    27318: 00/11/17: Mark Harvey: Re: 5v parallel cable with 2.5/3.3v spartan II?
27258: 00/11/16: Jan Gray: 8-way MIMD multiprocessor in an XCV50E
    27371: 00/11/20: Richard Meester: Re: 8-way MIMD multiprocessor in an XCV50E
        27389: 00/11/20: Jan Gray: Re: 8-way MIMD multiprocessor in an XCV50E
27260: 00/11/16: Arrigo Benedetti: Xilinx coregen problems
    27274: 00/11/16: Ray Andraka: Re: Xilinx coregen problems
        27279: 00/11/16: Arrigo Benedetti: Re: Xilinx coregen problems
            27281: 00/11/17: Ray Andraka: Re: Xilinx coregen problems
    27431: 00/11/21: Carl Rohrer: Re: Xilinx coregen problems
        27434: 00/11/21: Arrigo Benedetti: Re: Xilinx coregen problems
27261: 00/11/16: J.Niu: test
27264: 00/11/16: J.Niu: Can FPGA perform float point calculation?
    27267: 00/11/16: Andy Peters: Re: Can FPGA perform float point calculation?
    27268: 00/11/16: Ray Andraka: Re: Can FPGA perform float point calculation?
        27272: 00/11/16: Peter Alfke: Re: Can FPGA perform float point calculation?
        27288: 00/11/17: Tom: Re: Can FPGA perform float point calculation?
    27287: 00/11/17: Mirek: Re: Can FPGA perform float point calculation?
    27291: 00/11/17: Michael Strothjohann: Re: Can FPGA perform float point calculation?
        27300: 00/11/17: Ben Franchuk: Re: Can FPGA perform float point calculation?
            27407: 00/11/21: glen herrmannsfeldt: Re: Can FPGA perform float point calculation?
        27305: 00/11/17: Ray Andraka: Re: Can FPGA perform float point calculation?
            27320: 00/11/17: glen herrmannsfeldt: Re: Can FPGA perform float point calculation?
27271: 00/11/16: rk: AT6010 - 3.3V core and 5V I/Os
27280: 00/11/17: Recruit Express: Off subject-WIRELESS H/W S/W - pre IPO - San Jose
27290: 00/11/17: Nial Stewart: Spartan 3.3V Driving 5v input tristate + pull up problem...
    27298: 00/11/17: rickman: Re: Spartan 3.3V Driving 5v input tristate + pull up problem...
        27317: 00/11/17: Peter Alfke: Re: Spartan 3.3V Driving 5v input tristate + pull up problem...
    27311: 00/11/17: Andy Peters: Re: Spartan 3.3V Driving 5v input tristate + pull up problem...
        27324: 00/11/18: Ray Andraka: Re: Spartan 3.3V Driving 5v input tristate + pull up problem...
            27402: 00/11/20: Scott Schlachter: Re: Spartan 3.3V Driving 5v input tristate + pull up problem...
                27420: 00/11/21: Austin Lesea: Re: Spartan 3.3V Driving 5v input tristate + pull up problem...
            27417: 00/11/21: Nial Stewart: Re: Spartan 3.3V Driving 5v input tristate + pull up problem...
                27430: 00/11/21: Greg Neff: Re: Spartan 3.3V Driving 5v input tristate + pull up problem...
27296: 00/11/17: Wolfgang Kufer: Using FPGA as PCI target
    27299: 00/11/17: <cadmanager@my-deja.com>: Re: Using FPGA as PCI target
        27338: 00/11/19: Cameron Watt: Re: Using FPGA as PCI target
        27347: 00/11/19: Austin Franklin: Re: Using FPGA as PCI target
    27411: 00/11/21: John: Re: Using FPGA as PCI target
    27443: 00/11/22: <eml@riverside-machines.com.NOSPAM>: Re: Using FPGA as PCI target
        27451: 00/11/22: Eckhard Hammer: Re: Using FPGA as PCI target
            27459: 00/11/22: <eml@riverside-machines.com.NOSPAM>: Re: Using FPGA as PCI target
27297: 00/11/17: <longwayhome@my-deja.com>: Hardware suggestions for evolutionary experiments
    27363: 00/11/19: Neil Franklin: Re: Hardware suggestions for evolutionary experiments
        27376: 00/11/20: <longwayhome@my-deja.com>: Re: Hardware suggestions for evolutionary experiments
            27384: 00/11/20: Ray Andraka: Re: Hardware suggestions for evolutionary experiments
27302: 00/11/17: Simon Bilodeau: XC95288 : Problem using 16 bits counters
27303: 00/11/17: John Larkin: Xilinx config bits
    27328: 00/11/18: Brian Davis: Re: Xilinx config bits
        27369: 00/11/19: John Larkin: Re: Xilinx config bits
27304: 00/11/17: Olivier Regnault: Re: COREGEN ROM in VHDL... How do I use it?
27306: 00/11/17: Theron Hicks: COREGEN ROM in VHDL... How do I use it?
    27308: 00/11/17: John Ayer: Re: COREGEN ROM in VHDL... How do I use it?
    27310: 00/11/17: Andy Peters: Re: COREGEN ROM in VHDL... How do I use it?
        27518: 00/11/27: Theron Hicks: Re: COREGEN ROM in VHDL... How do I use it?
27314: 00/11/17: Ben Franchuk: Re: In the news
27322: 00/11/17: Rex Fisher: Altera MAX+PlusII v.s. Xilinx Foundation
    27332: 00/11/18: William Banzhof: Re: Altera MAX+PlusII v.s. Xilinx Foundation
    27333: 00/11/18: Mark Harvey: Re: Altera MAX+PlusII v.s. Xilinx Foundation
        27337: 00/11/18: S. Ramirez: Re: Altera MAX+PlusII v.s. Xilinx Foundation
            27528: 00/11/27: Steve Rencontre: Re: Altera MAX+PlusII v.s. Xilinx Foundation
                27793: 00/12/08: <harveytwyman@my-deja.com>: Re: Altera MAX+PlusII v.s. Xilinx Foundation
                    27799: 00/12/08: Austin Lesea: Re: Altera MAX+PlusII v.s. Xilinx Foundation
27329: 00/11/17: Philip Freidin: In the news
    27330: 00/11/17: John Larkin: Re: In the news
    27336: 00/11/18: Magnus Homann: Re: In the news
        27364: 00/11/20: Neil Franklin: Re: In the news
            27379: 00/11/20: Jamie Lokier: Re: In the news
                27383: 00/11/20: Magnus Homann: Re: In the news
                27394: 00/11/20: Neil Franklin: Re: In the news
    27372: 00/11/20: Dines Justesen: Re: In the news
        27374: 00/11/20: <kolja@prowokulta.org>: Re: In the news
        27375: 00/11/20: <kolja@prowokulta.org>: Re: In the news
            27381: 00/11/20: Rick Filipkiewicz: Re: In the news
        27395: 00/11/20: Neil Franklin: Re: In the news
            27413: 00/11/21: Magnus Homann: Re: In the news
    27388: 00/11/20: Andy Peters: Re: In the news
        27393: 00/11/20: Rick Filipkiewicz: Re: In the news
        27412: 00/11/21: Eric Montreal: Re: In the news
27331: 00/11/17: Bill Y.-C. Su: Xilinx Virtex-E : Interface to Parallel Port...
27335: 00/11/18: Anthony Ellis - LogicWorks: Altera 768 x 16 RAM?
    27341: 00/11/18: <serebr@my-deja.com>: Re: Altera 768 x 16 RAM?
        27342: 00/11/18: <serebr@my-deja.com>: Re: Altera 768 x 16 RAM?
27340: 00/11/18: Hul Tytus: re: manchester decoder
27343: 00/11/18: Ben Franchuk: Re: What is the fundamental limitation factor for FPGA clock rate
27348: 00/11/19: Austin Franklin: Real size of the Virtex-E parts...
27349: 00/11/19: V Ram: Synthesizable VHDL
    27350: 00/11/19: Muzaffer Kal: Re: Synthesizable VHDL
        27356: 00/11/19: Joel Kolstad: Re: Synthesizable VHDL
    27398: 00/11/20: David Emrich: Re: Synthesizable VHDL
    27400: 00/11/20: Scott Schlachter: Re: Synthesizable VHDL
27351: 00/11/19: stabilization: help
    27373: 00/11/20: aladdinn: Re: help
27353: 00/11/19: Akito: Xilinx FPGA: SRAM based, but is it dependant upon SEEPROM?
    27355: 00/11/19: Ray Andraka: Re: Xilinx FPGA: SRAM based, but is it dependant upon SEEPROM?
27354: 00/11/19: Eric Montreal: Rambus Reveals Plans To Collect Royalties From Chipset Makers
    27387: 00/11/20: Andy Peters: Re: Rambus Reveals Plans To Collect Royalties From Chipset Makers
        27410: 00/11/21: Eric Montreal: Re: Rambus Reveals Plans To Collect Royalties From Chipset Makers
27357: 00/11/19: Rick Filipkiewicz: Synthesis & Routing speed
    27358: 00/11/19: Ray Andraka: Re: Synthesis & Routing speed
        27365: 00/11/20: Rick Filipkiewicz: Re: Synthesis & Routing speed
    27382: 00/11/20: Rick Filipkiewicz: Re: Synthesis & Routing speed
        27385: 00/11/20: Joel Kolstad: Re: Synthesis & Routing speed
    27529: 00/11/27: Phil Martin: Re: Synthesis & Routing speed
        27584: 00/11/29: Rick Filipkiewicz: Re: Synthesis & Routing speed
            27655: 00/12/01: Phil Martin: Re: Synthesis & Routing speed
27359: 00/11/19: Daniel Nilsson: xilinx xc9500
    27360: 00/11/19: Bertram Geiger: Re: xilinx xc9500
27361: 00/11/19: Angela Macharia: Invest $6 get $40,000
27362: 00/11/19: Angela Macharia: invest $6 get $40,000
27368: 00/11/20: Barry Schneider: Long Island Verilog and VHDL people wanted!!
    27404: 00/11/21: <yuryws@my-deja.com>: Re: Long Island Verilog and VHDL people wanted!!
        27435: 00/11/22: Barry Schneider: Re: Long Island Verilog and VHDL people wanted!!
27377: 00/11/20: Gary Watson: What happens to CCLK after config on Xilinx Spartan II?
27378: 00/11/20: Chris Mc Clements: Virtex-E Global Set/Reset
27380: 00/11/20: Theron Hicks: initialization of ROM contents in COREGEN part
    27390: 00/11/20: Muzaffer Kal: Re: initialization of ROM contents in COREGEN part
27386: 00/11/20: Hawker: Xilinx and Tri state I/O
    27392: 00/11/20: Mikeandmax: Re: Xilinx and Tri state I/O
    27396: 00/11/20: Rick Filipkiewicz: Re: Xilinx and Tri state I/O
    27408: 00/11/21: Klaus Falser: Re: Xilinx and Tri state I/O
    27414: 00/11/21: Olaf Birkeland: Re: Xilinx and Tri state I/O
27391: 00/11/20: Zhen Luo: What is the fundamental limitation factor for FPGA clock rate
    27426: 00/11/21: Muzaffer Kal: Re: What is the fundamental limitation factor for FPGA clock rate
        27429: 00/11/21: glen herrmannsfeldt: Re: What is the fundamental limitation factor for FPGA clock rate
    27523: 00/11/27: Austin Lesea: Re: What is the fundamental limitation factor for FPGA clock rate
27397: 00/11/20: Mike: Altera FLEX 10k F.S.
27399: 00/11/20: S.Ivanov: Spartan and XC4000 configuration
    27403: 00/11/21: <yuryws@my-deja.com>: Re: Spartan and XC4000 configuration
        27424: 00/11/21: S.Ivanov: Re: Spartan and XC4000 configuration
    27405: 00/11/20: Philip Freidin: Re: Spartan and XC4000 configuration
        27425: 00/11/21: S.Ivanov: Re: Spartan and XC4000 configuration
    27473: 00/11/23: mohankumar: Re: Spartan and XC4000 configuration
27406: 00/11/20: Steve Oldridge: HELP! Lucent ORCA datasheets needed!
    27423: 00/11/21: <husby@my-deja.com>: Re: HELP! Lucent ORCA datasheets needed!
        27446: 00/11/22: rickman: Re: HELP! Lucent ORCA datasheets needed!
27415: 00/11/21: regal: Help :asynchronous Reset has no effect
    27427: 00/11/21: Olivier Regnault: Re: Help :asynchronous Reset has no effect
        27441: 00/11/22: regal: Re: Help :asynchronous Reset has no effect
27418: 00/11/21: Kevin Breeding: Resetting Flip-Flops in Virtex
    27428: 00/11/21: Olivier Regnault: Re: Resetting Flip-Flops in Virtex
        27438: 00/11/22: Markus Michel: Re: Resetting Flip-Flops in Virtex
            27445: 00/11/22: <eml@riverside-machines.com.NOSPAM>: Re: Resetting Flip-Flops in Virtex
    27444: 00/11/22: <eml@riverside-machines.com.NOSPAM>: Re: Resetting Flip-Flops in Virtex
27419: 00/11/21: <lkostov@my-deja.com>: Cores for EPP
27421: 00/11/21: Roli Z.: Webpack 3.2: Problem with Design Implementation
    27433: 00/11/22: Rick Filipkiewicz: Re: Webpack 3.2: Problem with Design Implementation
27422: 00/11/21: Steve Nordhauser: Low Power FPGA?
    27439: 00/11/22: Michael Strothjohann: Re: Low Power FPGA?
        27501: 00/11/24: rk: Re: Low Power FPGA?
            27524: 00/11/27: Steve Nordhauser: Re: Low Power FPGA?
27432: 00/11/22: Don Teeter: Another simple Xilinx question
    27436: 00/11/21: Philip Freidin: Re: Another simple Xilinx question
        27504: 00/11/24: Don Teeter: Re: Another simple Xilinx question
    27437: 00/11/22: <lkostov@my-deja.com>: Re: Another simple Xilinx question
    27540: 00/11/28: Bruce C. Headley: Re: Another simple Xilinx question
27440: 00/11/22: Frank Z.F Xie: Free Z80 ip core
27442: 00/11/22: Henrik =?iso-8859-1?Q?S=F8rensen?=: Post synthesis pre-NGDbuid gate-level functional simulation
27447: 00/11/22: walter haas: Clock Skew : Does Xilinx know what they're doing?
    27449: 00/11/22: Magnus Homann: Re: Clock Skew : Does Xilinx know what they're doing?
        27450: 00/11/22: Walter Haas: Re: Clock Skew : Does Xilinx know what they're doing?
            27454: 00/11/22: Muzaffer Kal: Re: Clock Skew : Does Xilinx know what they're doing?
            27460: 00/11/22: <eml@riverside-machines.com.NOSPAM>: Re: Clock Skew : Does Xilinx know what they're doing?
            27503: 00/11/25: Hal Murray: Re: Clock Skew : Does Xilinx know what they're doing?
                27505: 00/11/25: Rick Filipkiewicz: Re: Clock Skew : Does Xilinx know what they're doing?
        27465: 00/11/22: Rick Filipkiewicz: Re: Clock Skew : Does Xilinx know what they're doing?
            27468: 00/11/23: Greg Neff: Re: Clock Skew : Does Xilinx know what they're doing?
            27472: 00/11/23: Magnus Homann: Re: Clock Skew : Does Xilinx know what they're doing?
    27456: 00/11/22: Andy Peters: Re: Clock Skew : Does Xilinx know what they're doing?
    27457: 00/11/22: Greg Neff: Re: Clock Skew : Does Xilinx know what they're doing?
    27458: 00/11/22: Walter Haas: Re: Clock Skew : Does Xilinx know what they're doing?
        27463: 00/11/22: Greg Neff: Re: Clock Skew : Does Xilinx know what they're doing?
        27464: 00/11/22: Magnus Homann: Re: Clock Skew : Does Xilinx know what they're doing?
        27466: 00/11/23: glen herrmannsfeldt: Re: Clock Skew : Does Xilinx know what they're doing?
            27475: 00/11/23: <eml@riverside-machines.com.NOSPAM>: Re: Clock Skew : Does Xilinx know what they're doing?
                27486: 00/11/24: Rick Filipkiewicz: Re: Clock Skew : Does Xilinx know what they're doing?
    27478: 00/11/23: Allan Herriman: Re: Clock Skew : Does Xilinx know what they're doing?
    27481: 00/11/23: walter haas: Re: Clock Skew : Does Xilinx know what they're doing?
        27482: 00/11/23: Phil Hays: Re: Clock Skew : Does Xilinx know what they're doing?
        27484: 00/11/23: Greg Neff: Re: Clock Skew : Does Xilinx know what they're doing?
        27485: 00/11/23: Magnus Homann: Re: Clock Skew : Does Xilinx know what they're doing?
        27490: 00/11/24: fred: Re: Clock Skew : Does Xilinx know what they're doing?
            27497: 00/11/24: rk: Re: Clock Skew : Does Xilinx know what they're doing?
                27516: 00/11/27: fred: Re: Clock Skew : Does Xilinx know what they're doing?
                    27519: 00/11/27: rk: Re: Clock Skew : Does Xilinx know what they're doing?
    27521: 00/11/27: Walter Haas: Re: Clock Skew : Does Xilinx know what they're doing?
        27526: 00/11/27: Rick Filipkiewicz: Re: Clock Skew : Does Xilinx know what they're doing?
        27538: 00/11/28: Ray Andraka: Re: Clock Skew : Does Xilinx know what they're doing?
    27545: 00/11/28: Walter Haas: Re: Clock Skew : Does Xilinx know what they're doing?
        27590: 00/11/29: Newsbrowser: Re: Clock Skew : Does Xilinx know what they're doing?
27448: 00/11/22: Jurjen Boss: Power consumption FPGA...
    27462: 00/11/22: Theron Hicks: Re: Power consumption FPGA...
        27496: 00/11/24: rickman: Re: Power consumption FPGA...
    27525: 00/11/27: Austin Lesea: Re: Power consumption FPGA...
    28169: 00/12/23: John Larkin: Re: Power consumption FPGA...
27452: 00/11/22: Christian Werner: Virtex-PCI-Boards
    27453: 00/11/22: Steven Derrien: Re: Virtex-PCI-Boards
        27487: 00/11/24: Joel Kolstad: Re: Virtex-PCI-Boards
    27461: 00/11/22: Zhen Luo: Re: Virtex-PCI-Boards
    27477: 00/11/23: <fpgamax@my-deja.com>: Re: Virtex-PCI-Boards
    27507: 00/11/25: Martin Filteau: Re: Virtex-PCI-Boards
    27700: 00/12/04: <rob_dickinson@my-deja.com>: Re: Virtex-PCI-Boards
27455: 00/11/22: <fhipvl@hotmail.com>: 10 Pcs. Of Paper Money From Around the World 5551
27467: 00/11/22: Zhen Luo: Survey on design methodologies
    27520: 00/11/27: Nial Stewart: Re: Survey on design methodologies
27469: 00/11/23: Rcat1204: work from home
27470: 00/11/23: Akito: Xilinx XC4000** Speed Grades
    27488: 00/11/24: Joel Kolstad: Re: Xilinx XC4000** Speed Grades
27471: 00/11/23: Frank Z.F Xie: How to reduce the Tco
    27489: 00/11/24: Magnus Homann: Re: How to reduce the Tco
    27491: 00/11/24: Jean-Paul GOGLIO: Re: How to reduce the Tco
        27495: 00/11/24: Rick Filipkiewicz: Re: How to reduce the Tco
            27500: 00/11/24: Jean-Paul GOGLIO: Re: How to reduce the Tco
    27492: 00/11/24: Rick Filipkiewicz: Re: How to reduce the Tco
        27493: 00/11/24: Magnus Homann: Re: How to reduce the Tco
27474: 00/11/23: Jianyong Niu: survey of fpga application
27476: 00/11/23: David Gilchrist: XILINX Virtex SelectMAP configuration
27479: 00/11/23: <teleporteur@my-deja.com>: fpga kit from kanda HELP !
27483: 00/11/23: Daniel Nilsson: ide and dram controller
27498: 00/11/24: Philippe Chagny: FPGA Express warning ???
    27499: 00/11/24: Nicolas Matringe: Re: FPGA Express warning ???
27502: 00/11/24: Rick Filipkiewicz: NGDBUILD/UCF Problem
    27506: 00/11/25: Rick Filipkiewicz: Re: NGDBUILD/UCF Problem
        27588: 00/11/29: <eml@riverside-machines.com.NOSPAM>: Re: NGDBUILD/UCF Problem
            27602: 00/11/29: Rick Filipkiewicz: Re: NGDBUILD/UCF Problem
                27750: 00/12/06: Gary Cook: Re: NGDBUILD/UCF Problem
27508: 00/11/26: chsw: how do i?
    27517: 00/11/27: Srinivasan Venkataramanan: Re: how do i?
    27530: 00/11/27: Mujtaba Hamid: Re: how do i?
27509: 00/11/26: Fabio: fpga + live
    27636: 00/11/30: Fabio: R: fpga + live
27510: 00/11/26: Yves Le Henaff: Xilinx SPROM toaster
27511: 00/11/26: j: Fifo design problem
    27512: 00/11/27: Hal Murray: Re: Fifo design problem
    27514: 00/11/26: Frank Madison: Re: Fifo design problem
        27527: 00/11/27: Austin Franklin: Re: Fifo design problem
    27522: 00/11/27: Jason Daughenbaugh: Re: Fifo design problem
        27543: 00/11/28: Joel Kolstad: Re: Fifo design problem
            27553: 00/11/28: Hal Murray: Re: Fifo design problem
            27560: 00/11/28: Andy Peters: Re: Fifo design problem
                27573: 00/11/29: Joel Kolstad: Re: Fifo design problem
                    27596: 00/11/29: Andy Peters: Re: Fifo design problem
                    27604: 00/11/29: Rick Filipkiewicz: Re: Fifo design problem
                    27607: 00/11/29: Rick Filipkiewicz: Re: Fifo design problem
                        27617: 00/11/30: Joel Kolstad: Re: Fifo design problem
                            27618: 00/11/30: Hal Murray: Re: Fifo design problem
            27565: 00/11/29: Kent Orthner: Re: Fifo design problem
    27574: 00/11/29: Jean Nicolle: Re: Fifo design problem
        27576: 00/11/29: Joel Kolstad: Re: Fifo design problem
        27597: 00/11/29: Andy Peters: Re: Fifo design problem
27513: 00/11/27: Ben Franchuk: Re: Gates in a typical small MPU
27531: 00/11/27: <longwayhome@my-deja.com>: Xess - XS40-005XL question
    27532: 00/11/28: Akito: Re: Xess - XS40-005XL question
    27533: 00/11/28: Jonas Thor: Re: Xess - XS40-005XL question
        27564: 00/11/29: Neil Franklin: Re: Xess - XS40-005XL question
            27579: 00/11/29: <longwayhome@my-deja.com>: Re: Xess - XS40-005XL question
                27609: 00/11/29: Neil Franklin: Re: Xess - XS40-005XL question
            27702: 00/12/04: Phil James-Roxby: Re: Xess - XS40-005XL question
    27555: 00/11/28: Nick Bruty: Re: Xess - XS40-005XL question
27534: 00/11/28: Bill Lenihan: Virtex ROM ques.
    27537: 00/11/28: Rick Filipkiewicz: Re: Virtex ROM ques.
    27615: 00/11/29: A person: Re: Virtex ROM ques.
    27673: 00/12/01: Phil James-Roxby: Re: Virtex ROM ques.
        27677: 00/12/01: Eric Smith: Re: Virtex ROM ques.
            27686: 00/12/02: Neil Franklin: Re: Virtex ROM ques.
                27705: 00/12/04: Phil James-Roxby: Re: Virtex ROM ques.
                27766: 00/12/06: Eric Smith: JBits, Xilinx customer "support" (was Re: Virtex ROM ques.)
                    27777: 00/12/07: Eric Smith: Re: JBits, Xilinx customer "support" (was Re: Virtex ROM ques.)
                    27778: 00/12/07: Neil Franklin: Re: JBits, Xilinx customer "support" (was Re: Virtex ROM ques.)
    28217: 01/01/01: Jerry Schroefter: Re: Virtex ROM ques.
27535: 00/11/28: Pierre VERNEL: hard or soft core for FPGA?
    27541: 00/11/28: Wolfgang Loewer: Re: hard or soft core for FPGA?
        27583: 00/11/29: Nial Stewart: Re: hard or soft core for FPGA?
            27628: 00/11/30: Wolfgang Loewer: Re: hard or soft core for FPGA?
    27542: 00/11/28: Muzaffer Kal: Re: hard or soft core for FPGA?
    27544: 00/11/28: Muzaffer Kal: Re: hard or soft core for FPGA?
        27550: 00/11/28: Austin Lesea: Re: hard or soft core for FPGA?
            27551: 00/11/28: Keith R. Williams: Re: hard or soft core for FPGA?
    27549: 00/11/28: Dave Vanden Bout: Re: hard or soft core for FPGA?
    27552: 00/11/28: Ulf Samuelsson: Re: hard or soft core for FPGA?
    27556: 00/11/28: Nick Bruty: Re: hard or soft core for FPGA?
27536: 00/11/28: Klaus Falser: Re: 150MHz LVDS vs. 75MHz TTL
    27620: 00/11/30: Hal Murray: Re: 150MHz LVDS vs. 75MHz TTL
        27623: 00/11/30: Magnus Homann: Re: 150MHz LVDS vs. 75MHz TTL
            27638: 00/11/30: Hal Murray: Re: 150MHz LVDS vs. 75MHz TTL
                27648: 00/12/01: fred: Re: 150MHz LVDS vs. 75MHz TTL
                    27649: 00/12/01: fred: Re: 150MHz LVDS vs. 75MHz TTL
                    27804: 00/12/09: Hal Murray: Re: 150MHz LVDS vs. 75MHz TTL
        27627: 00/11/30: Klaus Falser: Re: 150MHz LVDS vs. 75MHz TTL
27539: 00/11/28: Utku Ozcan: floorplan thru UCF fail in M2.1i
27546: 00/11/28: Walter Haas: Newsgroup : Accessing through Netscape Navigator
    27547: 00/11/28: Keith R. Williams: Re: Newsgroup : Accessing through Netscape Navigator
    27548: 00/11/28: Walter Haas: Re: Newsgroup : Accessing through Netscape Navigator
    27570: 00/11/28: John Larkin: Re: Newsgroup : Accessing through Netscape Navigator
27559: 00/11/28: Nick Bruty: Xilinx Coolrunner going on last time buy?
    27563: 00/11/28: betsy thibault: Re: Xilinx Coolrunner going on last time buy?
        27603: 00/11/29: Richard Dungan: Re: Xilinx Coolrunner going on last time buy?
            27610: 00/11/30: Jim Granville: Re: Xilinx Coolrunner going on last time buy?
        27693: 00/12/03: Peter: Re: Xilinx Coolrunner going on last time buy?
    27632: 00/11/30: olivier.regnaultavnet.com: Re: Xilinx Coolrunner going on last time buy?
        27640: 00/12/01: Ulf Samuelsson: Re: Xilinx Coolrunner going on last time buy?
27562: 00/11/28: Pete Dudley: Virtex II DLL at 311MHz on XCV300e-8ES
    27571: 00/11/28: Austin Lesea: Re: Virtex II DLL at 311MHz on XCV300e-8ES
    27805: 00/12/09: Hal Murray: Re: Virtex II DLL at 311MHz on XCV300e-8ES
        27818: 00/12/10: pete dudley: Re: Virtex II DLL at 311MHz on XCV300e-8ES
27566: 00/11/29: Kent Orthner: Wide AND function.
    27568: 00/11/28: Duane: Re: Wide AND function.
        27572: 00/11/29: Kent Orthner: Re: Wide AND function.
            27585: 00/11/29: Rick Filipkiewicz: Re: Wide AND function.
            27703: 00/12/04: Phil James-Roxby: Re: Wide AND function.
                27725: 00/12/05: <erika_uk@my-deja.com>: Re: Wide AND function.
                    27732: 00/12/05: Phil James-Roxby: Re: Wide AND function.
                        27763: 00/12/06: Duane: Re: Wide AND function.
27567: 00/11/28: Arrigo Benedetti: question on initial states of FFs and GSR in Virtex
    27569: 00/11/28: rickman: Re: question on initial states of FFs and GSR in Virtex
        27595: 00/11/29: Muzaffer Kal: Re: question on initial states of FFs and GSR in Virtex
            27598: 00/11/29: Andy Peters: Re: question on initial states of FFs and GSR in Virtex
        27885: 00/12/13: Dan Hopper: Re: question on initial states of FFs and GSR in Virtex
27575: 00/11/29: <adam_hawes@dingoblue.net.au>: Virtex bitstream generation
    27591: 00/11/29: Nicolas Matringe: Re: Virtex bitstream generation
27577: 00/11/29: Akito: Gates in a typical small MPU
    27580: 00/11/29: <kolja@prowokulta.org>: Re: Gates in a typical small MPU
    27601: 00/11/29: Herbert Kleebauer: Re: Gates in a typical small MPU
27581: 00/11/29: Richard Wilkinson: Synplify Benchmarks
    27586: 00/11/29: Rick Filipkiewicz: Re: Synplify Benchmarks
    27592: 00/11/29: Joel Kolstad: Re: Synplify Benchmarks
        27593: 00/11/29: Richard Wilkinson: Re: Synplify Benchmarks
            27599: 00/11/29: Muzaffer Kal: Re: Synplify Benchmarks
            27606: 00/11/29: Rick Filipkiewicz: Re: Synplify Benchmarks
        27616: 00/11/29: A person: Re: Synplify Benchmarks
        27626: 00/11/30: Austin Franklin: Re: Synplify Benchmarks
            27634: 00/11/30: Magnus Homann: Re: Synplify Benchmarks
                27637: 00/11/30: Austin Franklin: Re: Synplify Benchmarks
                    27647: 00/12/01: Magnus Homann: Re: Synplify Benchmarks
                        27659: 00/12/01: Ray Andraka: Re: Synplify Benchmarks
                            27670: 00/12/01: Arrigo Benedetti: Re: Synplify Benchmarks
                        27665: 00/12/01: Joel Kolstad: Re: Synplify Benchmarks
                            27671: 00/12/01: Magnus Homann: Re: Synplify Benchmarks
                        27720: 00/12/05: Hal Murray: Re: Synplify Benchmarks
                            27721: 00/12/05: Ray Andraka: Re: Synplify Benchmarks
                27644: 00/12/01: Ray Andraka: Re: Synplify Benchmarks
                    27646: 00/12/01: Magnus Homann: Re: Synplify Benchmarks
                        27651: 00/12/01: Rick Filipkiewicz: Re: Synplify Benchmarks
                            27654: 00/12/01: <eml@riverside-machines.com.NOSPAM>: Re: Synplify Benchmarks
                                27662: 00/12/01: Ray Andraka: Re: Synplify Benchmarks
                        27660: 00/12/01: Ray Andraka: Re: Synplify Benchmarks
                            27672: 00/12/01: Magnus Homann: Re: Synplify Benchmarks
                    27674: 00/12/01: <pbmueller@my-deja.com>: Re: Synplify Benchmarks
                        27680: 00/12/02: Ray Andraka: Re: Synplify Benchmarks
27582: 00/11/29: Marc Reinert: Selfmade Cores or something similar (Xilinx)
    27612: 00/11/30: Ray Andraka: Re: Selfmade Cores or something similar (Xilinx)
27587: 00/11/29: Daio: FPGA Express warning
    27631: 00/11/30: Olivier REGNAULT: Re: FPGA Express warning
27600: 00/11/29: Robert K. Anderson: I am trying to instantiate ROM with a parameterized width
27605: 00/11/29: Isabelle: Reverse-engineering FPGA's
    27611: 00/11/29: Rick Filipkiewicz: Re: Reverse-engineering FPGA's
        27613: 00/11/30: Jan Gray: Re: Reverse-engineering FPGA's
    28060: 00/12/20: <harveytwyman@my-deja.com>: Re: Reverse-engineering FPGA's
        28074: 00/12/20: Austin Lesea: Re: Reverse-engineering FPGA's
        28082: 00/12/20: Peter Alfke: Re: Reverse-engineering FPGA's
27608: 00/11/29: C.Schlehaus: S: Exaclibur Kit
27614: 00/11/30: Oh Sheau Pyng: how to constaint a design without inserting pad?
27619: 00/11/30: jj: Orca 3t sram gsr question
    27630: 00/11/30: <husby@my-deja.com>: Re: Orca 3t sram gsr question
        27639: 00/11/30: j: Re: Orca 3t sram gsr question
    27643: 00/11/30: Bryan: Re: Orca 3t sram gsr question
27621: 00/11/30: korg: Job opportunities
27622: 00/11/30: Robert S.: high level timing by C generated VHDL?
    27625: 00/11/30: Eric Pearson: Re: high level timing by C generated VHDL?
        27633: 00/11/30: Robert S.: Re: high level timing by C generated VHDL?
27624: 00/11/30: Tim Gordon: FC II & Xilinx libraries macros
    27635: 00/11/30: Rick Filipkiewicz: Re: FC II & Xilinx libraries macros
        27726: 00/12/05: Tim Gordon: Re: FC II & Xilinx libraries macros
27629: 00/11/30: <mmeraliuk@yahoo.co.uk>: Routing constraints & A2.1i
    27685: 00/12/02: Utku Ozcan: Re: Routing constraints & A2.1i


Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015Jan2015

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search