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http://www.delphion.com/details?pn=USRE034363__ http://www.delphion.com/details?pn=US04642487__ The second patent by William S. Carter contains claims for configurable logic arrays in general and therefore could be attacked with publications in the field of cellular automata from the sixties and seventies. (von Neuman, Schaffner, Minnik, ...) The claims are for a logic array that contains a general interconnect structure as well as a special interconnect structure. Most work from the sixties will have only one or the other, but one might be able to find some weird publication that proposes to use both. The other patent is not as vulnerable to this attack, because it restricts itself to integrated circuits. Although one could try to attack on the basis that the restriction to integrated circuits is not relevant to the invention. I hope that Altera succeeds in attacking these patents. In article <8van4k$t66$1@news.inet.tele.dk>, "Dines Justesen" <dcj_k@rescom.dk> wrote: > > While I could make quite a few comments on this, > > I think I will just give you the link: > > > > > > http://www.xilinx.com/prs_rls/xilinxwin.htm > > Alteras response is here: > > http://www.altera.com/html/new/pressrel/pr_litigation1.html > > Dines > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27376
In article <6uaeavd1ix.fsf@chonsp.franklin.ch>, Neil Franklin <neil@franklin.ch.remove> wrote: > Bigger problem for "evolutionary hardware" (whatever that is) may be > that the XC4000 and Spartan series FPGAs only allow reconfiguring of > the entire chip, not partial reconfigurability. Thanks for your helpful reply. I had almost given up hope of getting one - I really appreciate it. Could you tell me why reconfiguring the entire chip is bad (is that just because its time consuming, and if so how time consuming is it) ? David Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27377
After config is done, does CCLK become a pullup or keeper on a Spartan II? Can I manually toggle CCLK by connecting an I/O pin to it, to get more bits out of the config prom? Or does it stay driven to whatever level? -- Gary Watson gary2@nexsan.com (you should leave off the digit two for email) Nexsan Technologies Ltd. Derby DE21 7BF ENGLAND UK-based Engineers: See our job postings at http://www.nexsan.com/pages/careers.htmArticle: 27378
The documentation from Xilinx recommends not to use the STARTUP_VIRTEX component for GSR but to write the set reset signal explicitly in the code. How can this be acheived? Is it simply a matter of omitting the STARTUP_VIRTEX component and connecting reset pins to an input port called reset, perhaps? plus, when simulating, the simprim vhdl file creates it's own reset on configuration model which overides the reset net anyway?? Any help would be greatlfully acceptedArticle: 27379
Neil Franklin writes: > Anyone know what features the 2 patents mentioned in the text forbid > Altera (and anyone else) from including in their devices? Who else is > endangered for being sued off of the market (I assume that Xilinx took > on Altera as largest competitor in 1993)? Filing date 1993 suggests > something that appeared in XC4000. > Dammit, after over 2 months of investigating the various chips, I was > just thinking of using Xilinx chips (the do seem to be the best). Now > I am going to have to rethink that (I belong to the dying breed of > people who think that societies wellfare should stand above maximal > individual profit). > Eith FLEX (and "its derivative programmable logic devices" = ACEX > and APEX?) illegal, what remains? (P.S. does anyone have a statemewnt > from Altera, what they are intending of doing?). No sympathy for Altera though. Have you seen the whole screenful of patent numbers on Altera Maxplus2's splash screen? Then every single generated text file includes a heavy boilerplate demanding no reverse engineering, no using the text for anything other than programming Altera devices etc. etc. Even GNU compilers don't place restrictions on the use of their output files. > MAX has not got enough FFs for me No kidding, especially when you count FFs in 1,000s :-) >> I'm sure this is all in the society's best interest. After all, that's >> what patents are for. Patents are intended for society's best interest by causing Xilinx to reveal their methods earlier rather than later. They probably did that too, and got their temporary monopoly in return. Is it good for society? Well you have admitted that Xilinx produce the best FPGAs... and their business model is bound to have helped with that. I guess the crux rests on whether Altera or other manufacturers would have produced better FPGAs, or FPGA tools, in the absence of Xilinx' patents. Personally I find the general lack of public information about internal FPGA architectures far more harmful. Despite the patents alleged purpose being to reveal secrets to the public -- they don't do that very well. > You can bet your soul on that :-). Hell and Eternal Damnation for all > patent lawmakers and lawyers. (Now why can't we get black magic or > Voodoo to work? :-)) > I suppose this has once again demonstrated that patent law has got to > be abolished. Completely. No replacement. The belief it was founded on > (patents are better (or less bad) than trade secrets) simply is false. > Trade secrets can be reverse engineered, patents are anti-competitive > devices that can not be legally circumvented. Indeed. Not that I'm for patents, but I'd be less offended by them if they revealed more technical detail in return for that stinking monopoly. Not only do you have to try and work around patents, get patents of your own for defence if you're a business (even when you don't want the theoretical benefit of patents: the monopoly), and keep an army of trained lawyers -- you _still_ have to reverse engineer the chips and tools anyway! > P.S. Have you signed the "no software patents in Europe" petition? > http://petition.eurolinux.org/ Yes. -- JamieArticle: 27380
Thanks to all who gave me assistance with COREGEN. As a result my HC11 system code is now functional (mostly). The only problem I have is in how to get the COREGEN rom to initialize properly. When I power the system up (in my simulation) the rom is initialized to all zero's. I can forcibly load it using a hex file or by means of the memory function, but as soon as I power up the device the memory is all zero's again. To make it function I need to load it immediately after power up. This needs to happen after each power up sequence. Obviously this won't work with a real device. I need a real unit to power up with real rom data. Is there a way to get this to happen in a simulation? Thanks, TheronArticle: 27381
kolja@prowokulta.org wrote: > http://www.delphion.com/details?pn=USRE034363__ > http://www.delphion.com/details?pn=US04642487__ > > The second patent by William S. Carter contains claims for configurable > logic arrays in general and therefore could be attacked with > publications in the field of cellular automata from the sixties and > seventies. (von Neuman, Schaffner, Minnik, ...) > > The claims are for a logic array that contains a general interconnect > structure as well as a special interconnect structure. Most > work from the sixties will have only one or the other, but one > might be able to find some weird publication that proposes to > use both. > > The other patent is not as vulnerable to this attack, because it > restricts itself to integrated circuits. > Although one could try to attack on the basis that the restriction > to integrated circuits is not relevant to the invention. > > I hope that Altera succeeds in attacking these patents. > > In article <8van4k$t66$1@news.inet.tele.dk>, > "Dines Justesen" <dcj_k@rescom.dk> wrote: > > > While I could make quite a few comments on this, > > > I think I will just give you the link: > > > > > > > > > http://www.xilinx.com/prs_rls/xilinxwin.htm > > > > Alteras response is here: > > > > http://www.altera.com/html/new/pressrel/pr_litigation1.html > > > > Dines > > > > > > Sent via Deja.com http://www.deja.com/ > Before you buy. Although I'm a Xilinx fan I think, in the spirit that competition is healthy, this might call for a global reponse from all us FPGA users. We could offer our collective services, a la Linux community, in an effort to come up with a way of re-engineering the Altera parts.Article: 27382
Rick Filipkiewicz wrote: > I've just upgraded my NT PC to a 600MHz PIII from a 450MHz PII and, to > my surprise, there's no discernable improvement in speed. Synplify is > exactly the same and the Xilinx PAR improves by a measly 2-3 min on a > run that used to take just over an hour. > > Am I doing something wrong or are these processes so memory bound that I > might as well use anything as long as its got 100MHz SDRAM ? [or an > Athlon PC with DDR memory]. > > Both PCs have 100MHz motherboards & I did remember to set the L2 cache > size entry in the registry. With 384MB of memory I'm nowhere near the > swapping limit. Oops! My stupidity. I was looking at files that I thought were pre the machine change but in fact, due to some redundancy in a makefile, had been rebuilt. The real results are: Synplify faster by between 1.5x for large compilcated modules and 2x for smaller ones. However PAR is a disappointment with an improvement of only 17% which means that it probably is memory-access bounded so to get it to go any faster I'll need PC133/150 SDRAM & maybe a new motherboard - still cheaper than the 3.1i ransom.Article: 27383
Jamie Lokier <spamfilter.nov2000@tantalophile.demon.co.uk> writes: > Not only do you have to try and work around patents, get patents of your > own for defence if you're a business (even when you don't want the > theoretical benefit of patents: the monopoly), and keep an army of > trained lawyers -- you _still_ have to reverse engineer the chips and > tools anyway! And this why I think patents hold no value to society, only to the company and, specially, their lawyers. It only forces companies to find new ways of performing the same task. Ways that might not be as good. So what are the odds we get rid of the patents in the near future? Pretty much zero. Homann -- Magnus Homann, M.Sc. CS & E d0asta@dtek.chalmers.seArticle: 27384
it's not bad, and in fact avoids a whole host of difficult obstacles present in partial configuration, however it also means your circuit state has to be offloaded, the FPGA reprogrammed and restarted, and intialized to your previous state. longwayhome@my-deja.com wrote: > > In article <6uaeavd1ix.fsf@chonsp.franklin.ch>, > Neil Franklin <neil@franklin.ch.remove> wrote: > > > Bigger problem for "evolutionary hardware" (whatever that is) may be > > that the XC4000 and Spartan series FPGAs only allow reconfiguring of > > the entire chip, not partial reconfigurability. > > Thanks for your helpful reply. I had almost given up hope of getting > one - I really appreciate it. Could you tell me why reconfiguring the > entire chip is bad (is that just because its time consuming, and if so > how time consuming is it) ? > > David > > Sent via Deja.com http://www.deja.com/ > Before you buy. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 27385
We went from an AMD K6/2-450 at work to an Athlon-700 and saw an almost 3x improvement in PAR speed (from ~3 hours on an XCV400E to ~1:05). I would expect a Pentium II/III-450 would have been faster (perhaps significantly so) than the K6-2, howeer. In all cases the PCs had enough memory to avoid swapping under NT/Win2K; Rick is correct that performance just comes to a complete stand-still when NT swaps. This requires ~512MB of RAM for our design, although usually task manager doesn't claim more than ~300MB is in use, so I imagine we might be able to squeak by on 256MB. Aldec is claiming that their VHDL simulator (Riviera) is 5x faster on Linux than NT (ActiveHDL). It's a little unclear exactly how they came up with those numbers, but it's a big enough boast that it's tempting to try out our own designs on a Linux box and see for ourselves. ---Joel KolstadArticle: 27386
(this may be a double post - sorry my browser is doing strange things) Hello all. I need to cost down some products that have a pile of 74LS244 and 74HC374s on them. Ideally I would love to be able to use an XC9500 part for this. The problem seems to be that I can't program a tri-state I/O in the 9500 if I understand correctly. Seems the next step would be a regular Spartan, but that does not seem to have tri state outputs/inputs either. This does not make sense as I thought I have seen folks use them for '8031 to i/o interfaces. What am I missing. What Xilinx Part (as that is the only toolset I have) would be good to use here. There won't be much other logic going on - decode to 64 outputs, encode 16 inputs and a few timers/dividers going on. Cost is a big factor. I need a 5V part with 5V outputs not 3.3 than can dive 5v ins. The end product needs to fire a pile (256) LEDs (2ma each) so I need to be able to sink some current as well. I assume I need to split this up into several small Xilinxs for current draw issues. Hopefully each xilinx can fire 64 points (~150ma). Thanx.Article: 27387
Eric Montreal wrote: > > I could write a long mail about it, but this link will do just as well : > > http://www.electronicnews.com/enews/news/5476-322NewsDetail.asp > > "Rambus’ runaway patent claims could extend even further than just chipsets, to ASICS, > programmable logic and graphics chips, according to Jim Handy, chief analyst at the > GartnerGroup Inc.’s Dataquest unit. " > > Rambus's swarm of bogus patents is approaching fast, any thoughs about the > "Rambus toll" ? I guess Rambus is gonna come after my ass because I put an SDRAM controller into my last FPGA? Here's a thought: BUY MICRON MEMORY. -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 27388
Philip Freidin wrote: > > While I could make quite a few comments on this, > I think I will just give you the link: > > http://www.xilinx.com/prs_rls/xilinxwin.htm Xilinx = Rambus? -- a ---------------------------- Andy Peters Sr. Electrical Engineer National Optical Astronomy Observatory 950 N Cherry Ave Tucson, AZ 85719 apeters (at) n o a o [dot] e d u "It is better to be silent and thought a fool, than to send an e-mail to the entire company and remove all doubt."Article: 27389
"Richard Meester" <rme@quest-innovations.com> wrote in message news:3A18DDD1.A23B4DF4@quest-innovations.com... > Interesting. With respect to the interconnect, we have developed several > hardware and software functionality, to connect them at high speed, and create a > network of these devices, which is scalable not only in the chip, but also > between chips and black boxes. Current rates at 200MBit/sec, but with virtex-E > parts 600MBit/sec (full duplex) may be achieved. I have a long reply that discusses FPGA MIMD memory and PE interconnect architectures, but I'm going to let it ferment for a few days. In the meantime, I note that Xilinx XAPP 234 (SelectLink) (www.xilinx.com/xapp/xapp234.pdf) discusses an interface that goes up to 311 Mb/s *per pin* (Virtex-E-7). I am also looking forward to Virtex-II's multi-gigabit/s serial I/O... Jan Gray, Gray Research LLCArticle: 27390
On Mon, 20 Nov 2000 10:03:38 -0500, Theron Hicks <hicksthe@egr.msu.edu> wrote: >Thanks to all who gave me assistance with COREGEN. As a result my HC11 >system code is now functional (mostly). The only problem I have is in >how to get the COREGEN rom to initialize properly. When I power the >system up (in my simulation) the rom is initialized to all zero's. I >can forcibly load it using a hex file or by means of the memory >function, but as soon as I power up the device the memory is all zero's >again. To make it function I need to load it immediately after power >up. This needs to happen after each power up sequence. Obviously this >won't work with a real device. I need a real unit to power up with real >rom data. Is there a way to get this to happen in a simulation? >Thanks, >Theron ROM module should load its .MIF when you start your simulation. Did you copy the mif file to the right place ? (I create my memories in another directory so I have to copy the edif and mif to their respective location). See if you find the mif and whether the core has the mif loading code. This should work in simulation. Muzaffer http://www.dspia.comArticle: 27391
Hi, guys I am writing my thesis now and one of my reviewers had a different view about FPGA clock rate. I felt FPGA could not achieve the general-purpose processor like clock rate (> 1GHz right now) because FPGA's structure and its components (like SRAM-based look-up table, programmable wiring switchbox) are just not fit for high clock rate. My reviewer pointed out that FPGAs couldn't achieve the general-purpose processor like clock rate because they had to be cost-effective. If Xilinx had a foundry like intel did and they would go all for the clock speed, they could make it to the similar range. I think there is some truth in it, but I still don't think FPGA could be that fast even if they do so. I would really like to hear your thoughts on this. Meanwhile, I also have a question, why is the I/O clock rate of Xilinx chips much slower than their internal clock rate? Would that finally become the bottleneck for improving the overall clock rate for FPGA applications? Also, since the clock rate on FPGA varies between applications, let's just assume that we have a design that is highly pipelinable, like an array-multiplier. Thanks! -- ZhenArticle: 27392
Hawker says >Hello all. > >I need to cost down some products that have a pile of 74LS244 and >74HC374s on them. Most CPLDs and FPGAs can do tristate i/o, and 2ma current is not an issue. I would suggest a call to your local FAE. Most vendors have 5v and 3.3v families, and free tools on the website, or handout CDROMs. For replacing all these buffers perhaps the Lattice GDX family might be more effective - tools are free on the web - 5v family as well as 3.3v family - www.latticesemi.comArticle: 27393
Andy Peters wrote: > Philip Freidin wrote: > > > > While I could make quite a few comments on this, > > I think I will just give you the link: > > > > http://www.xilinx.com/prs_rls/xilinxwin.htm > > Xilinx = Rambus? > No but any damages it receives will most likely go straight into the Rambus defence fund.Article: 27394
Jamie Lokier <spamfilter.nov2000@tantalophile.demon.co.uk> writes: > Neil Franklin writes: > > Anyone know what features the 2 patents mentioned in the text forbid > > Altera (and anyone else) from including in their devices? Who else is > > endangered for being sued off of the market (I assume that Xilinx took > > on Altera as largest competitor in 1993)? Filing date 1993 suggests > > something that appeared in XC4000. > > No sympathy for Altera though. Have you seen the whole screenful of > patent numbers on Altera Maxplus2's splash screen? No. As I said, I am just getting into FPGAs and on technical grounds have chosen Xilinx. So I have no Maxplus2 and have never used it. > Then every single generated text file includes a heavy boilerplate > demanding no reverse engineering, no using the text for anything other > than programming Altera devices etc. etc. Even GNU compilers don't > place restrictions on the use of their output files. Gawk! (GNU: that is not about gawk, your awk clone). > >> I'm sure this is all in the society's best interest. After all, that's > >> what patents are for. > > Patents are intended for society's best interest by causing Xilinx to > reveal their methods earlier rather than later. They probably did that > too, and got their temporary monopoly in return. > > Is it good for society? Well you have admitted that Xilinx produce the > best FPGAs... and their business model is bound to have helped with that. They do make em. But that is due to good engineering (nice design), not their patents. And their business model also contains such things like good marketing (good service to prospective customers). Both of these convinced me. > I guess the crux rests on whether Altera or other manufacturers would > have produced better FPGAs, or FPGA tools, in the absence of Xilinx' > patents. Arithmetic mode with 4 LUT inputs and additional mux + xor, instead of splitting into 2 3LUT arithmetic mode, as used by Altera, Lucent or even permanent 2 3LUTs with an optinal mux behind it as used by Atmel? > Personally I find the general lack of public information about internal > FPGA architectures far more harmful. Despite the patents alleged > purpose being to reveal secrets to the public -- they don't do that very > well. Exactly. Now if we got the bitstreams for an patent on their format... > Not only do you have to try and work around patents, get patents of your > own for defence if you're a business (even when you don't want the > theoretical benefit of patents: the monopoly), and keep an army of > trained lawyers -- you _still_ have to reverse engineer the chips and > tools anyway! .. and are not allowed to use the result, if it can be interpreted to be too similar to the patent. Tripple bummer. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Nerd, Geek, Hacker, Unix Guru, Sysadmin, Roleplayer, LARPer, MysticArticle: 27395
"Dines Justesen" <dcj_k@rescom.dk> writes: > > While I could make quite a few comments on this, > > I think I will just give you the link: > > > > > > http://www.xilinx.com/prs_rls/xilinxwin.htm > > Alteras response is here: > > http://www.altera.com/html/new/pressrel/pr_litigation1.html Thanks for the other sides link. Hmmm. Xilinx says Flex and all follow ups, Altera says only Flex8000 is treatened. Anyone got any info on who is bending the truth by how much? -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Nerd, Geek, Hacker, Unix Guru, Sysadmin, Roleplayer, LARPer, MysticArticle: 27396
Hawker wrote: > (this may be a double post - sorry my browser is doing strange things) > > Hello all. > > I need to cost down some products that have a pile of 74LS244 and > 74HC374s on them. Ideally I would love to be able to use an XC9500 part > for this. The problem seems to be that I can't program a tri-state I/O > in the 9500 if I understand correctly. Seems the next step would be a > regular Spartan, but that does not seem to have tri state outputs/inputs > either. This does not make sense as I thought I have seen folks use > them for '8031 to i/o interfaces. What am I missing. What Xilinx Part > (as that is the only toolset I have) would be good to use here. There > won't be much other logic going on - decode to 64 outputs, encode 16 > inputs and a few timers/dividers going on. Cost is a big factor. > > I need a 5V part with 5V outputs not 3.3 than can dive 5v ins. The end > product needs to fire a pile (256) LEDs (2ma each) so I need to be able > to sink some current as well. I assume I need to split this up into > several small Xilinxs for current draw issues. Hopefully each xilinx > can fire 64 points (~150ma). > > Thanx. We've been using the XC95K series almost since they came out and there's no problem with tri-state or bi-dir IOs. For all the Xilinx families I know of any IO pin can be used as in/out/bi. FYI With your voltage requirements the original XC95xxx parts are what you need with a 5V core voltage and IOs @ 5 or 3V3. The 95xxxXL parts parts use a 3V3 core and the 95xxxXV use 2V5. They're also really cheap for the amount of logic you get.Article: 27397
I don't know anything about these at all, but what I have are 2 boards out of a Dell OptiPlex GX1. Board number 1 is a PCI card with 5 Altera Flex EPF10K30RC240-3 chips with 4 Crucial 72 pin simms. There is 1 simm per processor, and there is only enough for 4 simms on the whole board. The outputs include 1, 9 pin serial and 4 smaller BNC type connectors. I know its hard to explain this, so if anybody wants pics just drop me a email and I'll send them to you. There is also a 59 pin connector built on the board for a internal ribbon cable, which is connected to the other card I have. Card Number 2 is a ISA Card with 1 Altera FLEX EPF10K20RC240-3. There is a DC/DC Voltage Converter built on board. The output is a 25 pin serial connector and likewise an internal 59 pin ribbon cable connector. The only description I could find on these board are these: Card 1-- Dual Beam Bit Board (PCI) Card 2-- Pixel Clock Generator (ISA) If anybody is interested drop me a email, I also have some National Instruments Cards too. Mike mikev@gvtel.comArticle: 27398
V Ram wrote: > > Hello! > > I have a few questions regarding synthesizing VHDL... > > Is there a website or document that describes what parts of VHDL > are/aren't synthesizable? I have the Designer's Guide to VHDL (Ashenden) > but I have no clue how synthesizable his code is... > > Typically the code I've written is simple enough that is has > synthesized(MaxPlus II & FPGA Express), but I might want to use variables > or do a few other things and I don't know what's suggested or not. > > My biggest complaint about Ashenden's book is that he doesn't really give > you clues as to what design method(s) you should take if you want your > designs to be synthesizable. From my memory of Ashenden's excellent book, except where he's specifically giving code for simulating your design, he provides synthesizable code. Of course there could be exceptions I've missed or forgotten, and simple because code is synthesizable doesn't mean it's supported by all synthesis tools. If you want further reading, Doug Perry and Ben Cohen discuss synthesis issues in their books. Regards, David Emrich Exemplar LogicArticle: 27399
Hello all, We have a board with 6 FPGAs. So far we have been using the XC4000 family for all the 6. The configuration is done from a 8-bit EEPROM via a daisy chain, where the first device is in Parallel Master Mode and the rest are in Serial Slave Mode. Now we want to switch to Spartan devices. The Spartan devices, however, don't have a parallel configuration mode. Since it is an existing board and we can not change anything, I am considering the option of keeping the first device in the chain as an XC4000 and replacing the other 5 with Spartans. Is this going to work? Is the serial data stream coming out of the XC4000 devise compatible with the serial stream for Spartan devices? Thanks, Stefan Ivanov
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