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Tom Branca wrote: > > Then the only way to do this is to identify the TBUF instances in your wild > carding. If for example you know that the all the TBUFs have an instance > name that matches the string --> "top/transmit/block/*tbuf*" then you could > create two constraints (the order in the UCF file DOES matter). > > INST "top/transmit/block/*" LOC=CLB_R1C22:CLB_R20C59; > INST "top/transmit/block/*tbuf*" LOC=TBUF_R1C22:TBUF_R20C59; > > If there is no way to currently pick out the TBUFs by their instance name > then you would need to either instantiate BUFTs in your hdl, make your BUFT > inference in a seperate hierarchial HDL module and indicate to your synthesis > tool to maintain the hierarchy, or floorplan the BUFTs using the > floorplanner. Generally I don't floorplan BUFTs unless I have instantiated > them, and know the name isn't going to change when I resynthesize. > > Cheers, > Tom Xilinx folks, thank you very much for your help. Yes, Tom's method above worked. I know now that I have to follow the rule: INST "top/transmit/block/*" LOC=CLB_...; INST "top/transmit/block/<all_tristate_buffers>" LOC=TBUF_...; INST "top/transmit/blocl/<all_RAMB4_*_elements>" LOC=RAMB4_...; MAP does not give any error. UtkuArticle: 27276
You might consider a simple instruction set simulator which=20 connects to bus model written in PLI for verilog. It aint an exact model but might do. --=20 Best Regards Ulf at atmel dot com These comment are intended to be my own personal view and may or may not be shared by my Employer Atmel Sweden. "S. Ramirez" <sramirez@deleet.cfl.rr.com> skrev i meddelandet = news:tNHQ5.36343$vc3.6411790@typhoon.tampabay.rr.com... > I just found out that Synopsis wants $80K for a one year license = of > their Mot 5307 or 8260 instruction set model! I consider this an ARM = and a > leg!! > My client will never go for this. I guess I'm back to just = simulating > the FPGAs and memories on the board, unless one of you out there knows = of a > cheaper alternative. > -Simon Ramirez, Consultant > Synchronous Design, Inc. >=20 > ******************************************************************** > > Does anyone here know of sources for microprocessor Verilog or = VHDL > > behavioral models? > > I am doing a board level simulation that involves FPGAs, = memories, > > peanut components, and a Mot ColdFire microprocessor. I checked = with Mot > > about providing a C behavioral model or an encrypted Verilog/VHDL > behavioral > > model, and they referred me to the Big S -- Synopsis. This means = that it > > will cost an ARM and a leg, and I'm not talking about an ARM = processor! > > Does anyone know of alternatives? > > -Simon Ramirez, Consultant > > Synchronous Design, Inc. >=20 >=20 >=20Article: 27277
Yes.Article: 27278
Andy,
Thanks for the suggestion, but I don't have time to write a 5307
simulation model; that's why I want to buy one at a reasonable cost!
But I am going to take a suggestion from you -- Janick Bergeron's book
on testbenches. Every time I review old code to get some reuse out of it, I
also get embarrassed. Good thing we improve ourselves on every project,
huh?
-Simon Ramire, Consultant
Synchronous Design, Inc.
> It may be worth your while to spend a week or so writing a model of the
> 5307. All it really needs to do is drive the busses and strobes at the
> proper time, in response to a "program." For "small" programs, I just
> have a little table in the code. For larger ones, I read the "program"
> from a file. I use VHDL records for each cycle. Use procedures for
> things like "bus read" and "bus write" and "interrupt ack" and so
> forth. I'd write it so that it's a unit-delay model, and have some way
> of adding real-life prop delays for post-FPGA-route timing sim (generics
> are good!). The timing model would probably also take setup and hold
> times into account, as well as checking to make sure the clock isn't too
> fast, and such. Maybe you could sell it to Motorola and make back your
> investment!
>
> I started to do a 5206e model but the project got put on the back
> burner. I did something similar with this Cypress VMEbus chip set I
> used. I'd send you that model if it wasn't an embarrassing mess. (I
> bought a copy of Janick Bergeron's book and now I hate all of my test
> benches!)
>
> -- a
> ----------------------------
> Andy Peters
> Sr. Electrical Engineer
> National Optical Astronomy Observatory
> 950 N Cherry Ave
> Tucson, AZ 85719
Article: 27279Hi Ray, these error messages are generated by coregen, not by the simulator. My feeling is that there are some wrong permissions in $XILINX/coregen/ip (I'm running Solaris 2.7). While Xilinx is looking at this I'm studying the theory of array multipliers to see how I can make one in VHDL... Thanks, -Arrigo Ray Andraka <ray@andraka.com> writes: > I installed the latest IP two days ago without incident, and it simulates fine. > Sounds like you need to compile the library, and if that has been done, make > sure it is mapped to your simulator. You also may have to put the edfs in the > projects you updated. There are some step by step install instructions and > compile scripts on the xilinx website that make the whole thing easier. > > Arrigo Benedetti wrote: > > > > I have found that after upgrading to the latest service packs for > > Xilinx Alliance M3.2i and coregen I am no longer able to generate > > any multiplier core: > > > > ERROR: Error locating library for class com.xilinx.ip.parm_v2_0.parm_scaled_adder$virtex$adder_inputs_type. > > ERROR: Error loading library for class com.xilinx.ip.parm_v2_0.parm_scaled_adder$virtex$adder_inputs_type > > ERROR: Could not load/define class file com.xilinx.ip.parm_v2_0.parm_scaled_adder$virtex$adder_inputs_type. > > ERROR: An internal error has occurred. To resolve this error, please consult the Answers Database at http://support.xilinx.com > > ERROR: Sim has a problem implementing the selected core. Implementation netlist will not be generated. > > ERROR: SimGenerator: Failure of Sim to implement customization parameters core multhaccko > > ERROR: Core multhaccko did not generate EDIF implementation netlist (.EDN) file. > > WARNING: Warnings and/or errors encountered while generating multhaccko (Multiplier 2.0) All output products requested may not have been generated. > > ERROR: Elaboration failure for core Multiplier > > > > ERROR: Elaboration of core Multiplier failed. > > > > Xilinx tech support has already been alerted. Does anyone know a cure for this? > > > > Thanks, > > > > -Arrigo > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com or http://www.fpga-guru.com -- Dr. Arrigo Benedetti o e-mail: arrigo@vision.caltech.edu Caltech, MS 136-93 < > phone: (626) 395-3129 Pasadena, CA 91125 / \ fax: (626) 795-8649 -- We choose to go to the moon in this decade and do the other things not because they are easy, but because they are hard. - John F. KennedyArticle: 27280
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Mine's on a PC running WINNT, so we have horses of a different color here. For multipliers, you might have a look at my website to get your started on the right foot. Arrigo Benedetti wrote: > > Hi Ray, > > these error messages are generated by coregen, not by the simulator. My feeling > is that there are some wrong permissions in $XILINX/coregen/ip (I'm running > Solaris 2.7). While Xilinx is looking at this I'm studying the theory of array > multipliers to see how I can make one in VHDL... > > Thanks, > -Arrigo > > Ray Andraka <ray@andraka.com> writes: > > > I installed the latest IP two days ago without incident, and it simulates fine. > > Sounds like you need to compile the library, and if that has been done, make > > sure it is mapped to your simulator. You also may have to put the edfs in the > > projects you updated. There are some step by step install instructions and > > compile scripts on the xilinx website that make the whole thing easier. > > > > Arrigo Benedetti wrote: > > > > > > I have found that after upgrading to the latest service packs for > > > Xilinx Alliance M3.2i and coregen I am no longer able to generate > > > any multiplier core: > > > > > > ERROR: Error locating library for class com.xilinx.ip.parm_v2_0.parm_scaled_adder$virtex$adder_inputs_type. > > > ERROR: Error loading library for class com.xilinx.ip.parm_v2_0.parm_scaled_adder$virtex$adder_inputs_type > > > ERROR: Could not load/define class file com.xilinx.ip.parm_v2_0.parm_scaled_adder$virtex$adder_inputs_type. > > > ERROR: An internal error has occurred. To resolve this error, please consult the Answers Database at http://support.xilinx.com > > > ERROR: Sim has a problem implementing the selected core. Implementation netlist will not be generated. > > > ERROR: SimGenerator: Failure of Sim to implement customization parameters core multhaccko > > > ERROR: Core multhaccko did not generate EDIF implementation netlist (.EDN) file. > > > WARNING: Warnings and/or errors encountered while generating multhaccko (Multiplier 2.0) All output products requested may not have been generated. > > > ERROR: Elaboration failure for core Multiplier > > > > > > ERROR: Elaboration of core Multiplier failed. > > > > > > Xilinx tech support has already been alerted. Does anyone know a cure for this? > > > > > > Thanks, > > > > > > -Arrigo > > > > -- > > -Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com or http://www.fpga-guru.com > > -- > Dr. Arrigo Benedetti o e-mail: arrigo@vision.caltech.edu > Caltech, MS 136-93 < > phone: (626) 395-3129 > Pasadena, CA 91125 / \ fax: (626) 795-8649 > -- > We choose to go to the moon in this decade and do the other things not > because they are easy, but because they are hard. - John F. Kennedy -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.com or http://www.fpga-guru.comArticle: 27282
Looks like you are trying to use attributes of Cypress VHDL tools. These attributes are most likely not supported by Xilinx (Synopsys) tools. As Andy pointed out use UCF file of FPGA Express constraints editor. -- Yury Wolf In article <8v18lk$1bi2$2@noao.edu>, Andy Peters <"apeters <"@> n o a o [.] e d u> wrote: > Qian Zhang wrote: > > > > now I plan to setup my Spartan S40PQ240 pins, > > > > but check syntax says: > > > > "pinnum not declared " > > > > can anyone tell me how to define the FPGA pins > > > > to the corresponding input and output? > > Assign the pins in the UCF file. > > -- a > ---------------------------- > Andy Peters > Sr. Electrical Engineer > National Optical Astronomy Observatory > 950 N Cherry Ave > Tucson, AZ 85719 > apeters (at) n o a o [dot] e d u > > "It is better to be silent and thought a fool, > than to send an e-mail to the entire company > and remove all doubt." > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27283
On Thu, 16 Nov 2000 08:55:30 -0000, "Niall Murphy" <nmurphynews@panelsoft.com> wrote: >My >question is that I am curious if a CRC would solve your specific problem. >When you say that you get corrupted dataconstantly, do you mean that you get >data with a valid checksum, even though it has been corrupted? > Yes -- undetected errors. I don't get the checksums -- the communications provider forwards the data to me via Email once they reach the ground station. His data link layer protocol (both subscriber<->satellite and satellite<->ground station) would induce retransmissions if the Fletcher checksum were not failing to spot the need for them. >Mathematically CRC is definitly better than a checksum, I have just not come >across a real practical case where the difference could be identified. I >suspect that it is a function of how large the packets are - 16 bits as a >check on 100 bytes seems reasonable, but as a check on 10000 bytes seems >riskier to me (but I do not know if there is a simple mathematical >justification of that) - what is the ratio on your appication. If anyone >knows a recommended ratio where you should switch to CRC I would be curious. > Niall Murphy (http://www.panelsoft.com) > Here's what I think I know: If I recall correctly, the standards CRC-16 and CRC-CCITT are good up to 32,768 BITS (including the CRC itself). For shorter messages (up to 255 BITS) , one can use the (16-bit) generator polynomial of the code BCH(255,239). This detects ANY four bits in error. It also has a much better weight distribution (# of undetected 5-bit errors, 6-bit errors, etc.) than the standards, when within its length limits. To this, you can add an overall parity bit and get an extra bit of detection in a 256 bit packet (still only 239 data bits). I'll look up my figures at the office tomorrow (and the polynomial) and post again. -DanArticle: 27284
Eric Smith <eric-no-spam-for-me@brouhaha.com> writes: >Some of those claims (specifically the double-bit and odd-number-of-bits) >are only true if the block size is below a maximum. I don't know offhand >what the maximum is, but it's under 65536 bits. Proof left as an >exercise to the reader. I believe a CRC will 'loop around' at (2^n)-1 bits, where n is the length of your CRC checksum. This means a CRC-16 can be used on up to 2^16-1 bits before it starts repeating itself. (CAUTION: this is off the top of my head, since I don't have the book I read this in handy right now.). -- ________________________________________________________________________ Dipl.-Ing. Eric Doenges http://www.rcs.ei.tum.de Institute for Real-Time Computer Systems (RCS) fon +49-89-289-23590 Technische Universitaet Muenchen, D-80290 Muenchen fax +49-89-289-23555Article: 27285
Convert the pad file to the ucf format. This is a good link: http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=3534 M Qian Zhang wrote: > > now I plan to setup my Spartan S40PQ240 pins, > ... For reply, remove the "x" from my email addressArticle: 27286
Hi, I think I must decribe my problem more precise: I only want that an CLB Register FF inits to one after the configuration of the FPGA is done. I dont want to use expilicit asynchron set lines to do this. thanks 4 help peterArticle: 27287
"J.Niu" <COP00JN@sheffield.ac.uk> wrote in message news:3A143DA7.C7182B76@sheffield.ac.uk... > I post a question here... anybody know if fpga support float point > calculation? thanx. > > jy Yes of course. More information you can find here: http://www.dcd.com.pl/english/ipcores.htm#arit MirekArticle: 27288
"Ray Andraka" wrote in message: > Yes, but it will cost you more area per function, especially for add/subtract. > Of course, you or someone will have to design the floating point hardware just > as you would any other hardware to be put in the FPGA. Hi, DCD was implemented a few Floating Point design in FPGA I think that doesn't cost so much resources as some designers think. Of course if you compare it to the same size fixed point stuff, Floating Point consume more resources. Everything depends on reference point and meaning "more and less resources". Regards, Tomek Krzyzak ----------------------------------------- VCEO, Digital Core Design tel. ++48 32 282 82 66 web : http://www.dcd.com.pl -----------------------------------------Article: 27289
Hi,
ok, you don't want to use a external set/reset - wire.
You may generate an internal set/reset-signal in a separate
process clocked by your global clock, and *gate*
your global clock bevor it is send to all other FFs.
The net-effect is a set/reset to your FFs after
the initialisation but bevor normal operation.
( in effect you add an additional initialisation
phase bevor normal operation )
regards
michael
Peter Lang schrieb:
> Hi,
> I think I must decribe my problem more precise:
> I only want that an CLB Register FF inits to one after the configuration of
> the FPGA is
> done. I dont want to use expilicit asynchron set lines to do this.
> thanks 4 help
> peter
Article: 27290
The guy who did the board I'm currently working on had a
3.3V IO spartan 2 driving (or not) the 5V CMOS inputs
on an ADC.
I implemented the 'tri-state when driving high ie
signal_out <= 'Z' when (signal_internal = '1') else signal_i;
with an external pull up' which allows the driven signals
to reach 5V, but a couple of the lines are clocks and
were taking 40nS to get from 1V -> 4V. I think this was
causing problems with the DAC.
I then tried the 'drive it to 3.3V high level then
tristate' improvement ie
signal_out <= 'Z' when (signal_internal = '1' and signal_out = '1') else
signal_internal;
This improved things a lot speedwise, but I started getting
a fair bit of ringing around 3.3 -> 4 V and the ADC input
started 'double clocking' on some of the edges (the traces
are fairly long).
The Xilinx app note (Tech Topic VTT002 v1.0) says
"Ringing can be avoided by following proper board design
practices", but most termination techniques are concerned
with terminating a trace with it's characteristic
impedance, not having to simultaneously pull the signal
high as hard as possible to get a fast rising edge.
I've experimented with various terminations, and with
varying the DRIVE attribute of the output to see if I
can cut down on the problem, withought much success.
Has anone come across a similar problem and come up with a
satisfactory solution?
Thanks for any suggestions,
Nial Stewart.
Article: 27291
Hi,
yes, fp is like any other arithmetic.
Have in mind, it will be costly in terms of area
and speed will be slow, compared to
full custom logic
( pentium or any floating-point dsp ).
Some applicalions can use piplining.
It is worth to do as much as possible
in integer arithmetic. It depends on your
application, but if it realy needs floating-point,
try to use a low-cost floatingpoint dsp
( like 67xx, .. ).
regards
michael
"J.Niu" schrieb:
> I post a question here... anybody know if fpga support float point
> calculation? thanx.
>
> jy
Article: 27292ooh experts, any input here ? ray, where are you hidding !!!!??? In article <8usdpl$qbl$1@nnrp1.deja.com>, erika_uk@my-deja.com wrote: > I forget to add, is there any prefixed from where i can drive it ? > > In article <8usd7d$pqh$1@nnrp1.deja.com>, > erika_uk@my-deja.com wrote: > > hey, > > > > just basic question. will the reset pulse be generated "automatically" > > after configuration? can i use this pulse to clear some counters > > synchrnously. i don't want to infer the startup because of...(the > > famous story) > > > > thanks > > > > --Erika > > > > Sent via Deja.com http://www.deja.com/ > > Before you buy. > > > > Sent via Deja.com http://www.deja.com/ > Before you buy. > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27293
Hi Michael, I think I dont need any logic to implement my CLB Register FF inits to one after the configuration because the init state of each FF can be individually configured via the Bitstream send to the FPGA. So its a kind of property which I have to put at the registered signal. But I dont know how to do this via VHDL. With schematic entry I used a property like "INIT=S" thanks 4 help peterArticle: 27294
Just use the Convert File option in MAXPLUS2 best regards In article <3a103889$1@news.xetron.com>, "Dan Alley" <dana@xetron.com> wrote: > What is the method for conversion of a POF file for an Altera EPC1441 device > into an equivalent POF file for an Altera EPC2, when only the POF file > exists? > > Thanks in advance, Dan > > Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27295
"Peter Lang" <Peter.Lang@rmvmachinevision.de> wrote in message news:8v0kfs$i4p$04$1@news.t-online.com... > Hi, > by default FGPA Express will init all Registers in my Spartan device to > zero. > How can I change this default? > When doing schematic entry this was easyly done by adding "INIT=S" > But how can I do this with VHDL? I think you can do this by instantiating a "ROC" function (Reset On Configuration) and using the output to preset your registers. Do a search for ROC in the Xilinx on-line documentation. HTH MHArticle: 27296
Hi All, I want to use an FPGA as PCI target. What are the possibilities of configuring this device? Must I use an onboard flash/eeprom device as configuration memory or is there any way to download the configuration data via the pci bus? At what time during boot the pci target must be ready or is it possible to reconfigure the target during runtime? Thanks, WolfgangArticle: 27297
Hi I'm trying to get started in evolutionary hardware experiments as a hobby. I'm finding it hard to get a handle on what hardware I ought to buy to get started. Last time I thought I had found a suitable board (one of the 300 dollar xess boards) someone helpfully informed me that it was flash ram based and therefore only good for something like 50k rewrites. Could someone give me suggestions for suitable hardware (i have a 2k USD max budget for this). I really just want to feed it input and check its output (input and output as numbers if possible). Thanks very much. David Sent via Deja.com http://www.deja.com/ Before you buy.Article: 27298
Nial Stewart wrote: > > The guy who did the board I'm currently working on had a > 3.3V IO spartan 2 driving (or not) the 5V CMOS inputs > on an ADC. > > I implemented the 'tri-state when driving high ie > > signal_out <= 'Z' when (signal_internal = '1') else signal_i; > > with an external pull up' which allows the driven signals > to reach 5V, but a couple of the lines are clocks and > were taking 40nS to get from 1V -> 4V. I think this was > causing problems with the DAC. Can you explain the problems you saw in this mode? I am curious since the double clocking you saw when you had ringing is also a problem that could be caused by a slow edge. A slow edge has less dV/dt and can become non-monotonic from noise. This can cause double clocking when it is crossing the threshold of the input. If you don't see double clocking in this case, maybe there is a different way to fix your problem. > I then tried the 'drive it to 3.3V high level then > tristate' improvement ie > > signal_out <= 'Z' when (signal_internal = '1' and signal_out = '1') else > signal_internal; > > This improved things a lot speedwise, but I started getting > a fair bit of ringing around 3.3 -> 4 V and the ADC input > started 'double clocking' on some of the edges (the traces > are fairly long). > > The Xilinx app note (Tech Topic VTT002 v1.0) says > "Ringing can be avoided by following proper board design > practices", but most termination techniques are concerned > with terminating a trace with it's characteristic > impedance, not having to simultaneously pull the signal > high as hard as possible to get a fast rising edge. > > I've experimented with various terminations, and with > varying the DRIVE attribute of the output to see if I > can cut down on the problem, withought much success. > > Has anone come across a similar problem and come up with a > satisfactory solution? I have not tried this trick, but is it possible that the ringing is actually causing an oscillation of the tristate driver? The equation lets the output drive until the input threshold is crossed. Then the driver is turned off. But if a small amount of ringing brings the output back low enough to trip the input threshold again, the output will drive hard again, causing more ringing. Is is possible to use the tristate control FF with the output signal driving the clock? Then once the clock turns the tristate off, it will stay off no matter what ringing happens. Of course this will stop the oscillation, but you still have the initial ring that may still cause problems on a clock line. But that truly is layout and edge rate related. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design Arius 4 King Ave Frederick, MD 21701-3110 301-682-7772 Voice 301-682-7666 FAX Internet URL http://www.arius.comArticle: 27299
To use onboard FPGA with PCI bus, YOU MUST have 1 device that work on PCI POWER ON. It means many solutions: 1: got a specific PCI compliant interface device 2: got A OTP FPGA (like ACTEL) who's got a PCI IP or customer PCI interface 3: got FPGA whith EEPROM (like FLEX10K) " " " So, then, all others FPGA on your card, could be programmed across PCI bus. Yes it's possible to configure the PCI interface FPGA during POWER ON of PCI bus. Just look for the maximum configuration time of the FPGA, and compare whith PCI Boot Delay. Best regards In article <3A1536C3.9407534D@rsd.rsd.de>, Wolfgang Kufer <wolfgang.kufer@rsd.rsd.de> wrote: > Hi All, > > I want to use an FPGA as PCI target. > > What are the possibilities of configuring this device? > Must I use an onboard flash/eeprom device as configuration memory or is > there any way to download the configuration data via the pci bus? > > At what time during boot the pci target must be ready or is it possible > to reconfigure the target during runtime? > > Thanks, Wolfgang > Sent via Deja.com http://www.deja.com/ Before you buy.
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