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Threads Starting Mar 2002
40174: 02/03/01: Thomas Zipper: high-speed clock distribution/divider in a FPGA?
40186: 02/03/01: Austin Lesea: Re: high-speed clock distribution/divider in a FPGA?
40187: 02/03/01: Theron Hicks (Terry): Re: high-speed clock distribution/divider in a FPGA?
40188: 02/03/01: Austin Lesea: Re: high-speed clock distribution/divider in a FPGA?
40176: 02/03/01: Colin Bury: Clock multiplier/ADPLL in PLD
40181: 02/03/01: Ray Andraka: Re: Clock multiplier/ADPLL in PLD
40190: 02/03/01: John_H: Re: Clock multiplier/ADPLL in PLD
40198: 02/03/01: Ray Andraka: Re: Clock multiplier/ADPLL in PLD
40211: 02/03/02: John_H: Re: Clock multiplier/ADPLL in PLD
40185: 02/03/01: Antonio: clock nets use non-dedicated resources
40194: 02/03/01: Nicholas Weaver: Xilinx Virtex Family die photos...
40215: 02/03/02: Speedy: Re: Xilinx Virtex Family die photos...
40217: 02/03/02: Nicholas Weaver: Re: Xilinx Virtex Family die photos...
40274: 02/03/04: Austin Lesea: Re: Xilinx Virtex Family die photos...
40197: 02/03/01: jerry1111: Altera Excalibur
40205: 02/03/01: Paul: Re: Altera Excalibur
40212: 02/03/01: James Horn: Re: Altera Excalibur
40216: 02/03/02: Peter Ormsby: Re: Altera Excalibur
40219: 02/03/02: jerry1111: Re: Altera Excalibur
40220: 02/03/02: Victor Schutte: Re: Altera Excalibur
40221: 02/03/02: jerry1111: Re: Altera Excalibur
40226: 02/03/02: Muzaffer Kal: Re: Altera Excalibur
40232: 02/03/02: Petter Gustad: Re: Altera Excalibur
40235: 02/03/03: Peter Ormsby: Re: Altera Excalibur
40241: 02/03/03: jerry1111: Re: Altera Excalibur
40202: 02/03/01: praveen: simulating time_sim.vhd file
40224: 02/03/02: Joey Nelson: Embedding counting in an FSM.
40230: 02/03/02: Mike Treseler: Re: Embedding counting in an FSM.
40248: 02/03/03: rickman: Re: Embedding counting in an FSM.
40250: 02/03/03: Rick Filipkiewicz: Re: Embedding counting in an FSM.
40252: 02/03/03: Hal Murray: Re: Embedding counting in an FSM.
40253: 02/03/03: Rick Filipkiewicz: Re: Embedding counting in an FSM.
40227: 02/03/02: Vladimir Ralev: turnaround cycle?
40231: 02/03/02: Kevin Brace: Re: turnaround cycle?
40238: 02/03/03: Vladimir Ralev: Re: turnaround cycle?
40242: 02/03/03: Rick Filipkiewicz: Re: turnaround cycle?
40255: 02/03/03: Kevin Brace: Re: turnaround cycle?
40228: 02/03/02: Ray Andraka: Re: What FPGA to use?
40290: 02/03/04: Jay: Re: What FPGA to use?
40314: 02/03/05: Remco Poelstra: Re: What FPGA to use?
40330: 02/03/05: Ray Andraka: Re: What FPGA to use?
40229: 02/03/02: Remco Poelstra: What FPGA to use?
40233: 02/03/02: Mike Treseler: Re: What FPGA to use?
40234: 02/03/02: Paul: Re: What FPGA to use?
40278: 02/03/04: John_H: Re: What FPGA to use?
40236: 02/03/02: Al Williams: Xilinx WebPack Simulation
40243: 02/03/03: Rick Filipkiewicz: Re: Xilinx WebPack Simulation
40258: 02/03/03: Al Williams: Re: Xilinx WebPack Simulation
40237: 02/03/03: Yunhsianghsu: Xilinx MXE 5.5 v.s. ModelSim PE for Xilinx Spartan II only
40256: 02/03/03: Kevin Brace: Re: Xilinx MXE 5.5 v.s. ModelSim PE for Xilinx Spartan II only
40244: 02/03/03: Daniel Yap: thank you friends
40254: 02/03/03: Ray Morales: max3000a odd behavior -- is the bug in my vhdl code? help!
40257: 02/03/04: Jim Granville: Re: max3000a odd behavior -- is the bug in my vhdl code? help!
40271: 02/03/04: Ray Morales: Re: max3000a odd behavior -- is the bug in my vhdl code? help!
40285: 02/03/04: Ray Morales: Re: max3000a odd behavior -- is the bug in my vhdl code? help!
40287: 02/03/05: Jim Granville: Re: max3000a odd behavior -- is the bug in my vhdl code? help!
40281: 02/03/04: Mike Treseler: Re: max3000a odd behavior -- is the bug in my vhdl code? help!
40259: 02/03/04: Kevin Brace: Has anyone got Quartus II 2.0/LeonardoSpectrum-Altera NativeLink to work
40262: 02/03/04: Paul: Re: Has anyone got Quartus II 2.0/LeonardoSpectrum-Altera NativeLink to work correctly?
40282: 02/03/04: Mike Treseler: Re: Has anyone got Quartus II 2.0/LeonardoSpectrum-Altera NativeLink to
40312: 02/03/05: Russell Shaw: Re: Has anyone got Quartus II 2.0/LeonardoSpectrum-Altera NativeLink to
40332: 02/03/05: Mike Treseler: Re: Has anyone got Quartus II 2.0/LeonardoSpectrum-Altera NativeLink to
40342: 02/03/05: Kevin Brace: Re: Has anyone got Quartus II 2.0/LeonardoSpectrum-Altera NativeLink to
40260: 02/03/03: Antonio: Constraining help required for clk_enable
40263: 02/03/04: David Hawke: Re: Constraining help required for clk_enable
40284: 02/03/04: Falk Brunner: Re: Constraining help required for clk_enable
40292: 02/03/05: Philip Freidin: Re: Constraining help required for clk_enable
40308: 02/03/05: David Hawke: Re: Constraining help required for clk_enable
40315: 02/03/05: Magnus Homann: Re: Constraining help required for clk_enable
40261: 02/03/03: Antonio: Other 2 constraining how to questions
40264: 02/03/04: David Hawke: Re: Other 2 constraining how to questions
40266: 02/03/04: Leon Qin: Is there a ver 7.1 of Sunplify?
40385: 02/03/06: S Ramirez: Re: Is there a ver 7.1 of Sunplify?
40459: 02/03/07: Bob Efram: Re: Is there a ver 7.1 of Sunplify?
40268: 02/03/04: Jarek: Atmel back annotation problems
40269: 02/03/04: satya: Asynchronous boundaries in FPGA
40283: 02/03/04: Peter Alfke: Re: Asynchronous boundaries in FPGA
40286: 02/03/04: Falk Brunner: Re: Asynchronous boundaries in FPGA
40306: 02/03/05: Ken Mac: Re: Asynchronous boundaries in FPGA
40376: 02/03/06: satya: Re: Asynchronous boundaries in FPGA
40270: 02/03/04: Giulio Ferro: quest for info
40275: 02/03/04: Ken Mac: phantom timing constraints in ISE 4.1
40280: 02/03/04: John_H: Re: phantom timing constraints in ISE 4.1
40309: 02/03/05: Ken Mac: Re: phantom timing constraints in ISE 4.1
40277: 02/03/04: Paul Butler: Minimum Size and Logic Sharing
40297: 02/03/04: Xilinx FAE from Insight SANKET: Re: Minimum Size and Logic Sharing
40300: 02/03/05: Ray Andraka: Re: Minimum Size and Logic Sharing
40288: 02/03/04: Chinmay: can "initial signal values" and other "for.....use" statements damage fpgas?
40291: 02/03/04: Rick Filipkiewicz: Re: can "initial signal values" and other "for.....use" statements
40294: 02/03/05: Kris Nichols: Xilinx EDA support for run-time reconfiguration
40577: 02/03/11: Ian Robertson: Re: Xilinx EDA support for run-time reconfiguration
40295: 02/03/04: ssy: convert_hex2ver can not generate the *.ver file
40299: 02/03/04: Mike Treseler: Re: convert_hex2ver can not generate the *.ver file
40298: 02/03/04: praveen: Converting VHDL netlist to EDN/EDF/XNF
40303: 02/03/05: Thomas Stanka: Re: Converting VHDL netlist to EDN/EDF/XNF
40325: 02/03/05: Praveen: Re: Converting VHDL netlist to EDN/EDF/XNF
40301: 02/03/05: Rob Finch: Clock dividing
40302: 02/03/04: Albert: Need Help
40337: 02/03/05: John_H: Re: Need Help
40304: 02/03/05: David de Andrés: Synthesizing with CORE Generator
40305: 02/03/05: Rick Filipkiewicz: Re: Synthesizing with CORE Generator
40321: 02/03/05: David de Andrés: Re: Synthesizing with CORE Generator
40311: 02/03/05: Paul: FPGA problems
40334: 02/03/05: Mike Treseler: Re: FPGA problems
40344: 02/03/05: Jay: Re: FPGA problems
40400: 02/03/06: Paul: Re: FPGA problems
40443: 02/03/07: Paul: Re: FPGA problems
40316: 02/03/05: Young-Su Kwon: Writing Synosys library for FPGA using LUT.
40357: 02/03/05: Muzaffer Kal: Re: Writing Synosys library for FPGA using LUT.
40317: 02/03/05: Matthias Wenzel: Array case expression must have a static subtype (VHDL)
40323: 02/03/05: Alan Fitch: Re: Array case expression must have a static subtype (VHDL)
40318: 02/03/05: M Schreiber: exceeding 2GB limits in xilinx
40322: 02/03/05: Austin Lesea: Re: exceeding 2GB limits in xilinx
40335: 02/03/05: Austin Lesea: Re: exceeding 2GB limits in xilinx
40354: 02/03/05: <istjohn@spamcop.net>: Re: exceeding 2GB limits in xilinx
40380: 02/03/06: Erwin Rol: Re: exceeding 2GB limits in xilinx
40384: 02/03/06: <hamish@cloud.net.au>: Re: exceeding 2GB limits in xilinx
40324: 02/03/05: emanuel stiebler: Re: exceeding 2GB limits in xilinx
40333: 02/03/05: Jay: Re: exceeding 2GB limits in xilinx
40339: 02/03/05: Ray Andraka: Re: exceeding 2GB limits in xilinx
40364: 02/03/05: Assaf Sarfati: Re: exceeding 2GB limits in xilinx
40365: 02/03/06: Nicholas Weaver: Re: exceeding 2GB limits in xilinx
40368: 02/03/06: Muzaffer Kal: Re: exceeding 2GB limits in xilinx
40370: 02/03/06: Lars Rzymianowicz: Re: exceeding 2GB limits in xilinx
40410: 02/03/06: Nicholas Weaver: Re: exceeding 2GB limits in xilinx
40426: 02/03/07: Peter Ormsby: Re: exceeding 2GB limits in xilinx
40435: 02/03/07: Petter Gustad: Re: exceeding 2GB limits in xilinx
40442: 02/03/07: Nial Stewart: Re: exceeding 2GB limits in xilinx
40476: 02/03/07: Petter Gustad: Re: exceeding 2GB limits in xilinx
40494: 02/03/08: Tim: Re: exceeding 2GB limits in xilinx
40519: 02/03/08: Petter Gustad: Re: exceeding 2GB limits in xilinx
40529: 02/03/08: Ray Andraka: Re: exceeding 2GB limits in xilinx
40532: 02/03/08: B. Joshua Rosen: Re: exceeding 2GB limits in xilinx
40533: 02/03/09: bob elkind: Re: exceeding 2GB limits in xilinx
40542: 02/03/09: Petter Gustad: Re: exceeding 2GB limits in xilinx
40544: 02/03/09: B. Joshua Rosen: Re: exceeding 2GB limits in xilinx
40552: 02/03/09: Petter Gustad: Re: exceeding 2GB limits in xilinx
40557: 02/03/10: <hamish@cloud.net.au>: Re: exceeding 2GB limits in xilinx
40574: 02/03/11: Erwin Rol: Re: exceeding 2GB limits in xilinx
40586: 02/03/11: Petter Gustad: Re: exceeding 2GB limits in xilinx
40639: 02/03/12: Erwin Rol: Re: exceeding 2GB limits in xilinx
40662: 02/03/12: Duane Clark: Re: exceeding 2GB limits in xilinx
40666: 02/03/12: Petter Gustad: Re: exceeding 2GB limits in xilinx
40787: 02/03/15: Peter Dudley: Re: exceeding 2GB limits in xilinx
40526: 02/03/08: glen herrmannsfeldt: Re: exceeding 2GB limits in xilinx
40386: 02/03/06: Johann Glaser: Re: exceeding 2GB limits in xilinx
40391: 02/03/06: Ray Andraka: Re: exceeding 2GB limits in xilinx
40406: 02/03/06: Rick Filipkiewicz: Re: exceeding 2GB limits in xilinx
40438: 02/03/07: <hamish@cloud.net.au>: Re: exceeding 2GB limits in xilinx
40428: 02/03/07: Allan Herriman: Re: exceeding 2GB limits in xilinx
40429: 02/03/07: Nicholas Weaver: Re: exceeding 2GB limits in xilinx
40450: 02/03/07: Tim: Re: exceeding 2GB limits in xilinx
40497: 02/03/08: Allan Herriman: Re: exceeding 2GB limits in xilinx
40541: 02/03/09: Rick Filipkiewicz: Re: exceeding 2GB limits in xilinx
40546: 02/03/09: Ray Andraka: Re: exceeding 2GB limits in xilinx
40640: 02/03/12: Allan Herriman: Re: exceeding 2GB limits in xilinx
40652: 02/03/12: Ray Andraka: Re: exceeding 2GB limits in xilinx
40436: 02/03/07: Petter Gustad: Re: exceeding 2GB limits in xilinx
40523: 02/03/08: Jay: Re: exceeding 2GB limits in xilinx
40374: 02/03/06: Alan Fitch: Re: exceeding 2GB limits in xilinx
40392: 02/03/06: Petter Gustad: Re: exceeding 2GB limits in xilinx
40320: 02/03/05: Guy Eschemann: digital video PLL
40327: 02/03/05: Jay: Re: digital video PLL
40328: 02/03/05: Falk Brunner: Re: digital video PLL
40343: 02/03/05: Guy Eschemann: Re: digital video PLL
40345: 02/03/06: Jim Granville: Re: digital video PLL
40347: 02/03/05: Austin Lesea: Re: digital video PLL
40349: 02/03/05: John_H: Re: digital video PLL
40350: 02/03/05: Austin Lesea: Re: digital video PLL
40331: 02/03/05: Austin Lesea: Re: digital video PLL
40336: 02/03/05: John_H: Re: digital video PLL
40717: 02/03/13: Frank Vorstenbosch: Re: digital video PLL
40718: 02/03/13: John_H: Re: digital video PLL
40719: 02/03/13: Frank Vorstenbosch: Re: digital video PLL
40724: 02/03/14: John_H: Re: digital video PLL
40563: 02/03/10: Christopher Holmes: Re: digital video PLL
40338: 02/03/05: VhdlCohen: From Verif. Guild: Challenging the need for HVLs
40346: 02/03/05: Jan Gray: Xilinx announces Virtex-II Pro is shipping
40366: 02/03/06: rickman: Re: Xilinx announces Virtex-II Pro is shipping
40367: 02/03/06: Nicholas Weaver: Re: Xilinx announces Virtex-II Pro is shipping
40377: 02/03/06: Rick Filipkiewicz: Re: Xilinx announces Virtex-II Pro is shipping
40396: 02/03/06: Austin Lesea: Re: Xilinx announces Virtex-II Pro is shipping
40393: 02/03/06: Ray Andraka: Re: Xilinx announces Virtex-II Pro is shipping
40348: 02/03/05: Kevin Brace: Quartus II 2.0 fast fit option
40358: 02/03/06: Peter Ormsby: Re: Quartus II 2.0 fast fit option
40362: 02/03/05: Kevin Brace: Re: Quartus II 2.0 fast fit option
40378: 02/03/06: Nial Stewart: Re: Quartus II 2.0 fast fit option
40479: 02/03/07: Kevin Brace: Re: Quartus II 2.0 fast fit option
40483: 02/03/07: Ray Andraka: Re: Quartus II 2.0 fast fit option
40509: 02/03/08: Nial Stewart: Re: Quartus II 2.0 fast fit option
40422: 02/03/07: Russell Shaw: Re: Quartus II 2.0 fast fit option
40480: 02/03/07: Kevin Brace: Re: Quartus II 2.0 fast fit option
40495: 02/03/08: Russell Shaw: Re: Quartus II 2.0 fast fit option
40427: 02/03/07: Terry: Re: Quartus II 2.0 fast fit option
40473: 02/03/07: bob elkind: Re: Quartus II 2.0 fast fit option
40355: 02/03/05: Guillaume: FPGA exp with "timing constraint export"
40359: 02/03/05: Michol: Re: FPGA exp with "timing constraint export"
40356: 02/03/05: Steven Nowick: 2nd Call for Papers: IWLS-02 - IEEE/ACM Int. Wkshp. on Logic &
40360: 02/03/05: ssy: possible problem of asyn read of block ram in apex 20k device
40363: 02/03/05: duy: Block Ram
40395: 02/03/06: Matthias Scheerer: Re: Block Ram
40846: 02/03/16: Edwin Bland: Re: Block Ram
40407: 02/03/06: Peter Alfke: Re: FPGA wich supports LVDS
40580: 02/03/11: lsuser: Re: FPGA wich supports LVDS
40581: 02/03/11: Austin Lesea: Re: FPGA which supports LVDS
40588: 02/03/11: lsuser: Re: FPGA wich supports LVDS
40589: 02/03/11: Peter Alfke: Re: FPGA wich supports LVDS
40595: 02/03/11: lsuser: Re: FPGA wich supports LVDS
40597: 02/03/11: Theron Hicks: Re: FPGA wich supports LVDS
40601: 02/03/11: Austin Lesea: Re: FPGA wich supports LVDS
40617: 02/03/12: Philip Freidin: Re: FPGA wich supports LVDS
40621: 02/03/11: Austin Lesea: Re: FPGA wich supports LVDS
40602: 02/03/11: lsuser: Re: FPGA wich supports LVDS
40371: 02/03/06: <msauer@gmx.net>: FPGA which supports LVDS
40412: 02/03/06: Tom Burgess: Re: FPGA which supports LVDS
40373: 02/03/06: g. giachella: QPRO Virtex
40408: 02/03/06: Peter Alfke: Re: QPRO Virtex
40415: 02/03/06: Kevin Brace: Re: QPRO Virtex
40375: 02/03/06: F. Modderkolk: FPGA or DSP
40379: 02/03/06: Allan Herriman: Re: FPGA or DSP
40389: 02/03/06: Ray Andraka: Re: FPGA or DSP
40381: 02/03/06: F. Modderkolk: FPGA or DSP in a power supply?
40383: 02/03/06: Paul: Re: FPGA or DSP in a power supply?
40394: 02/03/06: F. Modderkolk: Re: FPGA or DSP in a power supply?
40409: 02/03/06: Peter Alfke: Re: FPGA or DSP in a power supply?
40413: 02/03/07: Jim Granville: Re: FPGA or DSP in a power supply?
40521: 02/03/08: Santiago de Pablo: Re: FPGA or DSP in a power supply?
40388: 02/03/06: Allan Herriman: Re: FPGA or DSP in a power supply?
40390: 02/03/06: Ray Andraka: Re: FPGA or DSP in a power supply?
40433: 02/03/07: F. Modderkolk: Re: FPGA or DSP in a power supply?
40437: 02/03/07: Jim Granville: Re: FPGA or DSP in a power supply?
40446: 02/03/07: Ray Andraka: Re: FPGA or DSP in a power supply?
40510: 02/03/08: F. Modderkolk: Re: FPGA or DSP in a power supply?
40511: 02/03/08: Paul: Re: FPGA or DSP in a power supply?
40512: 02/03/08: Ray Andraka: Re: FPGA or DSP in a power supply?
40514: 02/03/08: Peter Alfke: Re: FPGA or DSP in a power supply?
40515: 02/03/08: Ray Andraka: Re: FPGA or DSP in a power supply?
40452: 02/03/07: Peter Alfke: Re: FPGA or DSP in a power supply?
40520: 02/03/08: F. Modderkolk: Re: FPGA or DSP in a power supply?
40525: 02/03/08: Peter Alfke: Re: FPGA or DSP in a power supply?
40576: 02/03/11: F. Modderkolk: Re: FPGA or DSP in a power supply?
40382: 02/03/06: Martin Thompson: V-II DCM options
40397: 02/03/06: Austin Lesea: Re: V-II DCM options
40401: 02/03/06: Martin Thompson: Re: V-II DCM options
40472: 02/03/07: Jay: Re: V-II DCM options
40387: 02/03/06: Roberto Capobianco: Fast transmission
40418: 02/03/06: Peter Alfke: Re: Fast transmission
40447: 02/03/07: Roberto Capobianco: Re: Fast transmission
40470: 02/03/07: Jay: Re: Fast transmission
40398: 02/03/06: Kenny: MXE 5.5e speed
40419: 02/03/06: Cindy: Re: MXE 5.5e speed
40467: 02/03/07: Kamal: Re: MXE 5.5e speed
40399: 02/03/06: Kenny: How to create testbench (Verilog) easily ? Any tools ?
40417: 02/03/06: VhdlCohen: Re: How to create testbench (Verilog) easily ? Any tools ?
40402: 02/03/06: ICCAD Conference: ICCAD 2002 Call for Papers
40403: 02/03/06: Nahum Barnea: max frequency of obuf_lvdci_dv2_18
40455: 02/03/07: Austin Lesea: Re: max frequency of obuf_lvdci_dv2_18
40693: 02/03/12: Eric Smith: IBIS simulation (was Re: max frequency of obuf_lvdci_dv2_18)
40696: 02/03/12: Bob Perlman: Re: IBIS simulation (was Re: max frequency of obuf_lvdci_dv2_18)
40709: 02/03/13: Austin Lesea: Re: IBIS simulation (was Re: max frequency of obuf_lvdci_dv2_18)
40710: 02/03/13: Austin Lesea: Re: IBIS simulation (was Re: max frequency of obuf_lvdci_dv2_18)
40404: 02/03/06: Chris Cowdery: Using a battery instead of Config device
40425: 02/03/07: Peter Alfke: Re: Using a battery instead of Config device
40469: 02/03/07: Jay: Re: Using a battery instead of Config device
40411: 02/03/06: Greg Neff: Mutual Clock Synchronization
40414: 02/03/06: John_H: Re: Mutual Clock Synchronization
40420: 02/03/06: Greg Neff: Re: Mutual Clock Synchronization
40421: 02/03/06: John_H: Re: Mutual Clock Synchronization
40465: 02/03/07: Greg Neff: Re: Mutual Clock Synchronization
40466: 02/03/07: John_H: Re: Mutual Clock Synchronization
40430: 02/03/07: Allan Herriman: Re: Mutual Clock Synchronization
40468: 02/03/07: Greg Neff: Re: Mutual Clock Synchronization
40475: 02/03/07: John_H: Re: Mutual Clock Synchronization
40694: 02/03/12: showbiz: Re: Mutual Clock Synchronization
40703: 02/03/13: Allan Herriman: Re: Mutual Clock Synchronization
40536: 02/03/08: bala iyer: Re: Mutual Clock Synchronization
40416: 02/03/06: Cindy: Virtex-II : Temperature Sensing Diodes
40456: 02/03/07: Austin Lesea: Re: Virtex-II : Temperature Sensing Diodes
40471: 02/03/07: Jay: Re: Virtex-II : Temperature Sensing Diodes
40474: 02/03/07: Austin Lesea: Re: Virtex-II : Temperature Sensing Diodes
40765: 02/03/14: Jon Elson: Re: Virtex-II : Temperature Sensing Diodes
40767: 02/03/14: Austin Lesea: Re: Virtex-II : Temperature Sensing Diodes
40423: 02/03/07: Nicholas Weaver: Announcement: Freely Available Rijndael Core for Virtex FPGAs.
40431: 02/03/06: ssy: high active and low active reset signal mixed in a design
40432: 02/03/07: Jim Granville: Re: high active and low active reset signal mixed in a design
40440: 02/03/07: ssy: Re: high active and low active reset signal mixed in a design
40445: 02/03/07: Phil Connor: Re: high active and low active reset signal mixed in a design
40449: 02/03/07: Muzaffer Kal: Re: high active and low active reset signal mixed in a design
40505: 02/03/08: ssy: Re: high active and low active reset signal mixed in a design
40543: 02/03/09: Rick Filipkiewicz: Re: high active and low active reset signal mixed in a design
40623: 02/03/11: Jay: Re: high active and low active reset signal mixed in a design
40697: 02/03/13: H.L: Re: high active and low active reset signal mixed in a design
40764: 02/03/14: Jon Elson: Re: high active and low active reset signal mixed in a design
40434: 02/03/07: sdfg: pipeline
40439: 02/03/07: MegaPowerStar: DPRAM implementation in altera
40558: 02/03/10: giga_super_man: Re: DPRAM implementation in altera
40673: 02/03/12: arpit.desai: Re: DPRAM implementation in altera
40680: 02/03/12: Mike Treseler: Re: DPRAM implementation in altera
40441: 02/03/07: David Brown: Converting old Mach 5 project from DSL to VHDL
40490: 02/03/08: Mikeandmax: Re: Converting old Mach 5 project from DSL to VHDL
40493: 02/03/08: Jim Granville: Re: Converting old Mach 5 project from DSL to VHDL
40506: 02/03/08: David Brown: Re: Converting old Mach 5 project from DSL to VHDL
40444: 02/03/07: dano: How can I install Xilinx ISE 4.1i under Linux?
40481: 02/03/07: Andy Main: Re: How can I install Xilinx ISE 4.1i under Linux?
40488: 02/03/08: dano: Re: How can I install Xilinx ISE 4.1i under Linux?
40482: 02/03/07: newman: Re: How can I install Xilinx ISE 4.1i under Linux?
40496: 02/03/08: Peter Ormsby: Re: How can I install Xilinx ISE 4.1i under Linux?
40559: 02/03/10: Utku Ozcan: Re: How can I install Xilinx ISE 4.1i under Linux?
40763: 02/03/14: Jon Elson: Re: How can I install Xilinx ISE 4.1i under Linux?
40451: 02/03/07: Salman Sheikh: Xilinx ISE 4.1
40463: 02/03/07: Falk Brunner: Re: Xilinx ISE 4.1
40498: 02/03/07: Xilinx FAE from Insight SANKET: Re: Xilinx ISE 4.1
40491: 02/03/08: Russell Shaw: Re: Xilinx ISE 4.1
40550: 02/03/09: Utku Ozcan: Re: Xilinx ISE 4.1
40551: 02/03/09: Utku Ozcan: Re: Xilinx ISE 4.1
40453: 02/03/07: Michael Amling: Re: Announcement: Freely available AES/Rijndael Core in Virtex FPGAs
40454: 02/03/07: Flip Flippy: Re: Announcement: Freely available AES/Rijndael Core in Virtex FPGAs
40458: 02/03/07: Kenny: Ports disappear after generating post place and route simulation model
40464: 02/03/07: Brian Philofsky: Re: Ports disappear after generating post place and route simulation
40461: 02/03/07: Joseph H Allen: Need XC2V4000/6000-4FF1152CES
40477: 02/03/07: Zak smith: Clamping Diode in the I/O !!!
40484: 02/03/07: Jay: Re: Clamping Diode in the I/O !!!
40485: 02/03/07: Austin Lesea: Re: Clamping Diode in the I/O !!!
40489: 02/03/08: Mikeandmax: Re: Clamping Diode in the I/O !!!
40478: 02/03/07: Niv: CLKDLL in Virtex
40487: 02/03/07: Peter Alfke: Re: CLKDLL in Virtex
40486: 02/03/07: Jon Schneider: Webpack/SpartanII maplib:93 error
40499: 02/03/07: MegaPowerStar: Re: Webpack/SpartanII maplib:93 error
40502: 02/03/08: Jon Schneider: Re: Webpack/SpartanII maplib:93 error
40500: 02/03/08: Peter Waldeck: Error in Foundation 4.1i
40762: 02/03/14: Jon Elson: Re: Error in Foundation 4.1i
40501: 02/03/07: dan doberstein: GATE ARRAY PROJECT
40516: 02/03/08: John_H: Re: GATE ARRAY PROJECT
40518: 02/03/08: Peter Alfke: Re: GATE ARRAY PROJECT
40503: 02/03/07: Peter Rauschert: Xilinx 32 Point FFT for post synthesis simulation ?
40504: 02/03/08: ssy: a simulation question about apex20ke_asynch_lcell
40507: 02/03/08: Nahum Barnea: suggestion to comp.arch.fpga
40513: 02/03/08: S Ramirez: Re: suggestion to comp.arch.fpga
40517: 02/03/08: VhdlCohen: Re: suggestion to comp.arch.fpga
40508: 02/03/08: sboe: hash arithmetic
40522: 02/03/08: Ryan Henderson: Sandwich board at ESC
40527: 02/03/08: S. Ramirez: Re: Sandwich board at ESC
40531: 02/03/08: Jay: Re: Sandwich board at ESC
40584: 02/03/11: James Horn: Re: Sandwich board at ESC
40530: 02/03/09: Hristo Stevic: Logic levels
40547: 02/03/09: Hristo Stevic: Re: Logic levels
40603: 02/03/11: John_H: Re: Logic levels
40534: 02/03/08: skldfb: BlockRam
40537: 02/03/09: Peter Alfke: Re: BlockRam
40538: 02/03/08: skldfb: Re: BlockRam
40540: 02/03/09: Ray Andraka: Re: BlockRam
40539: 02/03/08: skldfb: Re: BlockRam
40545: 02/03/09: Ray Andraka: Re: BlockRam
40535: 02/03/09: Tim: Xilinx Download Cable Connectors
40549: 02/03/09: Jeff Stout: Re: Xilinx Download Cable Connectors
40561: 02/03/10: Jim Kearney: Re: Xilinx Download Cable Connectors
40600: 02/03/11: rickman: Re: Xilinx Download Cable Connectors
40609: 02/03/11: In Memory of tecNovia: Re: Xilinx Download Cable Connectors
40611: 02/03/11: Jim Kearney: Re: Xilinx Download Cable Connectors
40616: 02/03/11: Tim: Re: Xilinx Download Cable Connectors
40548: 02/03/09: Jon Schneider: Instantiating BUFGSR goes tits up
40553: 02/03/10: Flora Cathy: 32-taps FIR !
40645: 02/03/12: Alan McKitterick: Re: 32-taps FIR !
40665: 02/03/12: Jacky Renaux: Re: 32-taps FIR !
40766: 02/03/14: Philippe: Re: 32-taps FIR !
40554: 02/03/09: David Lamb: Audio project with an FPGA?
40555: 02/03/10: Loi Tran: Re: Audio project with an FPGA?
40560: 02/03/10: Joey Nelson: Re: Audio project with an FPGA?
40568: 02/03/11: Andy Main: Re: Audio project with an FPGA?
40573: 02/03/11: Wolfgang Loewer: Re: Audio project with an FPGA?
40556: 02/03/09: Anbarasu: FPGA Synthesis ...new methodology
40562: 02/03/11: Mark: How to Align 7x DDR Data Input to a XC2V6000-5?
40585: 02/03/11: John_H: Re: How to Align 7x DDR Data Input to a XC2V6000-5?
40637: 02/03/12: Mark: Re: How to Align 7x DDR Data Input to a XC2V6000-5?
40664: 02/03/12: John_H: Re: How to Align 7x DDR Data Input to a XC2V6000-5?
40698: 02/03/13: Mark: Re: How to Align 7x DDR Data Input to a XC2V6000-5?
40714: 02/03/13: John_H: Re: How to Align 7x DDR Data Input to a XC2V6000-5?
40727: 02/03/14: Mark: Re: How to Align 7x DDR Data Input to a XC2V6000-5?
40564: 02/03/11: rickman: Spartan II E output voltage characteristics
40578: 02/03/11: Peter Alfke: Re: Spartan II E output voltage characteristics
40579: 02/03/11: Austin Lesea: Re: Spartan II E output voltage characteristics
40599: 02/03/11: rickman: Re: Spartan II E output voltage characteristics
40604: 02/03/11: Austin Lesea: Re: Spartan II E output voltage characteristics
40606: 02/03/11: Peter Alfke: Re: Spartan II E output voltage characteristics
40630: 02/03/12: rickman: Re: Spartan II E output voltage characteristics
40565: 02/03/10: Antonio: First steps with clock enable constraining
40583: 02/03/11: Peter Alfke: Re: First steps with clock enable constraining
40626: 02/03/12: Paul Taylor: Re: First steps with clock enable constraining
40566: 02/03/10: Antonio: floating pins
40610: 02/03/11: lsuser: Re: floating pins
40615: 02/03/11: Tim: Re: floating pins
40628: 02/03/11: Jonas Thor: Re: floating pins
40624: 02/03/11: Jay: Re: floating pins
40636: 02/03/11: Antonio: Re: floating pins
40653: 02/03/12: Ray Andraka: Re: floating pins
40669: 02/03/12: Jay: Re: floating pins
40567: 02/03/10: Antonio: MPPR question
40658: 02/03/12: Antonio: Re: MPPR question
40569: 02/03/11: Peter Rauschert: Cannot access header information - Modelsim Error with XilinxCoreLib ?
40570: 02/03/11: AT: JTAG & CPLD
40571: 02/03/11: X. Q.: MP3 decoder.
40591: 02/03/11: Falk Brunner: Re: MP3 decoder.
40572: 02/03/11: Utku Ozcan: promgen: unused area in with different values produce same checksum
40575: 02/03/11: David Brown: Newbie choosing a language - Verilog, VHDL, or ABEL
40587: 02/03/12: Jim Granville: Re: Newbie choosing a language - Verilog, VHDL, or ABEL
40605: 02/03/11: VhdlCohen: Re: Newbie choosing a language - Verilog, VHDL, or ABEL
40590: 02/03/11: Mike Treseler: Re: Newbie choosing a language - Verilog, VHDL, or ABEL
40592: 02/03/11: Falk Brunner: Re: Newbie choosing a language - Verilog, VHDL, or ABEL
40612: 02/03/11: Jay: Re: Newbie choosing a language - Verilog, VHDL, or ABEL
40638: 02/03/12: David Brown: Re: Newbie choosing a language - Verilog, VHDL, or ABEL
40667: 02/03/12: Mike Treseler: Re: Newbie choosing a language - Verilog, VHDL, or ABEL
40759: 02/03/14: Larry McKeogh: Re: Newbie choosing a language - Verilog, VHDL, or ABEL
40761: 02/03/15: Jim Granville: Re: Newbie choosing a language - Verilog, VHDL, or ABEL/CUPL
40582: 02/03/11: Sasa Bremec: SPI interface
40593: 02/03/11: Falk Brunner: Re: SPI interface
40598: 02/03/11: Theron Hicks: Re: SPI interface
40629: 02/03/12: Prasanth Kumar: Re: SPI interface
40594: 02/03/11: Theron Hicks: spartan2e startup module not being expanded
40620: 02/03/12: Georg Acher: Re: spartan2e startup module not being expanded
40596: 02/03/11: Theron Hicks: Has anyone used the LVDS or LVPECL I/O on spartan2e?
40607: 02/03/11: xchecker: FPGA download fails
40608: 02/03/11: Mark: Re: FPGA download fails
40644: 02/03/12: Neeraj: Re: FPGA download fails
40614: 02/03/11: Tim: Re: FPGA download fails
40641: 02/03/12: David Hawke: Re: FPGA download fails
40618: 02/03/11: Austin Franklin: Article in March Embedded Systems - "The Death of Hardware Engineering"...
40619: 02/03/12: Phil Hays: Re: Article in March Embedded Systems - "The Death of Hardware
40622: 02/03/12: Ray Andraka: Re: Article in March Embedded Systems - "The Death of Hardware
40627: 02/03/12: S. Ramirez: Re: Article in March Embedded Systems - "The Death of Hardware Engineering"...
40670: 02/03/12: Kevin Neilson: Re: Article in March Embedded Systems - "The Death of Hardware Engineering"...
40671: 02/03/12: S. Ramirez: Re: Article in March Embedded Systems - "The Death of Hardware Engineering"...
40674: 02/03/12: Nicholas Weaver: Re: Article in March Embedded Systems - "The Death of Hardware Engineering"...
40677: 02/03/12: Ray Andraka: Re: Article in March Embedded Systems - "The Death of Hardware
40683: 02/03/12: Ray Andraka: Re: Article in March Embedded Systems - "The Death of Hardware
40625: 02/03/11: wiy: a guide to digital design and synthesis
40632: 02/03/12: VhdlCohen: Re: a guide to digital design and synthesis
40649: 02/03/12: skdjf: Re: a guide to digital design and synthesis
40631: 02/03/12: rickman: Mystery two wire interface, or am I being dense?
40633: 02/03/12: Keith Brafford: Re: Mystery two wire interface, or am I being dense?
40685: 02/03/13: Rick Filipkiewicz: Re: Mystery two wire interface, or am I being dense?
40687: 02/03/13: Keith Brafford: Re: Mystery two wire interface, or am I being dense?
40634: 02/03/12: Jonathan Kirwan: Re: Mystery two wire interface, or am I being dense?
40635: 02/03/12: Jim Granville: Re: Mystery two wire interface, or am I being dense?
40643: 02/03/12: Phil Connor: Re: Mystery two wire interface, or am I being dense?
40648: 02/03/12: Christopher Saunter: Re: Mystery two wire interface, or am I being dense?
40650: 02/03/12: Allan Herriman: Re: Mystery two wire interface, or am I being dense?
40686: 02/03/13: michael brown: Re: Mystery two wire interface, or am I being dense?
40689: 02/03/13: Ray Andraka: Re: Mystery two wire interface, or am I being dense?
40691: 02/03/13: michael brown: Re: Mystery two wire interface, or am I being dense?
40701: 02/03/13: Tauno Voipio: Re: Mystery two wire interface, or am I being dense?
40651: 02/03/12: Jan Martin: Re: Mystery two wire interface, or am I being dense?
40656: 02/03/12: rickman: Re: Mystery two wire interface, or am I being dense?
40661: 02/03/12: Ned Konz: Re: Mystery two wire interface, or am I being dense?
40681: 02/03/12: Mark A. Odell: Re: Mystery two wire interface, or am I being dense?
40642: 02/03/12: Leon Qin: Where can I get a Ebbok <Writting Testbench>>
40647: 02/03/12: rg: Re: RTL/Gate-Level Simulation
40654: 02/03/12: Ray Andraka: Re: RTL/Gate-Level Simulation
40655: 02/03/12: Muthu: powerpc in virtex2pro
40660: 02/03/12: Peter Alfke: Re: powerpc in virtex2pro
40800: 02/03/15: Tim: Re: powerpc in virtex2pro
41486: 02/03/29: Cyrille de Brébisson: Re: powerpc in virtex2pro
41491: 02/03/30: Peter Alfke: Re: powerpc in virtex2pro
41520: 02/04/01: Ron Huizen: Re: powerpc in virtex2pro
41525: 02/04/01: Peter Alfke: Re: powerpc in virtex2pro
41568: 02/04/02: Jan Gray: Re: powerpc in virtex2pro
41583: 02/04/02: Austin Lesea: Re: powerpc in virtex2pro
41626: 02/04/03: jerry1111: Re: powerpc in virtex2pro
41627: 02/04/04: Jim Granville: Re: powerpc in virtex2pro
41628: 02/04/03: Austin Lesea: Re: powerpc in virtex2pro
41630: 02/04/03: Peter Alfke: Re: powerpc in virtex2pro
41631: 02/04/03: Jan Gray: Re: powerpc in virtex2pro
41632: 02/04/03: B. Joshua Rosen: Re: powerpc in virtex2pro
41633: 02/04/03: John_H: Re: powerpc in virtex2pro
41645: 02/04/04: Austin Lesea: Re: powerpc in virtex2pro
41657: 02/04/04: Falk Brunner: Re: powerpc in virtex2pro
41661: 02/04/04: Nicholas Weaver: Re: powerpc in virtex2pro
41658: 02/04/04: Nicholas Weaver: Re: powerpc in virtex2pro
41666: 02/04/04: Austin Lesea: Re: powerpc in virtex2pro
41668: 02/04/04: Nicholas Weaver: Re: powerpc in virtex2pro
41678: 02/04/05: Ray Andraka: Re: powerpc in virtex2pro
41663: 02/04/04: Peter Alfke: Re: powerpc in virtex2pro
41667: 02/04/04: Steve Casselman: Re: powerpc in virtex2pro
41670: 02/04/04: Nicholas Weaver: Re: powerpc in virtex2pro
41764: 02/04/07: Jan Gray: Re: powerpc in virtex2pro
41805: 02/04/08: Steve Casselman: Re: powerpc in virtex2pro
41675: 02/04/04: Kevin Brace: Re: powerpc in virtex2pro
41676: 02/04/04: Peter Alfke: Re: powerpc in virtex2pro
41655: 02/04/04: Falk Brunner: Re: powerpc in virtex2pro
41547: 02/04/01: Alan Calac: Re: powerpc in virtex2pro
41654: 02/04/04: Lasse Langwadt Christensen: Re: powerpc in virtex2pro
41659: 02/04/04: Nicholas Weaver: Re: powerpc in virtex2pro
41662: 02/04/04: Ken McElvain: Re: powerpc in virtex2pro
41496: 02/03/30: Keith R. Williams: Re: powerpc in virtex2pro
41535: 02/04/01: Rick Filipkiewicz: Re: powerpc in virtex2pro
41544: 02/04/02: Ray Andraka: Re: powerpc in virtex2pro
41554: 02/04/01: Keith R. Williams: Re: powerpc in virtex2pro
41498: 02/03/30: Kevin Brace: Re: powerpc in virtex2pro
41519: 02/04/01: Utku Ozcan: Re: powerpc in virtex2pro
40657: 02/03/12: Diping: Pins levels on Spartan.
40663: 02/03/12: John_H: Re: Pins levels on Spartan.
40659: 02/03/12: Timmestein: nOOb: wants to start using an fpga
40668: 02/03/12: Jay: Re: nOOb: wants to start using an fpga
40723: 02/03/13: Kevin Brace: Re: nOOb: wants to start using an fpga
40672: 02/03/12: drake: cyphers
40675: 02/03/12: Vikram Pasham: Re: cyphers
40676: 02/03/12: Andy Main: Re: cyphers
40678: 02/03/12: Nicholas Weaver: Re: cyphers
41438: 02/03/29: Wesley J. Landaker: Re: cyphers
40679: 02/03/12: Prashant: Timing Simulations
40682: 02/03/12: Mike Treseler: Re: Timing Simulations
40684: 02/03/12: Kevin Brace: How do I infer a carry-chain parity generator in XST?
40688: 02/03/13: Ray Andraka: Re: How do I infer a carry-chain parity generator in XST?
40692: 02/03/12: Kevin Brace: Re: How do I infer a carry-chain parity generator in XST?
40713: 02/03/13: John_H: Re: How do I infer a carry-chain parity generator in XST?
40690: 02/03/13: Kelvin Hsu: How would I know somebody has copied my files in Unix?
40702: 02/03/13: Timmestein: Re: How would I know somebody has copied my files in Unix?
40738: 02/03/14: e.i.chester: Re: How would I know somebody has copied my files in Unix?
40695: 02/03/13: Kelvin Hsu: How can I program into the EEPROM?
40699: 02/03/13: Zak smith: Pointer Processor for OC192
40707: 02/03/13: <hamish@cloud.net.au>: Re: Pointer Processor for OC192
40700: 02/03/13: Zak smith: Any data about SFI 4 interface ?
40704: 02/03/13: Michael Boehnel: Single-event upsets in ROM
40705: 02/03/13: Saurabh Pal: DES implementation in Handel C
40776: 02/03/15: John: Re: DES implementation in Handel C
40706: 02/03/13: sfjg: EDA tools(from front to end)
40708: 02/03/13: Arash Salarian: Synthesis tools comparison?
40722: 02/03/13: S. Ramirez: Re: Synthesis tools comparison?
40735: 02/03/14: Arash Salarian: Re: Synthesis tools comparison?
40739: 02/03/14: Mike Treseler: Re: Synthesis tools comparison?
40753: 02/03/14: Jay: Re: Synthesis tools comparison?
40736: 02/03/14: Tim: Re: Synthesis tools comparison?
40746: 02/03/14: S. Ramirez: Re: Synthesis tools comparison?
40711: 02/03/13: Prashant: IP cores availability
40712: 02/03/13: Nahum Barnea: minimum value for clock to output
40771: 02/03/15: Rick Filipkiewicz: Re: minimum value for clock to output
40866: 02/03/17: Nahum Barnea: Re: minimum value for clock to output
40868: 02/03/17: Rick Filipkiewicz: Re: minimum value for clock to output
40986: 02/03/19: Nahum Barnea: Re: minimum value for clock to output
40715: 02/03/13: Dionissis Efstathiou: Universal FPGA Programmer
40716: 02/03/13: Falk Brunner: Re: Universal FPGA Programmer
40799: 02/03/15: Tim: Re: Universal FPGA Programmer
40720: 02/03/13: Kevin Brace: Is XST's Keep Hierarchy option broken?
40721: 02/03/13: Kevin Brace: XST duplicates unnecessary IOB OE FFs
40743: 02/03/14: Brian Drummond: Re: XST duplicates unnecessary IOB OE FFs
40760: 02/03/14: Kevin Brace: Re: XST duplicates unnecessary IOB OE FFs
40836: 02/03/16: <hamish@cloud.net.au>: Re: XST duplicates unnecessary IOB OE FFs
40849: 02/03/16: Kevin Brace: Re: XST duplicates unnecessary IOB OE FFs
40870: 02/03/17: <hamish@cloud.net.au>: Re: XST duplicates unnecessary IOB OE FFs
40964: 02/03/19: Kevin Brace: Re: XST duplicates unnecessary IOB OE FFs
41340: 02/03/26: <hamish@cloud.net.au>: Re: XST duplicates unnecessary IOB OE FFs
41423: 02/03/27: Kevin Brace: Re: XST duplicates unnecessary IOB OE FFs
40725: 02/03/13: Sniper Daryl: the server to access to this newgroup
40775: 02/03/15: Topo Gigio: Re: the server to access to this newgroup
41048: 02/03/20: piaoliuren: Re: the server to access to this newgroup
40726: 02/03/14: Martin Sauer: Difference between Virtex-II(E) und Virtex-E
40741: 02/03/14: Austin Lesea: Re: Difference between Virtex-II(E) und Virtex-E
40749: 02/03/14: Falk Brunner: Re: Difference between Virtex-II(E) und Virtex-E
40769: 02/03/14: Pete Fraser: Re: Difference between Virtex-II(E) und Virtex-E
40786: 02/03/15: Austin Lesea: 18X18, oh the possibilities!
40831: 02/03/16: Jan Gray: Re: Difference between Virtex-II(E) und Virtex-E
40833: 02/03/16: Jan Gray: Re: Difference between Virtex-II(E) und Virtex-E, correction
40856: 02/03/17: Ray Andraka: Re: Difference between Virtex-II(E) und Virtex-E
40754: 02/03/14: Jay: Re: Difference between Virtex-II(E) und Virtex-E
40900: 02/03/18: Pete Dudley: Re: Difference between Virtex-II(E) und Virtex-E
40902: 02/03/17: Jan Gray: Re: Difference between Virtex-II(E) und Virtex-E
40904: 02/03/18: rickman: Re: Difference between Virtex-II(E) und Virtex-E
40933: 02/03/18: Jason Daughenbaugh: Re: Difference between Virtex-II(E) und Virtex-E
40728: 02/03/14: H.L: Virtex BUFGDLL
40750: 02/03/14: Falk Brunner: Re: Virtex BUFGDLL
40778: 02/03/15: H.L: Re: Virtex BUFGDLL
40729: 02/03/13: Markus Meng: Spartan-XL, SpartanII and Spartan-IIE bitstream format question ...
40751: 02/03/14: Falk Brunner: Re: Spartan-XL, SpartanII and Spartan-IIE bitstream format question ...
40827: 02/03/16: Markus Meng: Why do I want to do this ??
40832: 02/03/16: Hal Murray: Re: Why do I want to do this ??
40839: 02/03/16: Falk Brunner: Re: Why do I want to do this ??
40772: 02/03/15: Rick Filipkiewicz: Re: Spartan-XL, SpartanII and Spartan-IIE bitstream format question ...
40777: 02/03/15: Georg Acher: Re: Spartan-XL, SpartanII and Spartan-IIE bitstream format question ...
40779: 02/03/15: rickman: Re: Spartan-XL, SpartanII and Spartan-IIE bitstream format question ...
40782: 02/03/15: Georg Acher: Re: Spartan-XL, SpartanII and Spartan-IIE bitstream format question ...
40794: 02/03/15: Falk Brunner: Re: Spartan-XL, SpartanII and Spartan-IIE bitstream format question ...
40829: 02/03/16: Markus Meng: Re: Spartan-XL, SpartanII and Spartan-IIE bitstream format question ...
40730: 02/03/14: haim moshe: XILINX XC2V6000
40731: 02/03/14: Nahum Barnea: use virtex2 DCM as delay line
40742: 02/03/14: Austin Lesea: Re: use virtex2 DCM as delay line
40755: 02/03/14: Manfred Kraus: Re: use virtex2 DCM as delay line
40732: 02/03/14: Martin Sauer: Xilinix FPGA width 5V IO
40752: 02/03/14: Falk Brunner: Re: Xilinix FPGA width 5V IO
40756: 02/03/14: Manfred Kraus: Re: Xilinix FPGA width 5V IO
40758: 02/03/14: Falk Brunner: Re: Xilinix FPGA width 5V IO
40773: 02/03/15: Rick Filipkiewicz: Re: Xilinix FPGA width 5V IO
40784: 02/03/15: Austin Lesea: Re: Xilinix FPGA with 5V IO
40792: 02/03/15: Falk Brunner: Re: Xilinix FPGA with 5V IO
40808: 02/03/15: rickman: Re: Xilinix FPGA with 5V IO
40811: 02/03/15: Austin Lesea: Re: Xilinix FPGA with 5V IO
40733: 02/03/14: RSM: Where can I get the information on implementing CPU with FPGA?
40734: 02/03/14: Christian Plessl: Re: Where can I get the information on implementing CPU with FPGA?
40737: 02/03/14: Josh Pfrimmer: where to start with constraining..
40744: 02/03/14: Ray Andraka: Re: where to start with constraining..
40768: 02/03/14: Josh Pfrimmer: Re: where to start with constraining..
40774: 02/03/15: Rick Filipkiewicz: Re: where to start with constraining..
40789: 02/03/15: Magnus Homann: Re: where to start with constraining..
40797: 02/03/15: Jay: Re: where to start with constraining..
40740: 02/03/14: Nitin Chandrachoodan: Proto boards for labs
40745: 02/03/14: Christopher Saunter: Re: Proto boards for labs
40747: 02/03/14: Noddy: Re: Proto boards for labs
40757: 02/03/14: Manfred Kraus: Re: Proto boards for labs
40770: 02/03/14: Jason Moore: Re: Proto boards for labs
41013: 02/03/19: Nitin Chandrachoodan: Re: Proto boards for labs
40785: 02/03/15: Wolfgang Loewer: Re: Proto boards for labs
40830: 02/03/16: Hal Murray: Re: Proto boards for labs
41011: 02/03/19: Nitin Chandrachoodan: Re: Proto boards for labs
40748: 02/03/14: Tom: WTB: Coolrunner
40780: 02/03/15: Stefanos: VHDL:Problem with depuncturing unit
40781: 02/03/15: Stefanos: Re: VHDL:Problem with depuncturing unit
40783: 02/03/15: Dan: PCI design in a Spartan II which crashes in some wintel PCs
40793: 02/03/15: Eric Crabill: Re: PCI design in a Spartan II which crashes in some wintel PCs
40814: 02/03/15: Yury: Re: PCI design in a Spartan II which crashes in some wintel PCs
40818: 02/03/15: Dan: To Yury's post
40795: 02/03/15: Falk Brunner: Re: PCI design in a Spartan II which crashes in some wintel PCs
40807: 02/03/15: Kevin Brace: Re: PCI design in a Spartan II which crashes in some wintel PCs
40820: 02/03/15: Dan: Reply to Kevin
40823: 02/03/16: Hal Murray: Re: Reply to Kevin
40855: 02/03/16: Kevin Brace: Re: Reply to Kevin
40817: 02/03/15: Dan: To Falk Brunner
40853: 02/03/16: Ray Andraka: Re: To Falk Brunner
40858: 02/03/16: Kevin Brace: Re: To Falk Brunner
40873: 02/03/17: Magnus Homann: Re: To Falk Brunner
40803: 02/03/15: Kevin Brace: Re: PCI design in a Spartan II which crashes in some wintel PCs
40815: 02/03/15: Kevin Brace: Re: PCI design in a Spartan II which crashes in some wintel PCs
40879: 02/03/17: ikauranen: Re: PCI design in a Spartan II which crashes in some wintel PCs
40788: 02/03/15: rickman: High speed clock routing
40790: 02/03/15: Magnus Homann: Re: High speed clock routing
40791: 02/03/15: rickman: Re: High speed clock routing
40802: 02/03/15: Magnus Homann: Re: High speed clock routing
40805: 02/03/16: Falk Brunner: Re: High speed clock routing
40834: 02/03/16: Magnus Homann: Re: High speed clock routing
40841: 02/03/16: Leon Heller: Re: High speed clock routing
40796: 02/03/15: Falk Brunner: Re: High speed clock routing
40810: 02/03/15: Austin Lesea: Re: High speed clock routing
40835: 02/03/16: Magnus Homann: Re: High speed clock routing
40837: 02/03/16: Falk Brunner: Re: High speed clock routing
40798: 02/03/15: rickman: Re: High speed clock routing
40801: 02/03/15: John_H: Re: High speed clock routing
40806: 02/03/15: rickman: Re: High speed clock routing
40809: 02/03/15: Austin Lesea: Re: High speed clock routing
40958: 02/03/19: rickman: Re: High speed clock routing
40987: 02/03/19: Austin Lesea: Re: High speed clock routing
40812: 02/03/16: John_H: Re: High speed clock routing
40821: 02/03/16: rickman: Re: High speed clock routing
40824: 02/03/16: Hal Murray: Re: High speed clock routing
40825: 02/03/16: Jonathan Kirwan: Re: High speed clock routing
40804: 02/03/15: Austin Lesea: Re: High speed clock routing
40901: 02/03/18: Pete Dudley: Re: High speed clock routing
40939: 02/03/18: rickman: Re: High speed clock routing
40942: 02/03/18: rickman: Re: High speed clock routing
40943: 02/03/18: Austin Lesea: Re: High speed clock routing
40946: 02/03/18: rickman: Re: High speed clock routing
41303: 02/03/25: <adyer@m5.dyer.dhs.org>: Re: High speed clock routing
40949: 02/03/18: Kevin Brace: Re: High speed clock routing
41015: 02/03/19: Bob Perlman: Re: High speed clock routing
41016: 02/03/19: Austin Lesea: Re: High speed clock routing
41000: 02/03/19: Jay: Re: High speed clock routing
41012: 02/03/19: Bob Perlman: Re: High speed clock routing
41071: 02/03/20: rickman: Re: High speed clock routing
41108: 02/03/20: Bob Perlman: Re: High speed clock routing
41112: 02/03/21: rickman: Re: High speed clock routing
41133: 02/03/21: Bob Perlman: Re: High speed clock routing
41134: 02/03/21: rickman: Re: High speed clock routing
41174: 02/03/22: Hal Murray: Re: High speed clock routing
41194: 02/03/22: rickman: Re: High speed clock routing
41139: 02/03/21: John_H: Re: High speed clock routing
41141: 02/03/21: Austin Lesea: Re: High speed clock routing
41147: 02/03/21: John_H: Re: High speed clock routing
41165: 02/03/21: Bob Perlman: Re: High speed clock routing
41143: 02/03/21: Falk Brunner: Re: High speed clock routing
41255: 02/03/23: Paul: Re: High speed clock routing
41264: 02/03/23: rickman: Re: High speed clock routing
41270: 02/03/23: Paul: Re: High speed clock routing
41284: 02/03/25: Martin Thompson: Re: High speed clock routing
41296: 02/03/25: rickman: Re: High speed clock routing
41333: 02/03/26: Martin Thompson: Re: High speed clock routing
40813: 02/03/15: J.Ho: [Virtex 2] DCM: "Factory_JF" option box in FPGA editor question
40928: 02/03/18: Austin Lesea: Re: [Virtex 2] DCM: "Factory_JF" option box in FPGA editor question
40951: 02/03/18: Kevin Brace: Re: [Virtex 2] DCM: "Factory_JF" option box in FPGA editor question
40988: 02/03/19: Austin Lesea: Re: [Virtex 2] DCM: "Factory_JF" option box in FPGA editor question
41007: 02/03/19: J.Ho: Re: [Virtex 2] DCM: "Factory_JF" option box in FPGA editor question
40816: 02/03/15: Dan: Spartan II IOB tristate control FF use
40819: 02/03/15: Eric Crabill: Re: Spartan II IOB tristate control FF use
40822: 02/03/16: Dan: Re: Spartan II IOB tristate control FF use
40826: 02/03/16: Rick Filipkiewicz: Re: Spartan II IOB tristate control FF use
40844: 02/03/16: Eric Crabill: Re: Spartan II IOB tristate control FF use
40869: 02/03/17: Rick Filipkiewicz: Re: Spartan II IOB tristate control FF use
40863: 02/03/17: Allan Herriman: Re: Spartan II IOB tristate control FF use
40871: 02/03/17: Rick Filipkiewicz: Re: Spartan II IOB tristate control FF use
40880: 02/03/17: Dan: Thanks to all for great tips
40840: 02/03/16: dmac: Spartan II IOB tristate control FF use
40828: 02/03/16: Rick Filipkiewicz: FPGA tools and Win2000 - problems
40842: 02/03/16: emanuel stiebler: Re: FPGA tools and Win2000 - problems
40874: 02/03/17: Rick Filipkiewicz: Re: FPGA tools and Win2000 - problems
40881: 02/03/17: emanuel stiebler: Re: FPGA tools and Win2000 - problems
40897: 02/03/17: Rick Filipkiewicz: Re: FPGA tools and Win2000 - problems
40843: 02/03/16: Spam Hater: Re: FPGA tools and Win2000 - problems
40875: 02/03/17: Rick Filipkiewicz: Re: FPGA tools and Win2000 - problems
40838: 02/03/16: Christopher Saunter: Extracting schematics to a vector file
40867: 02/03/17: <hamish@cloud.net.au>: Re: Extracting schematics to a vector file
40845: 02/03/16: niv: Virtex & CLKDLL
40847: 02/03/16: strut911: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
40848: 02/03/16: Mike Treseler: Re: just bought
40850: 02/03/16: Paul: Re: just bought
40857: 02/03/17: Tim Hubberstey: Re: just bought
40882: 02/03/17: VhdlCohen: Re: just bought
40851: 02/03/16: Austin Franklin: Re: just bought...
40852: 02/03/16: Pete Fraser: Re: just bought...
40854: 02/03/17: Tim: Re: just bought...
40862: 02/03/16: Austin Franklin: Re: just bought...
40884: 02/03/17: Clyde R. Shappee: Re: just bought...
40885: 02/03/17: Pete Fraser: Re: just bought...
40886: 02/03/17: Austin Franklin: Re: just bought...
40893: 02/03/17: Pete Fraser: Re: just bought...
40896: 02/03/17: VhdlCohen: Re: just bought...
40916: 02/03/18: Noddy: Re: just bought...
40927: 02/03/18: rickman: Re: just bought...
40903: 02/03/17: Austin Franklin: VERY OT - Re: just bought...
40892: 02/03/17: William Meyer: Re: just bought...
40919: 02/03/18: Magnus Homann: Re: just bought...
40859: 02/03/17: William Meyer: Re: just bought...
40883: 02/03/17: rickman: Re: just bought...
40890: 02/03/17: William Meyer: Re: just bought...
40898: 02/03/17: rickman: Re: just bought...
40931: 02/03/18: William Meyer: Re: just bought...
40917: 02/03/18: Noddy: Re: just bought...
40872: 02/03/17: Magnus Homann: Re: just bought...
40918: 02/03/18: Noddy: Re: just bought...
40877: 02/03/17: Frank Vorstenbosch: Re: just bought... -- wildly OT
40865: 02/03/16: strut911: Re: just bought
40864: 02/03/16: strut911: Re: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
40887: 02/03/17: Mike Treseler: Re: just bought
40876: 02/03/17: Leon Qin: Re: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
42127: 02/04/16: Paul Baxter: Re: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
42177: 02/04/17: Martin E.: Re: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
42179: 02/04/18: William Meyer: Re: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
42182: 02/04/18: Chuck Woodring: Re: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
42219: 02/04/18: VhdlCohen: Re: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
42242: 02/04/18: Paul Baxter: Re: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
42193: 02/04/18: Paul Baxter: Re: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
42228: 02/04/18: Mike Treseler: Re: just bought Cohen's book...Real Chip Design and Verification using Verilog and VHDL
40860: 02/03/16: Leon Qin: Looking for EBook?
40878: 02/03/17: Srinivasan Venkataramanan: Re: Looking for EBook?
41253: 02/03/23: Leon Qin: Re: Looking for EBook?
40861: 02/03/16: poirjh: pipeline
40888: 02/03/17: VhdlCohen: That vs Which // Common confusion among engineer writers
40895: 02/03/17: Tim: Re: That vs Which // Common confusion among engineer writers
40889: 02/03/17: VhdlCohen: Lies, damn lies and Synplicity
40912: 02/03/18: Muzaffer Kal: Re: Lies, damn lies and Synplicity
40922: 02/03/18: Rick Filipkiewicz: Re: Lies, damn lies and Synplicity
40891: 02/03/17: Prasanth Kumar: Xilinx Webpack/ModelSim VHDL Question
40894: 02/03/17: VhdlCohen: Re: Xilinx Webpack/ModelSim VHDL Question
40899: 02/03/18: Kelvin Hsu: How to deal with a high fan-out net in FPGA.
40907: 02/03/17: Amar Agnihotri: Re: How to deal with a high fan-out net in FPGA.
40909: 02/03/17: Amar Agnihotri: Re: How to deal with a high fan-out net in FPGA.
40910: 02/03/17: Amar Agnihotri: Re: How to deal with a high fan-out net in FPGA.
40947: 02/03/18: Jay: Re: How to deal with a high fan-out net in FPGA.
40905: 02/03/18: Kelvin Hsu: Clock buffer and Reset example.
40913: 02/03/18: Muzaffer Kal: Re: Clock buffer and Reset example.
40906: 02/03/17: Amar Agnihotri: Hardware : How to set the RESET signal...
40932: 02/03/18: John_H: Re: Hardware : How to set the RESET signal...
40908: 02/03/18: Martin Sauer: Xilinx Virtex II in comparsion with Altera Apex 20KC
41031: 02/03/20: Guy Schlacter: Re: Xilinx Virtex II in comparsion with Altera Apex 20KC
40911: 02/03/18: Kevin Brace: How do I simulate two separate designs simutaneously in ModelSim XE?
40914: 02/03/18: Muzaffer Kal: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
40921: 02/03/18: Utku Ozcan: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
40944: 02/03/18: Kevin Brace: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
40952: 02/03/18: Kevin Brace: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
41002: 02/03/19: Petter Gustad: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
40925: 02/03/18: marc Nance: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
40945: 02/03/18: Kevin Brace: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
40935: 02/03/18: Tom Loftus: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
40948: 02/03/18: Kevin Brace: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
40983: 02/03/19: Tom Loftus: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
40937: 02/03/18: Steve Meyer: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
40950: 02/03/18: Kevin Brace: Re: How do I simulate two separate designs simutaneously in ModelSim
41003: 02/03/19: Petter Gustad: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
40984: 02/03/19: Petter Gustad: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
41004: 02/03/19: Petter Gustad: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
41101: 02/03/20: Robert Schopmeyer: Re: How do I simulate two separate designs simutaneously in ModelSim XE?
40915: 02/03/18: Jo: simulating Core in ISE 4.1, + ModelSim
40920: 02/03/18: Jimmy Zhang: questions from a newby
40923: 02/03/18: Rick Filipkiewicz: Re: questions from a newby
40924: 02/03/18: Christian Plessl: Re: questions from a newby
40930: 02/03/18: Nicholas Weaver: Re: questions from a newby
40938: 02/03/18: Neil Franklin: Re: questions from a newby
41083: 02/03/20: Steve Casselman: Re: questions from a newby
41094: 02/03/20: Ray Andraka: Re: questions from a newby
40926: 02/03/18: Ken McElvain: New ASIC prototyping tool
40929: 02/03/18: luigi funes: laser programmed FPGAs
40934: 02/03/18: Kevin Neilson: All Digital PLL for locking DDS to input clock
40953: 02/03/19: Eric Jacobsen: Re: All Digital PLL for locking DDS to input clock
40954: 02/03/19: Kevin Neilson: Re: All Digital PLL for locking DDS to input clock
41259: 02/03/23: Matt Boytim: Re: All Digital PLL for locking DDS to input clock
40936: 02/03/18: James Lewis: Xilinx makesrc problem/questions
40940: 02/03/18: rickman: XC2S configuration... one more time
40941: 02/03/18: Hristo Stevic: advance in the design of controller
40955: 02/03/19: John Williams: XESS parallel cable
40973: 02/03/19: Dave Vanden Bout: Re: XESS parallel cable
40956: 02/03/19: John Williams: Webpack + XC4000
40974: 02/03/19: Dave Vanden Bout: Re: Webpack + XC4000
40997: 02/03/19: Johann Glaser: Re: Webpack + XC4000
40957: 02/03/18: Greg Otto: Xilinx : Altera pin compatibility
40980: 02/03/19: Ray Andraka: Re: Xilinx : Altera pin compatibility
41021: 02/03/19: Jay: Re: Xilinx : Altera pin compatibility
40959: 02/03/18: Aki Niimura: A petition for Synplify's new fature (FPGA synthesis tool)
40978: 02/03/19: Ken McElvain: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41017: 02/03/19: Kevin Brace: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41018: 02/03/19: Falk Brunner: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41043: 02/03/20: Kevin Brace: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41080: 02/03/20: Falk Brunner: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41113: 02/03/21: Kevin Brace: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41025: 02/03/19: Tim: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41111: 02/03/21: David Bishop: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41128: 02/03/21: Paul Butler: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41250: 02/03/22: Brian Davis: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41267: 02/03/23: Ken McElvain: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41269: 02/03/24: Tim: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41326: 02/03/25: Brian Davis: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41327: 02/03/25: Brian Davis: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41273: 02/03/24: Allan Herriman: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41275: 02/03/24: Ken McElvain: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41279: 02/03/24: Brian Davis: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41515: 02/04/01: sweir: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41566: 02/04/02: <hamish@cloud.net.au>: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41581: 02/04/02: sweir: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41589: 02/04/03: Allan Herriman: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41592: 02/04/03: sweir: Re: A petition for Synplify's new fature (FPGA synthesis tool)
41603: 02/04/03: Allan Herriman: Re: A petition for Synplify's new fature (FPGA synthesis tool)
40960: 02/03/19: Jimmy Zhang: simple Free FPGA tool
40971: 02/03/19: Jacky Renaux: Re: simple Free FPGA tool
41032: 02/03/19: arpit.desai: Re: simple Free FPGA tool
41039: 02/03/20: Kevin Brace: Re: simple Free FPGA tool
41280: 02/03/25: Kelvin Hsu: Re: simple Free FPGA tool
41390: 02/03/27: Kevin Brace: Re: simple Free FPGA tool
41040: 02/03/20: Kevin Brace: Re: simple Free FPGA tool
41197: 02/03/22: sunny: Re: simple Free FPGA tool
41201: 02/03/22: Tim: Re: simple Free FPGA tool
41215: 02/03/22: Kevin Brace: Re: simple Free FPGA tool
40961: 02/03/19: William Lenihan: Xilinx JTAG Cables
40995: 02/03/19: Manfred Kraus: Re: Xilinx JTAG Cables
41022: 02/03/19: In Memory of tecNovia: Re: Xilinx JTAG Cables
41162: 02/03/21: engr: Re: Xilinx JTAG Cables
41365: 02/03/26: Caleb Hess: Re: Xilinx JTAG Cables
40962: 02/03/19: wreg: constrain
40963: 02/03/19: wreg: state machine coding style
41023: 02/03/19: Jay: Re: state machine coding style
40965: 02/03/19: Philippe Robert: Unused I/Os + External Clock on Virtex II
40993: 02/03/19: Manfred Kraus: Re: Unused I/Os + External Clock on Virtex II
40994: 02/03/19: Austin Lesea: Re: Unused I/Os + External Clock on Virtex II
41005: 02/03/19: Austin Lesea: Re: Unused I/Os + External Clock on Virtex II
41006: 02/03/19: Tim: Re: Unused I/Os + External Clock on Virtex II
41008: 02/03/19: Peter Alfke: Re: Unused I/Os + External Clock on Virtex II
41019: 02/03/19: Falk Brunner: Re: Unused I/Os + External Clock on Virtex II
41052: 02/03/20: =?iso-8859-1?Q?St=E9phane?= Guyetant: Re: Unused I/Os + External Clock on Virtex II
41009: 02/03/19: Austin Lesea: Re: Unused I/Os + External Clock on Virtex II
41042: 02/03/20: Hal Murray: Re: Unused I/Os + External Clock on Virtex II
41055: 02/03/20: Austin Lesea: Re: Unused I/Os + External Clock on Virtex II + P-P Jitter
41078: 02/03/20: Falk Brunner: Re: Unused I/Os + External Clock on Virtex II + P-P Jitter
41089: 02/03/20: Austin Lesea: Re: Unused I/Os + External Clock on Virtex II + P-P Jitter
41184: 02/03/22: Hal Murray: Re: Unused I/Os + External Clock on Virtex II + P-P Jitter
40966: 02/03/19: Dave Haynes: Power Tie in Spartan IIE
40967: 02/03/19: Antonio: FIFO general question
40968: 02/03/19: Nicolas Matringe: Re: FIFO general question
40969: 02/03/19: Russell Shaw: Re: FIFO general question
40989: 02/03/19: Peter Alfke: Re: FIFO general question
40998: 02/03/19: Dan Kuechle: Re: FIFO general question
40999: 02/03/19: Falk Brunner: Re: FIFO general question
41027: 02/03/19: Loi Tran: Re: FIFO general question
41041: 02/03/19: Antonio: Re: FIFO general question
41061: 02/03/20: John_H: Re: FIFO general question
41065: 02/03/20: Peter Alfke: Re: FIFO general question
41086: 02/03/20: John_H: Re: FIFO general question
41087: 02/03/20: Peter Alfke: Re: FIFO general question
41104: 02/03/21: John_H: Re: FIFO general question
40970: 02/03/19: Mot: DDS in an FPGA
40972: 02/03/19: Kelvin Hsu: Re: DDS in an FPGA
40976: 02/03/19: Ray Andraka: Re: DDS in an FPGA
40982: 02/03/19: Salman Sheikh: Re: DDS in an FPGA
41010: 02/03/19: Ray Andraka: Re: DDS in an FPGA
40975: 02/03/19: H.L: STARTUP_VIRTEX primitive
41035: 02/03/19: Hobson: Re: STARTUP_VIRTEX primitive
41037: 02/03/20: Ray Andraka: Re: STARTUP_VIRTEX primitive
41070: 02/03/20: H.L: Re: STARTUP_VIRTEX primitive
40977: 02/03/19: Luigi: Signal driven by a "configuration done" event
40979: 02/03/19: news.dlr.de: 1,5V power supply?
40985: 02/03/19: Tim: Re: 1,5V power supply?
40991: 02/03/19: Manfred Kraus: Re: 1,5V power supply?
40996: 02/03/19: Theron Hicks: Re: 1,5V power supply?
41020: 02/03/19: Jay: Re: 1,5V power supply?
41131: 02/03/21: Ian Smith: Re: 1,5V power supply?
40981: 02/03/19: Chuck: virtex 2 orcad symbols?
40992: 02/03/19: Manfred Kraus: Re: virtex 2 orcad symbols?
41090: 02/03/20: Austin Franklin: Re: virtex 2 orcad symbols?
41092: 02/03/20: Mike Treseler: Re: virtex 2 orcad symbols?
40990: 02/03/19: Richard Auletta: ASIC/SOC 2002 CALL FOR CORPORATE PARTICIPATION AND PAPERS
41001: 02/03/19: thorsten mader: using carry logic
41014: 02/03/19: D Brown: Constraint File NET syntax
41024: 02/03/19: Hobson: Re: Constraint File NET syntax
41026: 02/03/19: Tim: Re: Constraint File NET syntax
41060: 02/03/20: D Brown: Re: Constraint File NET syntax
41072: 02/03/20: Tim: Re: Constraint File NET syntax
41073: 02/03/20: Tim: Re: Constraint File NET syntax
41028: 02/03/19: ssy: how to deal with signal pass through two clock domain
41029: 02/03/20: Guy Schlacter: Re: how to deal with signal pass through two clock domain
41075: 02/03/20: Mike Treseler: Re: how to deal with signal pass through two clock domain
41099: 02/03/20: ssy: Re: how to deal with signal pass through two clock domain
41154: 02/03/21: Mike Treseler: Re: how to deal with signal pass through two clock domain
41098: 02/03/20: Jay: Re: how to deal with signal pass through two clock domain
41114: 02/03/20: ssy: Re: how to deal with signal pass through two clock domain
41030: 02/03/19: Jacke: Fixed Point Library
41103: 02/03/20: Jay: Re: Fixed Point Library
41126: 02/03/21: Jun Jiang: Re: Fixed Point Library
41033: 02/03/20: Guy Schlacter: Any Stratix impressions based on results?
41038: 02/03/20: Ray Andraka: Re: Any Stratix impressions based on results?
41548: 02/04/02: Guy Schlacter: Re: Any Stratix impressions based on results?
41034: 02/03/20: Kelvin Hsu: Possibility of RTL and Gate-level simulation dont match?
41102: 02/03/20: Jay: Re: Possibility of RTL and Gate-level simulation dont match?
41105: 02/03/21: Kelvin Hsu: Re: Possibility of RTL and Gate-level simulation dont match?
41107: 02/03/21: Tim: Re: Possibility of RTL and Gate-level simulation dont match?
41110: 02/03/21: Kelvin Hsu: Re: Possibility of RTL and Gate-level simulation dont match?
41130: 02/03/21: Spam Hater: Re: Possibility of RTL and Gate-level simulation dont match?
41166: 02/03/22: Kelvin Hsu: Re: Possibility of RTL and Gate-level simulation dont match?
41200: 02/03/22: Spam Hater: Re: Possibility of RTL and Gate-level simulation dont match?
41243: 02/03/23: Kelvin Hsu: Re: Possibility of RTL and Gate-level simulation dont match?
41494: 02/03/30: Rick Filipkiewicz: Re: Possibility of RTL and Gate-level simulation dont match?
41495: 02/03/30: Spam Hater: Re: Possibility of RTL and Gate-level simulation dont match?
41155: 02/03/21: Mike Treseler: Re: Possibility of RTL and Gate-level simulation dont match?
41036: 02/03/20: Steve Meyer: Announce: Commercial/Non-Commercial Verilog simulator
41047: 02/03/20: Uwe Bonnes: Re: Announce: Commercial/Non-Commercial Verilog simulator
41044: 02/03/20: Le Mer Michel: which is the fastest FPGA ?
41054: 02/03/20: Ray Andraka: Re: which is the fastest FPGA ?
41177: 02/03/22: Hal Murray: Re: which is the fastest FPGA ?
41182: 02/03/22: Ulf Samuelsson: Re: which is the fastest FPGA ?
41189: 02/03/22: Ray Andraka: Re: which is the fastest FPGA ?
41286: 02/03/25: Le Mer Michel: Re: which is the fastest FPGA ?
41294: 02/03/25: Ray Andraka: Re: which is the fastest FPGA ?
41192: 02/03/22: Johann Glaser: Re: which is the fastest FPGA ?
41045: 02/03/20: Jimmy Zhang: low cost PCI spartan board needed
41046: 02/03/20: Jimmy Zhang: Re: low cost PCI spartan board needed
41081: 02/03/20: Kevin Brace: Re: low cost PCI spartan board needed
41082: 02/03/20: Jimmy Zhang: Re: low cost PCI spartan board needed
41085: 02/03/20: Kevin Brace: Re: low cost PCI spartan board needed
41118: 02/03/21: Jimmy Zhang: Re: low cost PCI spartan board needed
41149: 02/03/21: Eric Crabill: Re: low cost PCI spartan board needed
41053: 02/03/20: Denis Lachapelle: Re: low cost PCI spartan board needed
41049: 02/03/20: Luigi: VHDL OPEN association element error in QUARTUS compiler
41051: 02/03/20: Allan Herriman: Re: VHDL OPEN association element error in QUARTUS compiler
41050: 02/03/20: =?ISO-8859-1?Q?L=E4hteenm=E4ki?= Jussi: MAX7000 bypass capasitances
41064: 02/03/20: luigi funes: Re: MAX7000 bypass capasitances
41074: 02/03/20: Victor Schutte: Re: MAX7000 bypass capasitances
41084: 02/03/20: John_H: Re: MAX7000 bypass capasitances
41056: 02/03/20: Harjo Otten: syntax problem.....
41057: 02/03/20: Theron Hicks: XPOWER accuracy?
41077: 02/03/20: Falk Brunner: Re: XPOWER accuracy?
41096: 02/03/20: Patrick: Re: XPOWER accuracy?
41125: 02/03/21: Brendan Cullen: Re: XPOWER accuracy?
41129: 02/03/21: Theron Hicks: Re: XPOWER accuracy? Commendations
41148: 02/03/21: Peter Alfke: Re: XPOWER accuracy? Commendations
41181: 02/03/22: Hal Murray: Re: XPOWER accuracy? Commendations
41206: 02/03/22: Peter Alfke: Re: XPOWER accuracy? Commendations
41144: 02/03/21: Falk Brunner: Re: XPOWER accuracy?
41058: 02/03/20: emanuel stiebler: spartan 2e, 5V i/o
41062: 02/03/20: Austin Lesea: Re: spartan 2e, 5V i/o
41106: 02/03/20: emanuel stiebler: Re: spartan 2e, 5V i/o
41138: 02/03/21: Austin Lesea: Re: spartan 2e, 5V i/o
41063: 02/03/20: Prashant: Modelsim or Quartus II Simulator
41067: 02/03/20: Paul Baxter: Re: Modelsim or Quartus II Simulator
41068: 02/03/20: Kevin Neilson: Missing Timing by 30,000 ns
41076: 02/03/20: Falk Brunner: Re: Missing Timing by 30,000 ns
41088: 02/03/20: Goran Bilski: Re: Missing Timing by 30,000 ns
41097: 02/03/20: Kevin Neilson: Re: Missing Timing by 30,000 ns
41249: 02/03/23: Kevin Neilson: Re: Missing Timing by 30,000 ns
41297: 02/03/25: Goran Bilski: Re: Missing Timing by 30,000 ns
41300: 02/03/25: Austin Lesea: Re: Missing Timing by 30,000 ns
41299: 02/03/25: Jason Daughenbaugh: Re: Missing Timing by 30,000 ns
41309: 02/03/25: Kevin Neilson: Re: Missing Timing by 30,000 ns
41398: 02/03/27: Serkan Dinmez: Re: Missing Timing by 30,000 ns
41091: 02/03/20: Yves Petinot: Compilation of VHDL description to target FPGA ... (newbie)
41093: 02/03/20: Bob Armstrng: Can't program XC4010 with JTAG without BSCAN???
41159: 02/03/21: Arthur: Re: Can't program XC4010 with JTAG without BSCAN???
41208: 02/03/22: Bob Armstrng: Re: Can't program XC4010 with JTAG without BSCAN???
41224: 02/03/22: Arthur: Re: Can't program XC4010 with JTAG without BSCAN???
41100: 02/03/20: James Lewis: Xilinx Spartan XL VHDL????
41115: 02/03/21: Jimmy Zhang: more questions
41116: 02/03/21: Jimmy Zhang: Re: more questions
41153: 02/03/21: Kevin Brace: Re: more questions
41124: 02/03/21: Martin Thompson: Re: more questions
41176: 02/03/22: Hal Murray: Re: more questions
41150: 02/03/21: Kevin Brace: Re: more questions
41117: 02/03/21: Kelvin Hsu: Difference between two mulplications?
41136: 02/03/21: John_H: Re: Difference between two mulplications?
41119: 02/03/21: satya: doubt on GDSII file integration
41121: 02/03/21: Kelvin Hsu: Re: doubt on GDSII file integration
41120: 02/03/21: Wolfgang Pieper: RAM initialization
41135: 02/03/21: John_H: Re: RAM initialization
41122: 02/03/21: H.L: simulation issues
41123: 02/03/21: Kelvin Hsu: Re: simulation issues
41127: 02/03/21: Ray Andraka: Re: simulation issues
41142: 02/03/21: Paul Glover: Re: simulation issues
41132: 02/03/21: Stephanie McBader: Maximum device usage for successful PAR
41140: 02/03/21: Paul Glover: Re: Maximum device usage for successful PAR
41145: 02/03/21: John_H: Re: Maximum device usage for successful PAR
41167: 02/03/22: Ray Andraka: Re: Maximum device usage for successful PAR
41289: 02/03/25: S.H.McBader: Re: Maximum device usage for successful PAR
41293: 02/03/25: Ray Andraka: Re: Maximum device usage for successful PAR
41411: 02/03/27: Marc Randolph: Re: Maximum device usage for successful PAR
41137: 02/03/21: kudla: synplify, quartus II 2.0
41151: 02/03/21: Kevin Brace: Re: synplify, quartus II 2.0
41157: 02/03/21: Paul Baxter: Re: synplify, quartus II 2.0
42037: 02/04/13: Johnsonw10: Re: synplify, quartus II 2.0
41179: 02/03/22: kudla: Re: synplify, quartus II 2.0
41292: 02/03/25: Wolfgang Loewer: Re: synplify, quartus II 2.0
41397: 02/03/27: slarty: Re: synplify, quartus II 2.0
41146: 02/03/21: Tibor: cpga : Converting PAL design
41161: 02/03/21: Falk Brunner: Re: cpga : Converting PAL design
41152: 02/03/21: Kenny: Where to get docs regarding WEP Encryption
41156: 02/03/21: Jimmy Zhang: PCI interface
41158: 02/03/22: Changchun WAN: HELP me, about chipscope analyzer
41462: 02/03/29: William L Hunter Jr: Re: HELP me, about chipscope analyzer
41536: 02/04/01: Rick Filipkiewicz: Re: HELP me, about chipscope analyzer
41160: 02/03/21: Petter Gustad: coregen under Solaris
41163: 02/03/21: Georg Acher: Re: coregen under Solaris
41170: 02/03/22: Petter Gustad: Re: coregen under Solaris
41185: 02/03/22: Petter Gustad: Re: coregen under Solaris
41191: 02/03/22: Georg Acher: Re: coregen under Solaris
41226: 02/03/22: Petter Gustad: Re: coregen under Solaris
41164: 02/03/21: Craig McAdam: Interconnect system for multiple FPGA's ?
41171: 02/03/22: Muzaffer Kal: Re: Interconnect system for multiple FPGA's ?
41357: 02/03/26: Craig McAdam: Re: Interconnect system for multiple FPGA's ?
41193: 02/03/22: Christopher Saunter: Re: Interconnect system for multiple FPGA's ?
41359: 02/03/26: Craig McAdam: Re: Interconnect system for multiple FPGA's ?
41168: 02/03/21: David Lamb: Working modulo exponent routine?
41172: 02/03/22: Muzaffer Kal: Re: Working modulo exponent routine?
41169: 02/03/22: Dean Armstrong: Clock termination affecting JTAG interface
41178: 02/03/22: Paul Burke: Re: Clock termination affecting JTAG interface
41205: 02/03/22: Peter Alfke: Re: Clock termination affecting JTAG interface
41278: 02/03/25: Dean Armstrong: Re: Clock termination affecting JTAG interface
41180: 02/03/22: Martin Schoeberl: Re: Clock termination affecting JTAG interface
41593: 02/04/02: Barry Arneson: Re: Clock termination affecting JTAG interface
41204: 02/03/22: <nospam@newsguy.com>: Re: Clock termination affecting JTAG interface
41257: 02/03/23: Paul: Re: Clock termination affecting JTAG interface
41277: 02/03/25: Dean Armstrong: Re: Clock termination affecting JTAG interface
41463: 02/03/29: Eddy: Re: Clock termination affecting JTAG interface
41480: 02/03/29: Steve Casselman: Re: Clock termination affecting JTAG interface
41173: 02/03/21: siva koka: SPI-4 interface IP core available(OIF Standard) with MAC Core
41175: 02/03/22: Jimmy Zhang: another from newbie
41183: 02/03/22: Josh Pfrimmer: Re: another from newbie
41186: 02/03/22: Ken Mac: Re: another from newbie
41187: 02/03/22: Peter Lang: Altera Stratix compared to Xilinx Virtex
41188: 02/03/22: Ray Andraka: Re: Altera Stratix compared to Xilinx Virtex
41195: 02/03/22: Mikeandmax: Re: Altera Stratix compared to Xilinx Virtex
41210: 02/03/22: Falk Brunner: Re: Altera Stratix compared to Xilinx Virtex
41234: 02/03/22: Ray Andraka: Re: Altera Stratix compared to Xilinx Virtex
41242: 02/03/22: Girl: Re: Altera Stratix compared to Xilinx Virtex
41244: 02/03/23: Ray Andraka: Re: Altera Stratix compared to Xilinx Virtex
41261: 02/03/23: rickman: Re: Altera Stratix compared to Xilinx Virtex
41262: 02/03/23: rickman: Re: Altera Stratix compared to Xilinx Virtex
41190: 02/03/22: Jacke: SystemC compiler
41282: 02/03/25: Eyck Jentzsch: Re: SystemC compiler
41285: 02/03/25: Alan Fitch: Re: SystemC compiler
41196: 02/03/22: =?iso-8859-1?Q?St=E9phane?= Guyetant: JTAG under Linux
41228: 02/03/22: Jon Schneider: Re: JTAG under Linux
41198: 02/03/22: Dan: Ligthning strikes & EMI - SPARTAN II design in flight
41258: 02/03/23: Paul: Re: Ligthning strikes & EMI - SPARTAN II design in flight
41199: 02/03/22: rickman: Poor availability problems on Coolrunner
41203: 02/03/22: Mikeandmax: Re: Poor availability problems on Coolrunner
41217: 02/03/22: rickman: Re: Poor availability problems on Coolrunner
41220: 02/03/22: Mikeandmax: Re: Poor availability problems on Coolrunner
41225: 02/03/22: rickman: Re: Poor availability problems on Coolrunner
41227: 02/03/22: Theron Hicks: Re: Poor availability problems on Coolrunner
41231: 02/03/22: rickman: Re: Poor availability problems on Coolrunner
41317: 02/03/25: Jon Elson: Re: Poor availability problems on Coolrunner
41213: 02/03/22: MK: Re: Poor availability problems on Coolrunner
41218: 02/03/22: Falk Brunner: Re: Poor availability problems on Coolrunner
41221: 02/03/22: rickman: Re: Poor availability problems on Coolrunner
41222: 02/03/22: Austin Lesea: Re: Poor availability problems on Coolrunner
41232: 02/03/22: rickman: GREAT availability on Coolrunner!!! (was: Poor availability problems on
41233: 02/03/22: Austin Lesea: Got Parts?
41237: 02/03/22: Peter Alfke: Re: GREAT availability on Coolrunner!!! (was: Poor availability problems
41245: 02/03/22: rickman: Re: GREAT availability on Coolrunner!!! (was: Poor availability problems
41426: 02/03/27: Tim: Partial Reconfiguration (was: GREAT availability on Coolrunner)
41444: 02/03/28: Peter Alfke: Re: Partial Reconfiguration (was: GREAT availability on Coolrunner)
41447: 02/03/28: rickman: Re: Partial Reconfiguration (was: GREAT availability on Coolrunner)
41452: 02/03/28: Ray Andraka: Re: Partial Reconfiguration (was: GREAT availability on Coolrunner)
41454: 02/03/28: Steve Casselman: Re: Partial Reconfiguration (was: GREAT availability on Coolrunner)
41458: 02/03/29: Ray Andraka: Re: Partial Reconfiguration (was: GREAT availability on Coolrunner)
41456: 02/03/28: rickman: Re: Partial Reconfiguration (was: GREAT availability on Coolrunner)
41457: 02/03/28: Steve Casselman: Re: Partial Reconfiguration (was: GREAT availability on Coolrunner)
41453: 02/03/28: Peter Alfke: Re: Partial Reconfiguration (was: GREAT availability on Coolrunner)
41451: 02/03/28: Ray Andraka: Re: Partial Reconfiguration (was: GREAT availability on Coolrunner)
41455: 02/03/28: Peter Alfke: Re: Partial Reconfiguration (was: GREAT availability on Coolrunner)
41238: 02/03/23: Ray Andraka: Re: GREAT availability on Coolrunner!!! (was: Poor availability problems
41219: 02/03/23: Jim Granville: Re: Poor availability problems on Coolrunner
41223: 02/03/22: rickman: Re: Poor availability problems on Coolrunner
41236: 02/03/23: Jim Granville: Re: Poor availability problems on Coolrunner
41246: 02/03/22: rickman: Re: Poor availability problems on Coolrunner
41202: 02/03/22: Christian Plessl: Evaluation board for Virtex-II pro
41207: 02/03/22: John_H: Any DDR SDRAM controller stories?
41260: 02/03/23: Spam Hater: Re: Any DDR SDRAM controller stories?
41209: 02/03/22: Eric Crabill: Pipelined sorting algorithms...
41212: 02/03/22: John_H: Re: Pipelined sorting algorithms...
41214: 02/03/22: Eric Crabill: Re: Pipelined sorting algorithms...
41229: 02/03/22: Kelly Hall: Re: Pipelined sorting algorithms...
41230: 02/03/22: John_H: Re: Pipelined sorting algorithms...
41239: 02/03/23: Kevin Neilson: Re: Pipelined sorting algorithms...
41290: 02/03/25: Jonathan Bromley: Re: Pipelined sorting algorithms...
41429: 02/03/28: John_H: Re: Pipelined sorting algorithms...
41216: 02/03/22: Fabien Todescato: Re: Pipelined sorting algorithms...
41254: 02/03/23: Philip Freidin: Re: Pipelined sorting algorithms...
41287: 02/03/25: Christopher Saunter: Re: Pipelined sorting algorithms...
41291: 02/03/25: Christopher Saunter: Re: Pipelined sorting algorithms...
41304: 02/03/25: Eric Crabill: Re: Pipelined sorting algorithms...
41338: 02/03/26: Christopher Saunter: Re: Pipelined sorting algorithms...
41319: 02/03/26: glen herrmannsfeldt: Re: Pipelined sorting algorithms...
41211: 02/03/22: Philip Freidin: Call for Participation FCCM-2002
41235: 02/03/22: rickman: A poor man's boundary scan test tool
41241: 02/03/22: James Horn: Re: A poor man's boundary scan test tool
41240: 02/03/22: Yury: Electronic Parts Locator
41247: 02/03/22: rickman: Re: Electronic Parts Locator
41263: 02/03/23: Colin O'Flynn: Re: Electronic Parts Locator
41268: 02/03/23: Yury: Re: Electronic Parts Locator
41248: 02/03/23: BumsukLee: Xilinx Async Fifo trouble
41288: 02/03/25: Phil Connor: Re: Xilinx Async Fifo trouble
41251: 02/03/22: FIFO_Luvr: FIFOs are just like magic
41252: 02/03/23: Leon Qin: QuartusII 2.0!!!!!
41265: 02/03/23: Peter Ormsby: Re: QuartusII 2.0!!!!!
41266: 02/03/23: Kevin Brace: Re: QuartusII 2.0!!!!!
41256: 02/03/23: Niv: Too many clocks
41276: 02/03/24: Mike Johnson: Re: Too many clocks
41295: 02/03/25: Ray Andraka: Re: Too many clocks
41383: 02/03/26: Jason T. Wright: Re: Too many clocks
41271: 02/03/23: Mik e Payne: Help with Xilinx CoolRunner Problem
41272: 02/03/24: Falk Brunner: Re: Help with Xilinx CoolRunner Problem
41315: 02/03/25: Mik e Payne: Re: Help with Xilinx CoolRunner Problem
41316: 02/03/25: Jon Elson: Re: Help with Xilinx CoolRunner Problem
41370: 02/03/26: Mik e Payne: Re: Help with Xilinx CoolRunner Problem
41360: 02/03/26: Falk Brunner: Re: Help with Xilinx CoolRunner Problem
41371: 02/03/26: Mik e Payne: Re: Help with Xilinx CoolRunner Problem
41373: 02/03/27: Jim Granville: Re: Help with Xilinx CoolRunner Problem
41377: 02/03/26: Jon Elson: Re: Help with Xilinx CoolRunner Problem
41274: 02/03/24: Anurag: RTP & Aggregation design
41281: 02/03/24: anish: question on LFSR
41283: 02/03/25: Nicholas Weaver: Re: question on LFSR
41302: 02/03/25: John_H: Re: question on LFSR
41310: 02/03/25: VhdlCohen: Re: question on LFSR
41314: 02/03/25: Peter Alfke: Re: question on LFSR
41320: 02/03/26: Ray Andraka: Re: question on LFSR
41322: 02/03/25: Jan Gray: Re: question on LFSR
41324: 02/03/26: Ray Andraka: Re: question on LFSR
41354: 02/03/26: Ken Chapman: Re: question on LFSR
41364: 02/03/26: Ray Andraka: Re: question on LFSR
41366: 02/03/26: Ken McElvain: Re: question on LFSR
41369: 02/03/26: Kevin Neilson: Re: question on LFSR
41372: 02/03/26: Peter Alfke: Re: question on LFSR
41382: 02/03/27: Ray Andraka: Re: question on LFSR
41399: 02/03/27: Ken Chapman: Re: question on LFSR
41306: 02/03/25: Kevin Neilson: Re: question on LFSR
41307: 02/03/25: Austin Lesea: Re: question on LFSR
41308: 02/03/25: Jan Gray: Re: question on LFSR
41298: 02/03/25: David Frith: Xilinx 4.2i not working on my design
41311: 02/03/25: emanuel stiebler: Re: Xilinx 4.2i not working on my design
41334: 02/03/26: David Frith: Re: Xilinx 4.2i not working on my design
41347: 02/03/26: Noddy: Re: Xilinx 4.2i not working on my design
41355: 02/03/26: Bob Perlman: Re: Xilinx 4.2i not working on my design
41783: 02/04/08: Rick Filipkiewicz: Re: Xilinx 4.2i not working on my design
41784: 02/04/08: Kevin Brace: Re: Xilinx 4.2i not working on my design
41350: 02/03/26: Jon Schneider: Re: Xilinx 4.2i not working on my design
41392: 02/03/27: David Frith: Re: Xilinx 4.2i not working on my design
42423: 02/04/23: Peter Young: Re: Xilinx 4.2i not working on my design
42450: 02/04/24: David Frith: Re: Xilinx 4.2i not working on my design
41301: 02/03/25: James Thurley: Can't detect Altera MAX7000s using JTAG
41305: 02/03/25: Mike Treseler: Re: Can't detect Altera MAX7000s using JTAG
41312: 02/03/25: Tuomo Auer: Re: Can't detect Altera MAX7000s using JTAG
41318: 02/03/25: James Horn: Re: Can't detect Altera MAX7000s using JTAG
41323: 02/03/26: Arbitrary: Re: Can't detect Altera MAX7000s using JTAG
41325: 02/03/26: Arbitrary: Re: Can't detect Altera MAX7000s using JTAG
41330: 02/03/25: sunny: Re: Can't detect Altera MAX7000s using JTAG
41336: 02/03/26: Dan Oprisan: Re: Can't detect Altera MAX7000s using JTAG
41343: 02/03/26: James Thurley: Re: Can't detect Altera MAX7000s using JTAG
41313: 02/03/25: Robert S. Grimes: Using GCLK1 as Input on Spartan II under Foundation 4.1
41329: 02/03/26: Kevin Brace: Re: Using GCLK1 as Input on Spartan II under Foundation 4.1
41342: 02/03/26: Robert S. Grimes: Re: Using GCLK1 as Input on Spartan II under Foundation 4.1
41321: 02/03/26: Kelvin Hsu: How to recover a Bluetooth data stream.
41328: 02/03/25: Jaime Andres Aranguren Cardona: I2C Slave sampling edge
41332: 02/03/26: Matthias Weingart: Re: I2C Slave sampling edge
41349: 02/03/26: Yury: Re: I2C Slave sampling edge
41379: 02/03/27: Philip Freidin: Re: I2C Slave sampling edge
41386: 02/03/27: rickman: Re: I2C Slave sampling edge
41401: 02/03/27: Ray Andraka: Re: I2C Slave sampling edge
41407: 02/03/27: rickman: Re: I2C Slave sampling edge
41430: 02/03/28: Hal Murray: Re: I2C Slave sampling edge
41431: 02/03/28: Ray Andraka: Re: I2C Slave sampling edge
41439: 02/03/28: rickman: Re: I2C Slave sampling edge
41503: 02/03/31: Hal Murray: Re: I2C Slave sampling edge
42200: 02/04/18: Roland Zitzke: Re: I2C Slave sampling edge
42203: 02/04/18: Tauno Voipio: Re: I2C Slave sampling edge
41331: 02/03/26: Kevin Brace: How to activate 5V PCI I/O pads in FLEX10KE/ACEX1K?
41380: 02/03/27: Peter Ormsby: Re: How to activate 5V PCI I/O pads in FLEX10KE/ACEX1K?
41575: 02/04/02: Kevin Brace: Re: How to activate 5V PCI I/O pads in FLEX10KE/ACEX1K?
41335: 02/03/26: David Brown: VCC and GND net warnings with ispDesignExpert
41337: 02/03/26: Kevin Brace: FLEX10KE/ACEX1K IOE Packing Rules
41339: 02/03/26: S³awomir Balon: clock source
41352: 02/03/26: Mike Treseler: Re: clock source
41353: 02/03/26: Peter Alfke: Re: clock source
41358: 02/03/26: Falk Brunner: Re: clock source
41385: 02/03/27: rickman: Re: clock source
41400: 02/03/27: Ray Andraka: Re: clock source
41789: 02/04/08: Rick Filipkiewicz: Re: clock source
41341: 02/03/26: spyng: how to prevent infer of Mult18x18 in VirtexII
41344: 02/03/26: sunny: Re: how to prevent infer of Mult18x18 in VirtexII
41436: 02/03/28: spyng: Re: how to prevent infer of Mult18x18 in VirtexII
41440: 02/03/28: Ken McElvain: Re: how to prevent infer of Mult18x18 in VirtexII
41470: 02/03/29: spyng: Re: how to prevent infer of Mult18x18 in VirtexII
41345: 02/03/26: <vlad@comsys.ntu-kpi.kiev.ua>: failure rate of Xilinx chips
41361: 02/03/26: Peter Alfke: Re: failure rate of Xilinx chips
41389: 02/03/27: <vlad@comsys.ntu-kpi.kiev.ua>: Re: failure rate of Xilinx chips
41376: 02/03/26: Jon Elson: Re: failure rate of Xilinx chips
41346: 02/03/26: S³awomir Balon: clock multiplier
41351: 02/03/26: Mike Treseler: Re: clock multiplier
41374: 02/03/27: Jim Granville: Re: clock multiplier
41394: 02/03/27: sunny: Re: clock multiplier
41356: 02/03/26: Jeanan Del: Handel-C useless.. Move to SystemC
41378: 02/03/27: Kelvin Hsu: Re: Handel-C useless.. Move to SystemC
41384: 02/03/27: Phil Hays: Re: Handel-C useless.. Move to SystemC
41443: 02/03/28: Henry Styles: Re: Handel-C useless.. Move to SystemC
41567: 02/04/02: Noel Klonsky: Re: Handel-C vs SystemC
41598: 02/04/02: Jeanan Del: Re: Handel-C vs SystemC
41803: 02/04/08: Domagoj: Re: Handel-C useless.. Move to SystemC
41362: 02/03/26: Arbitrary: ByteblasterMV EPM7064S voltage problem
41363: 02/03/26: Mike Treseler: Re: ByteblasterMV EPM7064S voltage problem
41367: 02/03/26: sunny: Re: ByteblasterMV EPM7064S voltage problem
41375: 02/03/26: Russell Shaw: Re: ByteblasterMV EPM7064S voltage problem
41387: 02/03/27: Tuomo Auer: Re: ByteblasterMV EPM7064S voltage problem
41368: 02/03/26: Rene Tschaggelar: Re: ByteblasterMV EPM7064S voltage problem
41381: 02/03/27: Arbitrary: Re: ByteblasterMV EPM7064S voltage problem
41388: 02/03/27: Tuomo Auer: Re: ByteblasterMV EPM7064S voltage problem
41391: 02/03/27: Dan Oprisan: Re: ByteblasterMV EPM7064S voltage problem
41432: 02/03/27: Daniel Lang: Re: ByteblasterMV EPM7064S voltage problem
41588: 02/04/03: Russell Shaw: Re: ByteblasterMV EPM7064S voltage problem
41620: 02/04/03: Jay: Re: ByteblasterMV EPM7064S voltage problem
41625: 02/04/03: Arbitrary: Re: ByteblasterMV EPM7064S voltage problem
41393: 02/03/27: Andy Dow: XPower & Power Estimator Spreadsheet
41402: 02/03/27: Ray Andraka: Re: XPower & Power Estimator Spreadsheet
41405: 02/03/27: Steven Derrien: Re: XPower & Power Estimator Spreadsheet
41413: 02/03/27: Ray Andraka: Re: XPower & Power Estimator Spreadsheet
41395: 02/03/27: deerlux: How can I add constrains?
41404: 02/03/27: Ray Andraka: Re: How can I add constrains?
41396: 02/03/27: Kelvin Hsu: How to probe internal signals from Xilinx netlist?
41739: 02/04/06: Thomas: Re: How to probe internal signals from Xilinx netlist?
41749: 02/04/06: Jay: Re: How to probe internal signals from Xilinx netlist?
41753: 02/04/06: Steve Casselman: Re: How to probe internal signals from Xilinx netlist?
41760: 02/04/06: freny: Re: How to probe internal signals from Xilinx netlist?
41792: 02/04/08: Kelvin Xu Qijun: Re: How to probe internal signals from Xilinx netlist?
41810: 02/04/08: Steve Casselman: Re: How to probe internal signals from Xilinx netlist?
41809: 02/04/08: Steve Casselman: Re: How to probe internal signals from Xilinx netlist?
41403: 02/03/27: Paul Baxter: Quartus 2, ActiveHDL and megafunctions like altclklock
41406: 02/03/27: Zack Hugh: Core Generator and Modelsim XE
41412: 02/03/27: aaron: Re: Core Generator and Modelsim XE
41477: 02/03/29: praveen: Re: Core Generator and Modelsim XE
41408: 02/03/27: <chlin@telecom.ece.ntua.gr>: Re: simulation issues
41409: 02/03/27: Dziadek: XC9500 low temp. problem
41424: 02/03/27: Jon Elson: Re: XC9500 low temp. problem
41433: 02/03/28: Dziadek: Re: XC9500 low temp. problem
41434: 02/03/28: Hal Murray: Re: XC9500 low temp. problem
41576: 02/04/02: <hw_designer@yahoo.com>: Re: XC9500 low temp. problem
41410: 02/03/27: rickman: I2C complexity
41416: 02/03/28: Jim Granville: Re: I2C complexity
41414: 02/03/27: Chris Wilkson: FPGA config without boot PROM???
41415: 02/03/27: Peter Alfke: Re: FPGA config without boot PROM???
41427: 02/03/27: Kevin Brace: Re: FPGA config without boot PROM???
41428: 02/03/27: Peter Alfke: Re: FPGA config without boot PROM???
41465: 02/03/29: Kevin Brace: Re: FPGA config without boot PROM???
41492: 02/03/30: Pete Dudley: Re: FPGA config without boot PROM???
41516: 02/04/01: Falk Brunner: Re: FPGA config without boot PROM???
41533: 02/04/01: Ulf Samuelsson: Re: FPGA config without boot PROM???
41762: 02/04/07: Thomas: Re: FPGA config without boot PROM???
41763: 02/04/07: Falk Brunner: Re: FPGA config without boot PROM???
42056: 02/04/14: steve synakowski: Re: FPGA config without boot PROM???
42057: 02/04/14: Gregory C. Read: Re: FPGA config without boot PROM???
42060: 02/04/14: Kevin Brace: Re: FPGA config without boot PROM???
42062: 02/04/15: Jim Granville: Re: FPGA config without boot PROM???
42079: 02/04/15: Pete Koziar: Re: FPGA config without boot PROM???
41435: 02/03/28: Noddy: Filter design problem
41522: 02/04/01: <vt313@comsys.ntu-kpi.kiev.ua>: Re: Filter design problem
41545: 02/04/02: Kelvin Hsu: Re: Filter design problem
41437: 02/03/28: Steffen Thieringer: PLLs included in Altera Stratix Devices
41442: 02/03/28: Peter Alfke: Re: PLLs included in Altera Stratix Devices
41441: 02/03/28: praveen: time_sim.vhd and time_sim.sdf
41445: 02/03/28: H.L: core generator bus multiplexer and simulation
41446: 02/03/28: BAM: I need an advice regarding a switch to a Digital Design Career
41449: 02/03/28: Kevin Neilson: Re: I need an advice regarding a switch to a Digital Design Career
41450: 02/03/28: Mike Treseler: Re: I need an advice regarding a switch to a Digital Design Career
41448: 02/03/28: Kevin Brace: Unrecognized LUTs Inserted in A FLEX10KE/ACEX1K Design
41459: 02/03/28: Tullio Grassi: strange RAM timing problem (VirtexE)
41460: 02/03/29: Spam Hater: Re: strange RAM timing problem (VirtexE)
41751: 02/04/06: Jay: Re: strange RAM timing problem (VirtexE)
41756: 02/04/07: Spam Hater: Re: strange RAM timing problem (VirtexE)
41758: 02/04/06: Peter Alfke: Re: strange RAM timing problem (VirtexE)
41766: 02/04/07: Spam Hater: Re: strange RAM timing problem (VirtexE)
41461: 02/03/29: Alexander Miks: Homebuilt Altera-programmer totally dead...
41466: 02/03/29: Russell Shaw: Re: Homebuilt Altera-programmer totally dead...
41468: 02/03/29: Tuomo Auer: Re: Homebuilt Altera-programmer totally dead...
41471: 02/03/29: Alexander Miks: Re: Homebuilt Altera-programmer totally dead...
41473: 02/03/29: Tuomo Auer: Re: Homebuilt Altera-programmer totally dead...
41474: 02/03/29: Colin O'Flynn: Re: Homebuilt Altera-programmer totally dead...
41479: 02/03/29: m0: Re: Homebuilt Altera-programmer totally dead...
41483: 02/03/29: Steve Casselman: Re: Homebuilt Altera-programmer totally dead...
41485: 02/03/29: Colin O'Flynn: Re: Homebuilt Altera-programmer totally dead...
41510: 02/03/31: Joachim Schueth: Re: Homebuilt Altera-programmer totally dead...
41464: 02/03/29: Kevin Brace: Unusually Large Routing Delay From a FF To a Pin in FLEX10KE
41481: 02/03/29: Cyra.Nargolwalla: Re: Unusually Large Routing Delay From a FF To a Pin in FLEX10KE
41467: 02/03/29: Unit Manager: Q: Any Virtex II pro development board on market?
41475: 02/03/29: Tom Loftus: Re: Q: Any Virtex II pro development board on market?
41640: 02/04/04: Vincent Vendramini: Re: Q: Any Virtex II pro development board on market?
41513: 02/04/01: Peter Ormsby: Re: Any Virtex II pro development board on market?
41469: 02/03/29: xcvjb: position
41478: 02/03/29: John_H: Re: position
41489: 02/03/29: xcvjb: Re: position
41472: 02/03/29: Alexander Miks: Where to get MAX7000S
41476: 02/03/29: Tuomo Auer: Re: Where to get MAX7000S
41532: 02/04/01: Ulf Samuelsson: Re: Where to get MAX7000S
41482: 02/03/29: Romans: Xilinx : Mixed-languages design?
41488: 02/03/30: Tim: Re: Xilinx : Mixed-languages design?
41484: 02/03/29: Max Edmand: pipelined correlation block on Virtex2000?
41487: 02/03/29: John_H: Re: pipelined correlation block on Virtex2000?
41558: 02/04/02: Kelvin Hsu: Re: pipelined correlation block on Virtex2000?
41650: 02/04/04: Jonas Thor: Re: pipelined correlation block on Virtex2000?
41490: 02/03/29: tamu.edu: PCI Compliance..
41493: 02/03/30: Peter Alfke: Re: PCI Compliance..
41521: 02/04/01: Austin Franklin: Re: PCI Compliance..
41497: 02/03/30: Kevin Brace: Re: PCI Compliance..
41499: 02/03/30: Mike Treseler: Re: Compiler library ...
41500: 02/03/30: Ken: VirtexII : Any limitation on using LVDS?
41504: 02/03/31: Peter Alfke: Re: VirtexII : Any limitation on using LVDS?
41523: 02/04/01: Austin Lesea: Re: VirtexII : Any limitation on using LVDS?
41501: 02/03/30: Yves Petinot: Compiler library ...
41506: 02/03/31: Peter Alfke: Re: Compiler library ...
41606: 02/04/03: Tim: Re: Compiler library ...
41502: 02/03/30: Tina: Memory design for processor
41505: 02/03/31: Peter Alfke: Re: Memory design for processor
41507: 02/03/31: Digital EE: Orcad Sch f/Xilinx Spartan II
41508: 02/03/31: Keith R. Williams: Re: Orcad Sch f/Xilinx Spartan II
41509: 02/03/31: engr: Re: Orcad Sch f/Xilinx Spartan II
41511: 02/03/31: Aki Niimura: Update: A petition for Synplify's new fature (FPGA synthesis tool)
41527: 02/04/01: John_H: Re: Update: A petition for Synplify's new fature (FPGA synthesis tool)
41550: 02/04/02: sweir: Re: Update: A petition for Synplify's new fature (FPGA synthesis tool)
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