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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Threads Starting Oct 1996
4219: 96/10/01: Peter: Viewlogic 4.1 (DOS) mouse alternatives?
4220: 96/10/01: alain arnaud: Re: Viewlogic 4.1 (DOS) mouse alternatives?
4222: 96/10/01: <daveb@iinet.net.au>: Re: Viewlogic 4.1 (DOS) mouse alternatives?
4225: 96/10/02: Peter: Re: Viewlogic 4.1 (DOS) mouse alternatives?
4231: 96/10/02: Ray Andraka: Re: Viewlogic 4.1 (DOS) mouse alternatives?
4232: 96/10/03: Philip Freidin: Re: Viewlogic 4.1 (DOS) mouse alternatives?
4240: 96/10/03: mis-spelt!: Re: Viewlogic 4.1 (DOS) mouse alternatives?
4243: 96/10/04: Philip Freidin: Re: Viewlogic 4.1 (DOS) mouse alternatives?
4230: 96/10/02: Gavin Melville: Re: Viewlogic 4.1 (DOS) mouse alternatives?
4254: 96/10/05: Jon Harris: Re: Viewlogic 4.1 (DOS) mouse alternatives?
4255: 96/10/05: bob elkind: Re: Viewlogic 4.1 (DOS) mouse alternatives?
4223: 96/10/02: Gavin Melville: Has anyone changed from ViewLogic to Foundation [Q]
4224: 96/10/02: David Decker: Re: Has anyone changed from ViewLogic to Foundation [Q]
4227: 96/10/02: Tony Disanto: Re: Has anyone changed from ViewLogic to Foundation [Q]
4574: 96/11/16: Chris Hart: Re: Has anyone changed from ViewLogic to Foundation [Q]
4228: 96/10/02: P. Athanas: Research Position in Configurable Computing
4229: 96/10/02: Lloyd D. Songne, Jr.: Where can I find pSOS skilled professionals?
4233: 96/10/03: mis-spelt!: Q on Xilinx/Viewsim macros
4234: 96/10/03: Alan Weir: Re: Q on Xilinx/Viewsim macros
4235: 96/10/03: alain arnaud: Re: Q on Xilinx/Viewsim macros
4239: 96/10/03: mis-spelt!: Re: Q on Xilinx/Viewsim macros
4244: 96/10/04: Philip Freidin: Re: Q on Xilinx/Viewsim macros
4257: 96/10/05: mis-spelt!: Re: Q on Xilinx/Viewsim macros
4265: 96/10/07: Paul Hartley: Re: Q on Xilinx/Viewsim macros
4252: 96/10/04: Ray Andraka: Re: Q on Xilinx/Viewsim macros
4266: 96/10/07: Eric Pearson: Re: Q on Xilinx/Viewsim macros
4241: 96/10/03: Stan Hodge: Re: Q on Xilinx/Viewsim macros
4236: 96/10/03: Jackie Meyer: CFP: Memory Technology Design and Testing
4237: 96/10/03: Nick Gent: VHDL for Xilinx designs?
4247: 96/10/04: <patrick@pluto.e-technik.uni-dortmund.de>: Re: VHDL for Xilinx designs?
4302: 96/10/11: David Emrich: Re: VHDL for Xilinx designs?
4353: 96/10/18: Austin Franklin: Re: VHDL for Xilinx designs?
4362: 96/10/20: extra z to stop junk mail: Re: VHDL for Xilinx designs?
4365: 96/10/20: Scott Kroeger: Re: VHDL for Xilinx designs?
4370: 96/10/21: George Noten: Re: VHDL for Xilinx designs?
4371: 96/10/21: Austin Franklin: Re: VHDL for Xilinx designs?
4372: 96/10/21: Lance Gin: Re: VHDL for Xilinx designs?
4376: 96/10/22: extra z to stop junk mail: Re: VHDL for Xilinx designs?
4381: 96/10/22: Austin Franklin: Re: VHDL for Xilinx designs?
4386: 96/10/23: Tim Hubberstey: Re: VHDL for Xilinx designs?
4389: 96/10/23: Kenneth A. Becker: Re: VHDL for Xilinx designs?
4390: 96/10/23: Austin Franklin: Re: VHDL for Xilinx designs?
4396: 96/10/24: Tim Hubberstey: Re: VHDL for Xilinx designs?
4398: 96/10/24: SM Sasaki: Re: VHDL for Xilinx designs?
4408: 96/10/24: Wayne Turner: Re: VHDL for Xilinx designs?
4366: 96/10/20: Austin Franklin: Re: VHDL for Xilinx designs?
4373: 96/10/21: Lance Gin: Re: VHDL for Xilinx designs?
4374: 96/10/22: Andreas Wehr: Re: VHDL for Xilinx designs?
4380: 96/10/22: Austin Franklin: Re: VHDL for Xilinx designs?
4391: 96/10/23: Andreas Wehr: Re: VHDL for Xilinx designs?
4387: 96/10/23: J.Mawer: Re: VHDL for Xilinx designs?
4402: 96/10/24: Simon Bloyce: Re: VHDL for Xilinx designs?
4392: 96/10/23: Erasmo Brenes: Re: VHDL for Xilinx designs?
4395: 96/10/23: Austin Franklin: Re: VHDL for Xilinx designs?
4508: 96/11/06: Erasmo Brenes: Re: VHDL for Xilinx designs?
4406: 96/10/24: extra z to stop junk mail: Re: VHDL for Xilinx designs?
4238: 96/10/03: John Fitzpatrick: QuickLogic
4259: 96/10/06: <sarfati@netvision.net.il>: Re: QuickLogic
4242: 96/10/03: Fred Giorgi: Altera Checksums
4249: 96/10/04: David Pashley: Re: Altera Checksums
4258: 96/10/05: Richard Vireday: Re: Altera Checksums
4267: 96/10/08: Fred Giorgi: Re: Altera Checksums
4245: 96/10/04: jong moo kim: I want best synthesis tool for fpga/cpld.
4246: 96/10/04: jong moo kim: I want best synthesis tool for fpga/cpld.
4248: 96/10/04: Pasquale Corsonello: Reconfigurable hardware
4250: 96/10/04: Don Husby: Re: Reconfigurable hardware
4271: 96/10/08: Don Husby: Re: Reconfigurable hardware
4253: 96/10/04: Ray Andraka: Re: Reconfigurable hardware
4251: 96/10/04: Hui Zhang: FPGA for Reed-Solomon Codec
4262: 96/10/07: Christof Paar: Re: FPGA for Reed-Solomon Codec
4263: 96/10/07: Jason T. Wright: Re: FPGA for Reed-Solomon Codec
4292: 96/10/10: X0033$: Re: FPGA for Reed-Solomon Codec
4327: 96/10/16: Ander Royo Orejas: Re: FPGA for Reed-Solomon Codec
4256: 96/10/05: 1997 International Symposium on Physical Design: CFP: 1997 Intl. Symp. on Physical Design, April 14-16, CA
4260: 96/10/07: Michael Schnell: 1 Download -> alle Mails in allen Global foren weg
4261: 96/10/07: Stuart J Adams: Anyone using Altera MaxPlus VHDL ???
4286: 96/10/09: Mike Treseler: Re: Anyone using Altera MaxPlus VHDL ???
4320: 96/10/14: Petrus Pelser: Re: Anyone using Altera MaxPlus VHDL ???
4268: 96/10/08: mis-spelt!: Viewlogic v4.1 Plotter.exe cmd line usage?
4278: 96/10/09: Pak K. Chan: Re: Viewlogic v4.1 Plotter.exe cmd line usage?
4308: 96/10/12: extra z to stop junk mail: Re: Viewlogic v4.1 Plotter.exe cmd line usage?
4309: 96/10/12: Pak K. Chan: Re: Viewlogic v4.1 Plotter.exe cmd line usage?
4269: 96/10/08: Andrew Valentine: Require micrograph picture of an antifuse
4270: 96/10/08: David Van den Bout: COMMERCIAL: workshop on designing with FPGAs
4272: 96/10/08: Jorge P. Seidel: Re: Reversible LFSR?
4280: 96/10/09: Andreas Doering: Re: Reversible LFSR?
4273: 96/10/08: John L. Smith: Reversible LFSR?
4274: 96/10/08: Jorge P. Seidel: Re: Reversible LFSR?
4279: 96/10/09: Philip Freidin: Re: Reversible LFSR?
4276: 96/10/09: Philip Freidin: Re: Reversible LFSR?
4300: 96/10/11: Rich Hatcher: Re: Reversible LFSR?
4275: 96/10/08: Andrew Siska: Atmel Serial Configuration EEPROM - AT17C128
4281: 96/10/09: Julian Cox: Re: Atmel Serial Configuration EEPROM - AT17C128
4287: 96/10/09: Andrew Siska: Re: Atmel Serial Configuration EEPROM - AT17C128
4277: 96/10/09: Matthew J Myers: 16x16 multiplier needer (Altera or VHDL)
4282: 96/10/09: Julian Cox: Re: 16x16 multiplier needer (Altera or VHDL)
4285: 96/10/09: Michael Vincze: Re: 16x16 multiplier needer (Altera or VHDL)
4283: 96/10/09: Rynier van der Watt: Xilinx Startup symbol instantiation in VHDL using Viewlogic ?
4288: 96/10/10: H.Spaargaren: Re: Xilinx Startup symbol instantiation in VHDL using Viewlogic ?
4284: 96/10/09: Richard Jozefowski: ORCA 2C10A - RAM placement advice
4291: 96/10/10: David Dea: Re: ORCA 2C10A - RAM placement advice
4314: 96/10/14: Don Husby: Re: ORCA 2C10A - RAM placement advice
4289: 96/10/10: William J. Wolf: FPGA Web Links
4296: 96/10/11: Brad Hutchings: Re: FPGA Web Links
4297: 96/10/11: John L. Smith: Re: FPGA Web Links
4290: 96/10/10: Sebastian H Ziesler: help: max+ edif input problems
4307: 96/10/12: John Edelman: Re: help: max+ edif input problems
4293: 96/10/11: Dan Diekhoff: JOB: US-IN. VHDL/ASIC Design. HW/SW Integration debug. FPGAs. - ddiekhof@notes.techni-source.com
4294: 96/10/11: arif tumer: Make Money
4295: 96/10/11: Frederic Gruau: Next conf
4298: 96/10/11: Peter Alfke: Serial EEPROM problem
4299: 96/10/11: Dan Bartram: Info/opinions wanted for PCI interface in an FPGA
4311: 96/10/13: Wayne Turner: Re: Info/opinions wanted for PCI interface in an FPGA
4333: 96/10/17: Austin Franklin: Re: Info/opinions wanted for PCI interface in an FPGA
4400: 96/10/24: Dan Bartram: Re: Info/opinions wanted for PCI interface in an FPGA
4427: 96/10/28: Austin Franklin: Re: Info/opinions wanted for PCI interface in an FPGA
4439: 96/10/29: Dan Bartram: Re: Info/opinions wanted for PCI interface in an FPGA
4459: 96/11/01: Austin Franklin: Re: Info/opinions wanted for PCI interface in an FPGA
4301: 96/10/11: Bruce Oakley: Xilinx XACT Performance Appl. Note?
4319: 96/10/14: Marc Baker: Re: Xilinx XACT Performance Appl. Note?
4303: 96/10/11: David Emrich: Re: Xilinx Startup symbol instantiation in VHDL ... ?
4304: 96/10/12: David T. Wang: Async with FPGA?
4305: 96/10/12: extra z to stop junk mail: Re: Async with FPGA?
4310: 96/10/13: Ray Andraka: Re: Async with FPGA?
4306: 96/10/12: Scott Kroeger: Re: Async with FPGA?
4538: 96/11/11: Tim Forcer: Re: Async with FPGA?
4575: 96/11/16: Michael Baxter: Re: Async with FPGA?
4587: 96/11/18: Bill Mangione-Smith: Re: Async with FPGA?
4589: 96/11/18: Michael Baxter: Re: Async with FPGA?
4591: 96/11/19: Rick Filipkiewicz: Re: Async with FPGA?
4608: 96/11/20: Michael Baxter: Re: Async with FPGA?
4622: 96/11/21: Scott A. Hauck: Re: Async with FPGA?
4315: 96/10/14: John L. Smith: Re: Async with FPGA?
4312: 96/10/13: Alex 00009: 50 Mhz 24 CHANNEL LOGIC ANALYZER only $199
4313: 96/10/14: John Vickers: Seeking 16V8: Vcc=3.0-5.0V: Zero standby power.
4325: 96/10/16: extra z to stop junk mail: Re: Seeking 16V8: Vcc=3.0-5.0V: Zero standby power.
4377: 96/10/22: <granville@decus.org.nz>: Re: Seeking 16V8: Vcc=3.0-5.0V: Zero standby power.
4316: 96/10/14: Linda Boyd: COURSES: High Level Design Using VHDL, Beaverton, Oregon
4317: 96/10/14: Linda Boyd: COURSES: High Level Design Using Verilog, Beaverton, Oregon
4318: 96/10/14: Moshe Zalcberg: LPM standard support?
4322: 96/10/15: Veli-Matti Karppinen: Re: LPM standard support?
4321: 96/10/14: Andrew Siska: Update on Atmel AT17C128 Problem
4324: 96/10/15: Dan Bartram: Re: Update on Atmel AT17C128 Problem
4334: 96/10/17: Rene Bakker: Re: Update on Atmel AT17C128 Problem
4338: 96/10/17: Don Husby: Re: Update on Atmel AT17C128 Problem
4323: 96/10/15: Thomas Kobler: Xilinx xchecker.exe and Windows NT
4326: 96/10/16: Rene Bakker: Re: Xilinx xchecker.exe and Windows NT
4335: 96/10/17: Marc Baker: Re: Xilinx xchecker.exe and Windows NT
4354: 96/10/18: David Dye: Re: Xilinx xchecker.exe and Windows NT
4388: 96/10/23: Geir Ertzaas: Re: Xilinx xchecker.exe and Windows NT
4405: 96/10/24: extra z to stop junk mail: Re: Xilinx xchecker.exe and Windows NT
4340: 96/10/17: Jon Harris: Re: Xilinx xchecker.exe and Windows NT
4375: 96/10/22: Jim Burns: Re: Xilinx xchecker.exe and Windows NT
4328: 96/10/16: Stan Baker: WinEDA Plenary Session
4329: 96/10/16: Stan Baker: Conference Sessions Open at WinEDA
4330: 96/10/16: Durham 206 Mac 7200: PCI compliant ?
4332: 96/10/17: Austin Franklin: Re: PCI compliant ?
4331: 96/10/16: Rafiki Kim Hofmans: xc4000 and 2 clocks
4336: 96/10/17: Martin d'Anjou: Re: xc4000 and 2 clocks
4339: 96/10/17: Jason T. Wright: Re: xc4000 and 2 clocks
4346: 96/10/18: Martin d'Anjou: Re: xc4000 and 2 clocks
4337: 96/10/17: Peter McLeod Wilcox: Re: xc4000 and 2 clocks
4351: 96/10/18: Philip Freidin: Re: xc4000 and 2 clocks
4341: 96/10/18: Eric Edwards: What are I/O's doing prior to configuration?
4345: 96/10/18: Ray Andraka: Re: What are I/O's doing prior to configuration?
4347: 96/10/18: Scott Kroeger: Re: What are I/O's doing prior to configuration?
4349: 96/10/18: Austin Franklin: Re: What are I/O's doing prior to configuration?
4383: 96/10/22: Marc Baker: Re: What are I/O's doing prior to configuration?
4384: 96/10/22: Peter Alfke: Re: What are I/O's doing prior to configuration?
4342: 96/10/18: Shawn Lee: (no subject)
4352: 96/10/18: Philip Freidin: Re: (no subject) attempted humor
4431: 96/10/28: Steven K. Knapp: PCI Compliance in FPGAs
4343: 96/10/18: Shawn Lee: (no subject)
4344: 96/10/17: Scott Kroeger: Re: (no subject)
4350: 96/10/18: Austin Franklin: Re: (no subject)
4348: 96/10/18: Jimcde: price conversion from FPGA to gate array
4363: 96/10/20: extra z to stop junk mail: Re: price conversion from FPGA to gate array
4355: 96/10/19: 1997 International Symposium on Physical Design: CFP: 1997 Intl. Symp. on Physical Design, April 14-16, CA
4356: 96/10/19: Peter Fenn: Comment/opinion on ACTEL's annonced SPGA devices?
4357: 96/10/19: Wong Man Kit: Anyone use Lattice's CPLD
4358: 96/10/19: Steven J. Ackerman: Re: Anyone use Lattice's CPLD
4359: 96/10/19: ATOMROB: Announcing Workview Office Student Edition
4360: 96/10/19: Yun Feng: help Flex 10K configuration
4361: 96/10/19: Tim Green: Re: help Flex 10K configuration
4364: 96/10/20: Rune Baeverrud: Re: help Flex 10K configuration
4367: 96/10/21: Austin Franklin: Has anyone ever used a C -> Xilinx netlister?
4397: 96/10/24: Jan Gray: Re: Has anyone ever used a C -> Xilinx netlister?
4429: 96/10/28: Mark Shand: Re: Has anyone ever used a C -> Xilinx netlister?
4368: 96/10/21: Tony Hirst: Evolvable hardware/evolutionary elecronics
4369: 96/10/21: John Maher: VHDL Aware Editor
4378: 96/10/22: Reto Zimmermann: Multipliers on Xilinx FPGAs
4379: 96/10/22: <matt@esquire>: Re: Multipliers on Xilinx FPGAs
4432: 96/10/28: Steven K. Knapp: Re: Multipliers on Xilinx FPGAs
4446: 96/10/30: Wayne Turner: Re: Multipliers on Xilinx FPGAs
4484: 96/11/04: Simon: Re: Multipliers on Xilinx FPGAs
4382: 96/10/22: Dipl.-Ing. D. Lenz: Searching Demoboard for Altera Flex8000
4401: 96/10/24: Alfred Fuchs: Re: Searching Demoboard for Altera Flex8000
4385: 96/10/23: Larry Chen: Motorola 68HC16 background debugger
4393: 96/10/23: Lance Gin: Mentor B.2 and XACT 5.2.1 ?
4394: 96/10/23: Andrew Plumb: Suggestions for inexpensive FPGA EVM (new and used)?
4399: 96/10/24: tendy the: Integer Multiplier
4430: 96/10/28: Brad Taylor: Re: Integer Multiplier
4518: 96/11/08: Neal Becker: Re: Integer Multiplier
4403: 96/10/24: Dennis Morel: Synplicity vs. FPGA Express
4410: 96/10/25: alain arnaud: Re: Synplicity vs. FPGA Express
4413: 96/10/25: Austin Franklin: Re: Synplicity vs. FPGA Express
4415: 96/10/25: Wayne Turner: Re: Synplicity vs. FPGA Express
4418: 96/10/25: Jean-Michel Vuillamy: Re: Synplicity vs. FPGA Express
4416: 96/10/25: Brad Hutchings: Re: Synplicity vs. FPGA Express
4443: 96/10/30: alain arnaud: Re: Synplicity vs. FPGA Express
4447: 96/10/30: Wayne Turner: Re: Synplicity vs. FPGA Express
4404: 96/10/24: Jonny Cochrane: win95 env variables
4411: 96/10/25: Marek Skotnica: Re: win95 env variables
4407: 96/10/24: Acquisition Systems: New PCI Reconfigurable Hardware available
4409: 96/10/24: Eric Holmberg: Altera FPGA's
4414: 96/10/25: Wayne Turner: Re: Altera FPGA's
4425: 96/10/28: Eric Holmberg: Re: Altera FPGA's
4448: 96/10/30: Shawn Joel Dube: Configuring FPGA before PCI accesses config regs
4412: 96/10/25: Gurpreet S. Bhullar: 4K Carry Logic & XAPP NOTE...
4417: 96/10/25: Paul Donachy: New user
4419: 96/10/26: Austin Franklin: Re: New user
4420: 96/10/26: Steve Dewey: Altera Configuration EPROM Equivalents
4423: 96/10/28: Philip Freidin: Re: Altera Configuration EPROM Equivalents
4441: 96/10/29: Paul S Secinaro: Re: Altera Configuration EPROM Equivalents
4473: 96/11/02: Martin Mason: Re: Altera Configuration EPROM Equivalents
4426: 96/10/28: Julian Cox: Re: Altera Configuration EPROM Equivalents
4449: 96/10/30: John McDougall: Re: Altera Configuration EPROM Equivalents
4421: 96/10/27: Jeffrey M. Arnold: CFP: FCCM'97 Int'l Symp on Custom Computing Machines, 16-18 April Napa, CA
4422: 96/10/27: 1997 International Symposium on Physical Design: CFP: 1997 Intl. Symp. on Physical Design, April 14-16, CA
4424: 96/10/27: Xiangdong Li: PCI-compliant VHDL module
4440: 96/10/29: Shawn Joel Dube: Re: PCI-compliant VHDL module
4428: 96/10/28: Laurent Moll: Free NT device driver (with sources)
4433: 96/10/29: <hajimow@unconfigured.xvnews.domainSayed>: Question on Wavelet implementation
4437: 96/10/29: John C. Peck, Jr.: Re: Question on Wavelet implementation
4434: 96/10/29: <granville@decus.org.nz>: Re: VHDL for Xilinx designs?
4436: 96/10/29: Austin Franklin: Re: VHDL for Xilinx designs?
4444: 96/10/30: George Noten: Re: VHDL for Xilinx designs?
4445: 96/10/30: Don Husby: Re: VHDL for Xilinx designs?
4452: 96/10/30: ESPSys: Re: VHDL for Xilinx designs?
4456: 96/10/31: Austin Franklin: Re: VHDL for Xilinx designs?
4465: 96/11/01: Don Husby: Re: VHDL for Xilinx designs?
4474: 96/11/03: Peter - one extra v to stop junk mail: Re: VHDL for Xilinx designs?
4435: 96/10/29: Chris Herron: Novice: Flex 8000 ?
4438: 96/10/29: Richard Schwarz: Need fast/small SRAMS
4442: 96/10/29: Eric Holmberg: Altera EPX880
4450: 96/10/30: John McDougall: Anyone experience Altera 10k
4451: 96/10/30: William Vollrath: Altera & Verilog
4454: 96/10/31: Steve Wiseman: Re: Altera & Verilog
4457: 96/10/31: Kevin D. Drucker: Re: Altera & Verilog
4453: 96/10/31: Todd Peterson: FREE ELECTRONICS DIRECTORY
4455: 96/10/31: Steve Wiseman: Weird pre-config VCC-GND short in Altera or Xilinx
4458: 96/10/31: Marc Boulais: Re: Weird pre-config VCC-GND short in Altera or Xilinx
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Compare FPGA features and resources
Threads starting:
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