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I did a lot of work with an asynchronous technique called Transition Signalling. I was doing this in 1988-89, with Xilinx XC3000 FPGAs. While I was working with primary references in the literature, as luck would have it, during the Summer of 1989, Ivan Sutherland won the ACM Turing Award for development of Transition Signalling. This, plus several exemplary circuits, are covered in an ACM issue of approximately that time. These circuits are very interesting in that all logic acts like a FIFO, and systems of these circuits propagate signals at their naturally fastest rate. They do not incur metastable conditions in flip-flops. The aforementioned ACM article describes the circuit operation very well. My specific application was a small tightly-coupled multiprocessor which needed to have one moderate-size DRAM memory that was shared by all the requesters. In the application there were also alternative requesters which had a different operating rate than the CPUs. What I was trying to build was an asynchronous, but self-policing timing system for the memory, where the requester would use the Transition Signalling logic to "harmonize" the DRAM operations to it's natural speed. This meant there could be no central clock for the memory, it had to be self-timed, driven from the signalling rate of each requester individually. Since the assorted (independant) synchronous requesters (CPUs, and some imaging interfaces) would not operate the memory faster than it's rated speed, and since each of the Transition Signalling blocks operated with a Tpd way faster than any Tpw|clk that would be encountered, the whole memory controller ensemble worked "naturally" with this asynchronous logic, stimulated by the various synchronous requesters. The big benefit of the self-timed memory controller was not needing cross-boundary sychronizers for every set of signals exchanged at a CPU-memory or interface-boundary. Hence, the DRAM memory did not have a clock that was different than the CPU clocks, which were different than the imaging interface clocks, etc. In fact, since memory was the sole interface for CPU-to-CPU messaging, the CPUs didn't even have to have the same clock source. The FPGA logic tricks for Transition Signalling are interesting, but straightforward. In XC3000, to deal with dual-edge sensitivity implied in the signalling protocol, one creates an edge-to-pulse (ETP) converter using CLB logic and a flip-flop. However the return feedback needed to produce clocking events occurs through a FPGA global buffer. So the ETP flip-flop sources a signal to a BUFGP, and the returning feedback is sensed from the long metal line after the BUFGP. Such ETP circuits operate other clocked logic through the metal-lines of the global clock net on the FPGA. This clocked logic may happen to see an irregular clock, but it will have Tpw|H and Tpw|L minima that are safely far from pushing the FPGA circuitry AC constraints. In addition, this clocked logic will propagate signals traversing between like-clocked flip-flop ranks, and as the controlling events are really "locally synchronous," in that no AC constraint is ever violated. These FPGA circuits were in no way slower than conventional clocking approaches -- I obtained (using what is now really old silicon) 33 MHz system-wide Fmax with zero metastability errors. That is to say, the pin-to-pin maximum signalling between FPGAs, was supportable at 33 MHz. A memory controller for operation with 25 MHz RISC CPUs of the day was perfectly workable. In my experience, asynchronous circuit techniques seem to always arouse passions; I'd only like to say that I had a need for detemporalizing one important system element, and it worked to spec, and well. Ivan's paper tells quite a lot about the system approach itself. The mechanism I've described for FPGA diverges from Transition Signalling according to the ACM paper quite a lot in the operation of the apparatus, due to the limits of FPGA architecture. In classical Transition Signalling, EVERY logic element (encoder, decoder, mux, etc.) works according the dual-edge approach. In FPGA, one must build functions at a larger level of granularity (state-machine, timing generator, address counter, FIFO, etc.), and due to the aforementioned technique for accomplishing dual-transition clocking on nominally single-edged flip-flops, there are limits to the circuit nesting depth, since there are few global buffers. Circuits made in VLSI using this technique would have FIFO-action at every single stage containing anything doing logic, allowing a dataflow action that is streamlike. In FPGA, the circuits tended to be "big chunk logic" and "flat" in cascaded ranking. Hence, all switching was more group-like, traversing many fewer cascaded ranks of flip-flops; through-the-chip pin-to-pin latency was typically 3-4 stages maximum, effectivey a shallow-depth pipeline. Such an approach was actually relatively ideal for a high-performance, low-latency, self-timed memory controller, where multiple independant requesters on independant timebases had to be served. I suspect that current modern FPGAs are all adapatable to this same technique. Cheers, Michael BaxterArticle: 4576
Greetings! E-LAB Digital Engineering, Inc. is pleased to make freely available our new Electronics Internet Resource Directory! This directory is a collection of many internet sites of use to electronics builders, designers, and engineers. It is divided into 40 categories, with each category containing many hot-links to companies and/ or web pages containing information on topics from Compilers to Code Examples to Components Distributors. The directory is available at http://www.netins.net/showcase/elab You WILL want to set a bookmark! We also invite you to check out our products, such as our new line of integrated circuits for embedded design. Thanks, Todd Peterson E-LAB Digital Engineering, Inc.Article: 4577
Hi, Does anyone over here know to convert EDIF netlist file to BLIF netlist file ? Please forward your reply to: poladia@suntan.eng.usf.edu RSVP. Thanks Ketan PoladiaArticle: 4578
Vincent Rowley <vrowley@hexavision.com> wrote in article > We are looking for a VHDL code editor for Windows NT platform. > Accolade Design sells a package which is a full featured VHDL simulator integrated with a very nice VHDL mode editor. Errors in the compile will jump directly to the line in the editor where the error was. The editor alone is about $500.00 There are several Lisp extensions to emacs which work well under NT also. I am sending this from my daughters computer at home so I don't have the exact names or addresses. Wilbur Harvey wnh@sinewave.comArticle: 4579
ILLEGAL SCAM!! YOU WILL NEVER SEE A DOLLAR OF YOUR MONEY AGAIN!!! READ WHY! http://www.usps.gov/websites/depart/inspect/chainlet.htm Chain letters are a form of gambling, and sending them through the mail or delivering them in person or by computer, violates Title 18, United States Code, Section 1302, the Postal Lottery Statute. (A copy of this chain letter has been sent to this person's Internet provider and Cc'd to jccheezum@uspis.gov, The U.S. Postal Inspection Service, with a list of all names involved. Another copy of all names and addresses has been forwarded to a local branch of the Internal Revenue Service.) A chain letter is a "get rich quick" scheme that promises that your mail box will soon be stuffed full of cash if you decide to participate. You're told you can make thousands of dollars every month if you follow the detailed instructions in the letter. A typical chain letter includes names and addresses of several individuals whom you may or may not know. You are instructed to send a certain amount of money--usually $5--to the person at the top of the list, and then eliminate that name and add yours to the bottom. You are then instructed to mail copies of the letter to a few more individuals who will hopefully repeat the entire process. The letter promises that if they follow the same procedure, your name will gradually move to the top of the list and you'll receive money -- lots of it. There's at least one problem with chain letters. They're illegal if they request money or other items of value and promise a substantial return to the participants. Chain letters are a form of gambling, and sending them through the mail (or delivering them in person or by computer, but mailing money to participate) violates Title 18, United States Code, Section 1302, the Postal Lottery Statute. (Chain letters that ask for items of minor value, like picture postcards or recipes, may be mailed, since such items are not things of value within the meaning of the law.) Recently, high-tech chain letters have begun surfacing. They may be disseminated over the Internet, or may require the copying and mailing of computer disks rather than paper. Regardless of what technology is used to advance the scheme, if the mail is used at any step along the way, it is still illegal. The main thing to remember is that a chain letter is simply a bad investment. You certainly won't get rich. You will receive little or no money. The few dollars you may get will probably not be as much as you spend making and mailing copies of the chain letter. Chain letters don't work because the promise that all participants in a chain letter will be winners is mathematically impossible. Also, many people participate, but do not send money to the person at the top of the list. Some others create a chain letter that lists their name numerous times--in various forms with different addressee. So, in reality, all the money in a chain is going to one person. Do not be fooled if the chain letter is used to sell inexpensive reports on credit, mail order sales, mailing lists, or other topics. The primary purpose is to take your money, not to sell information. "Selling" a product does not ensure legality. Be doubly suspicious if there's a claim that the U.S. Postal Service or U.S. Postal Inspection Service has declared the letter legal. This is said only to mislead you. Neither the Postal Service nor Postal Inspectors give prior approval to any chain letter. Participating in a chain letter is a losing proposition. Turn over any chain letter you receive that asks for money or other items of value to your local postmaster or nearest Postal Inspector. Write on the mailing envelope of the letter or in a separate transmittal letter, "I received this in the mail and believe it may be illegal."Article: 4580
> I'm using Xilinx's Foundation for VHDL. > I'm trying to figure out how to change a 4 bit add to have a carry in > and carry out. (I can't find anything like this in my VHDL books). That would be real easy with a schematic! ;-) BTW...do the Foundation tools allow you to do simulation with full timing? I heard that they don't... Austin Franklin ..darkroom@ix.netcom.com.Article: 4581
Hi, I'm Steven Esau <stevene@asymetrix.com> the general counsel of Asymetrix Corporation. Mark J. Christie <mapsing@pacific.net.sg> is the mastermind behind this scam to sabotage Jeffrey Tay. I gave Jeffrey Tay a letter to authorize him to distribute KaiZenWare but Mark J. Christie secretly sabotaged Jeffrey Tay by spreading lies and rumours that KaiZenWare is illegal. I'll ask Paul Allen to sack Mark J. Chrisite. Asymetrix will very soon announce on its home page the official recognition of KaiZenWare as the copyright property of Jeffrey Tay. KaiZenWare can be developed to run on any version of ToolBook - v1.5, v3.0, v.4.0 and the ToolBook II series and all future versions of ToolBook and MultiMedia ToolBook. Watch out for Asymetrix's announcement. Thank you. ------------------------------------ Confession By Mark J. Christie below: Mother! Please don't shoot! I'll confess! I'll confess! (Mark J. Christie's mother is pointing a gun at his head and threatening to blow off his brain if he does not come clean). Please forgive me Steven Esau (Steven is the general counsel of Asymetrix Corporation, USA <stevene@asymetrix.com>), my mom will be visiting you later. This is what happened and I emphasize this is the absolute truth. ***The Objective - Get Jeffrey Tay's software called KaiZenWare Jeffrey Tay created a multimedia authoring tool called KaiZenWare in 1993. However, he has not released it for a variety of reasons. This year (1996) we came to know about it and wanted to get hold of KaiZenWare but we did not succeed. He found a company interested in marketing his software but we sabotaged him by telling that company that KaiZenWare violates Asymetrix's copyright without even seeing KaiZenWare (remember he refused to let go of his software). Details of this can be found at: http://www.ets.bris.ac.uk/comments/21612.htm. The question is: How to get hold of Jeffrey's Tay software called KaiZenWare? We hatched out a plot to lure him to release his software called KaiZenWare. This is how the plot works: Stage 1 we gave him a letter from Steven Esau, general counsel of Asymetrix Corporation, USA <stevene@asymetrix.com> which authorized him to distribute his software called KaiZenWare. Stage 2 we waited for him to fall for our trap. He started marketing his software called KaiZenWare on the Internet in Aug 1996 and we proceeded to download a copy for our own reference so that we can copy his ideas. Stage 3 whenever someone enquired about KaiZenWare we will tell them that it is illegal (members of the ToolBook mailing list have been told in Aug 1996 that it is illegal) and we refuse to acknowledge the fact that KaiZenWare is an exception and that Steven Esau has indeed sent Jeffrey Tay a letter to authorize the distribution of KaiZenWare. Stage 4 we keep totally quiet about this dual-reality. Jeffrey Tay is the only one who knows of the letter from Steven Esau. Jeffrey Tay does not know that members of the ToolBook mailing list thinks it is illegal. Jeffrey Tay does not know that we spread words that it is illegal. Stage 5 we will carry on this charade and will ensure that nobody buys KaiZenWare because they think it is illegal. Jeffrey Tay can spend the rest of his life wasting time and money marketing KaiZenWare but nobody will buy because they think it is illegal. Unfortunately, Jeffrey Tay found out and complained to members of the ToolBook mailing list. Our good friend who owns the list speedily arranged to forbid Jeffrey Tay from posting articles to members of this list even though he has just subscribed to the list. The idea is to gag Jeffrey Tay and to let everyone else say bad things about KaiZenWare and Jeffrey Tay and ensuring that Jeffrey Tay does not have a chance to ask questions and answer questions. Is this cruel? This is the world of business and it is necessarily dirty and cruel. I have no sympathy for Jeffrey Tay because I also want to copy his ideas. I also want to make lots of money. Who cares about Jeffrey Tay even though his software called KaiZenWare was developed and tested in 1993? Jeffrey Tay's job is to prove that his software is good and then our job is to steal his idea and prevent him from selling KaiZenWare by sabotaging him secretly. Please broadcast this message to everyone on the Internet. Jeffrey Tay is a one-man show working from home and he needs all the help he can get. Steven Esau has to answer one question: Did he send a letter to Jeffrey Tay authorizing Jeffrey Tay to distribute KaiZenWare? Thank you. P.S. To find out about KaiZenWare, use Excite and HotBot and use "kaizenware" as the keyword to search the database.Article: 4582
In article 6e84d9ce@drt1, "Austin Franklin" <darkroom@ix.netcom.com> writes:
>> I'm using Xilinx's Foundation for VHDL.
>> I'm trying to figure out how to change a 4 bit add to have a carry in
>> and carry out. (I can't find anything like this in my VHDL books).
>
>That would be real easy with a schematic! ;-)
Schematic, schematic, schematic, uuhh, I always read schematic.
When it's so real easy with schematic, then show it in this newsgroup ;-)
This another disadvantage for schematics!
So let me show how easy with a HDL. In this case VHDL, not Verilog.
But same nearly with verilog...and this works with Synopsys.
For other tools you need to change the "use IEEE.std_logic_unsigned.all;" clause
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity ADDER is
generic(WIDTH: integer := 4);
port(OP1 : in std_logic_vector(WIDTH - 1 downto 0);
OP2 : in std_logic_vector(WIDTH - 1 downto 0);
CI : in std_logic;
SUM : out std_logic_vector(WIDTH - 1 downto 0);
CO : out std_logic);
end ADDER;
architecture BEHAVE of ADDER is
signal SUM_TEMP : std_logic_vector(WIDTH downto 0);
signal OP1_TEMP : std_logic_vector(WIDTH downto 0);
signal OP2_TEMP : std_logic_vector(WIDTH downto 0);
begin
OP1_TEMP <= '0' & OP1;
OP2_TEMP <= '0' & OP2;
SUM_TEMP <= OP1_TEMP + OP2_TEMP + CI;
CO <= SUM_TEMP(WIDTH);
SUM <= SUM_TEMP(WIDTH - 1 downto 0);
end BEHAVE;
Hope this helps,
Andi
Article: 4583Chris Hart wrote: > > I'm using Xilinx's Foundation for VHDL. > I'm trying to figure out how to change a 4 bit add to have a carry in > and carry out. (I can't find anything like this in my VHDL books). > > Ie currently I have something like (from memory) > > signal A,B,C : STD_LOGIC_VECTOR (3 downto 0); > signal C_IN, C_OUT : STD_LOGIC; > ..... > > A <= B + C ; > > and I want something like > > A with C_OUT <= A + B + C_IN ; > > Anyone know how to do this? > > Cheers > Chris Hart - chris.hart@iee.org If you have synopsys, try setting the variable 'hdlin_use_cin' to true (1). This is undocumented (at least in the 3.4b online docs), and you get a "defined new variable" (or something like that) warning when you do it. I found this tip in the Solvit! database. If you have access to Solvit!, pull article SYNTH-902. -- ....__.....__.................................................................. ...| |...| |... Theodore L. Boydston IV . .__| |___| |... . _ /\ /\ _|__ Harris Corporation, GASD email: tboydsto@harris.com . ._\/ \/__\/ |... PO BOX 94000, MS: 102-4823 voice: (407) 729-7999 . ...| |...| |... Melbourne, FL 32902 fax : (407) 729-2782 . ...|__|...|__|.................................................................Article: 4584
In a paper from Jonathan Rose et al. i found references to FPGA devices from GEC Plessey (ERA60100), Plus Logic (FPGA2040) and Toshiba. Does anyone know, if these devices are existent in reality? Or do they only exist on paper? And by the way: I have some data sheets on FPGAs from National Semiconductor. They look like a second source of Atmel's FPGAs. Did these FPGAs reach production? Markus Wannemacher FernUniversitaet Hagen, GermanyArticle: 4585
Markus Wannemacher wrote: > And by the way: I have some data sheets on FPGAs from National > Semiconductor. > They look like a second source of Atmel's FPGAs. Did these FPGAs > reach production? > They are in production. The NSC parts are distributed by Sea Cliff Technology. The rep there is Ed Browder 408/522-8716. Both the Atmel and NSC parts are descendants of the Concurrent Technology design. There are some minor differences between the Atmel and NSC parts, that depending on the exact application might be a help or a hinderance. Those differences are in the permitted connections to local busses. The Atmel design permits a cell to simultaneously have an input from one local bus and an output to another, but restricts turn cell connections as a result. There is also a minor difference in the bus repeaters...the NSC part allows you to change direction of the bus signal at the repeater using the express bus while Atmel does not. -Ray Andraka, P.E. Chairman, the Andraka Consulting Group 401/884-7930 Fax 401/884-7950 email randraka@ids.net http://www.ids.net/~randrakaArticle: 4586
>Is there not any VHDL code available for UARTs. You would then be able >to select the appropriate or general solution by importing/commenting out >the relevant architectures. There must have been an engineer somewhere >who has written some UART VHDL ??? There have been lots, but the designs are owned by one or another company. One firm I know sells a multi-port product which has a XC3030 on each port, and by uploading different configs into these FPGAs they can select each port to be async, sdlc, bisync, etc. So someone had to design all these different UARTs. Peter. Return address is invalid to help stop junk mail. E-mail replies to z80@digiserve.com.Article: 4587
Michael Baxter <mbaxter@best.com> wrote in article <328E328C.5C61@best.com>... > I did a lot of work with an asynchronous technique called Transition > Signalling. I was doing this in 1988-89, with Xilinx XC3000 FPGAs. > While I was working with primary references in the literature, as luck > would have it, during the Summer of 1989, Ivan Sutherland won the ACM > Turing Award for development of Transition Signalling. This, plus > several exemplary circuits, are covered in an ACM issue of > approximately that time. Hmmm... I was under the impression that the micropipeline etc stuff Sutherland was doing was relatively new. I'm pretty sure his turing award was for the graphics work. BillArticle: 4588
Austin Franklin wrote: > > > BTW...do the Foundation tools allow you to do simulation with full timing? > I heard that they don't... > > Austin Franklin > ..darkroom@ix.netcom.com. Foundation simulator does accept full back annotated timing from placed/routed design. However, on startup the simulator wants to overwrite the timing info, you have to tell it no. -- John L. Smith, Pr. Engr. | Sometimes we are inclined to class Univision Technologies, Inc. | those who are once-and-a-half witted 6 Fortune Dr. | with the half-witted, because we Billerica, MA 01821-3917 | appreciate only a third part of their wit. jsmith@univision.com | - Henry David ThoreauArticle: 4589
I think Bill you're probably right, my recollection is probably faulty wrt to Ivan's Turing Award in that I likely misremembered his bio, in relation to the aforementioned micropipeline article which listed it. The micropipeline article reference is approximately right, however, e.g. sometime in the Summer of 1989. I was lucky enough meet Ivan Sutherland circa 1987, and to watch at that time a 16mm movie about his "Sketchpad" from more than two decades earlier. That was electric. Thank-you for pointing my error out, as we should indeed honor the pioneers in computing. Cheers, Michael BaxterArticle: 4590
Hi, I have just started investigating designing using fpga's, cplds etc and was wondering if there are any advantages at all in purchasing third party software (ie viewlogic, mentor, cadence, veribest etc). In my case, the most likely technologies used would be Altera and Xilinx. As I understand it, I must use their tools (Max+Plus and XACT) to place and route, obtain timing etc). These tools seem to come with schematic capture, vhdl simulators, synthesis engines etc (a complete design environment?). Is there any advantage in using the major CAD vendors for these tools? (ie schematic capture, simulation, synthesis). Thanks, Phil.Article: 4591
Re Transition Logic: Is the relevant ACM paper(s) online anywhere ?Article: 4592
Julian Cox (CoxJA@augustsl.demon.co.uk) wrote: : deand@ontrack.com (Dean Dunnigan) wrote: : >I'm currently working with an Altera 880 running at 100 MHz : >but this is not going to be fast enough. Does anyone know : >of an FPGA currently available or available soon that can : >handle clock speed in excess of 100 MHz?? : > : >Thanks in advance! : > If, as I assume, you are talking about the FLASH logic EPX880 (ex-Intel) parts I'm using now this is much faster than by Altera data book would allow. For the -10 parts with a Tco=6.5nsec. & Tsu=6nsec this gives a max frequency of 80MHz. Have you got some -7 parts ? _________________________________________________________________________ Dr. Richard Filipkiewicz phone: +44 171 700 3301 Algorithmics Ltd. fax: +44 171 700 3400 3 Drayton Park email: rick@algor.co.uk London N5 1NU EnglandArticle: 4593
FOR IMMEDIATE RELEASE BREAKTHROUGH COMPUTER SYSTEM TO BE INTRODUCED ON DEC 2 New Computer, with New Architecture, Reportedly Outruns Pentium 166 by 180 x A potentially revolutionary computer technology unlike any other seen before will be introduced on December 2 at New York’s St. Regis Hotel at 10:15 AM. On that date, a new type of neural computer with dozens of parallel processors, will run 180x faster than the Pentium 166. The computer, to be called the RICHTER PARADIGM Computer, is based on a new type of architecture that has already been previewed by select editors at key computer, electronics and high-tech trade publications. The computer will be presented, marketed and manufactured by a San Jose-based high-tech company that will soon be listed on NASDAQ. If you have any interest in computers and its potential on applications, then this is a must-see demonstration. Some have already called this the most unique innovation to the computer industry since Oracle was introduced. Highlights of the Press Conference are Expected to Include: A side-by-side hands-on demonstration of the new computer versus a computer running with the Pentium 166; Introduction of the new computer, its architecture and its software; Real-time arbitrage of the commodities market and other demonstrations requiring real-time analysis; TIME: 10:15 AM DATE: Monday, December 2 PLACE:St. Regis Hotel 2 East 55th Street CONTACTS:Peter Collins/Brian Bailey Rubenstein Associates, Inc. pcolli@rubenstein.com or bbaile@rubenstein.comArticle: 4594
Frustrated with viewing DSP signals as hex, I've recently added MatLab test vectors to my bag of tricks. Its like taking off blinders! Suddenly, I can see what's going on. Now, I can easily generate noisy sine waves, increasing freq, increasing amplitude, whatever. These are converted by MatLab to \h hex numbers and written to a file. ViewSim then picks these up (using assign < filename) and uses them for input vectors. ViewSim then writes the \h hex results (using, check > filename) to another file, MatLab reads these results, converts back to floating point, and plots. I wish ViewLogic would permit a hot link to MatLab like the big boys do, (Alta Group, DSP Canvas etc.) instead of having to interface through files, but for now, I'm having too much fun to complain much. There is no comparison to viewing miles of hex numbers in ViewTrace, with a simple plot of a clipped sign wave! Is anyone else doing this? I also plan to use MatLab to provide stimulus vectors to my Link Logic analizer/generator, and analyze results returned from the Link, which will be hooked to the breadboard hardware. I haven't even received the Link yet, so any experience you may have with DSP signals and Logic analyzers would be appreciated. In a more general vein. Why don't more vendors provide graphical interfaces for digital signals? Logic analyzers should be able to display a DSP sine wave as a sine wave on the screen. Digital simulators should be able to display the output of a FIR graphically, and have a means of generating, and graphically viewing. stimulus vectors. Or, perhaps they should just hot link to MatLab. You can't drag me away from this MatLab simulation now, Dave Decker ddecker@diabloresearch.comArticle: 4595
IMHO, Chronology: Well established, professional EDA company with 30+ employees, and significant patents on their timing diagram analysis tools, which I have heard they are now seeking to enforce. Synapticad: V. small startup who have copied Chronology's products and marketed the resulting efforts at cut-down prices. Take your pick. David PashleyArticle: 4596
I have a couple of questions about configuring a Xilinx XC4000-series
device via Asynchrous Peripheral Mode. I have a design in which
I configure an XC4013L in Asynch. Peripheral Mode over VME. The
download appears to work (in the sense that ERR* never goes low, and
DONE goes high at the appropriate time), but I am having a spot of
confusion regarding the actual startup. Details:
I am using NeoCAD (err...Xilinx) FPGA Foundry to create Motorola
Exormacs format (S-Record) data which is read by a VME single-board
computer which in turn writes the bitstream to the XC4013L device
(which is located on a separate card, reachable from the SBC via VME).
This data is 30995 bytes (247960 bits) long, which exactly matches
the "PROM size" required for this device ('96 data book table 22,
page 4-57). I write the data to the device using 30995 writes,
checking RDY/BUSY* and ERR/INIT* as necessary. After the 30995th
write, DONE goes high as expected, but the newly-configured device
does not actually complete startup (all I/O pins are still 3-stated,
I am using the "default" startup order, activate DONE first, then
release internal GTS, then release internal GSR). I need to write
one more byte of data to the device (a 30996th byte, it doesn't seem
to matter what the byte contents are) to get the I/O's to activate.
I wanted to understand why I needed this 30996th write (which didn't
really make sense to me), so I started digging. The only funny
thing I could find was that the "length count" field generated
by NeoCAD (umm...Xilinx) bitgen, and placed in the bitstream,
was NOT 247960 (as I had naively expected) but was actually 247958.
Does this make sense? What does Xilinx MakeBits put in as a length
count for a single 4013 device? Is this a known bitgen bug?
One more thing. This 247958 value DOES work for a different 4013L
(on the same board) which configures itself in Master Serial Mode,
reading out of an XC17256 SPROM.
Thanks in advance for any possible tips. Peter, do you have any
insight?
-Steve Gross gross@pa.msu.edu
Article: 4597>As I understand it, I must use their tools (Max+Plus and XACT) to place >and route, obtain timing etc). These tools seem to come with schematic >capture, vhdl simulators, synthesis engines etc (a complete design >environment?). Xilinx tools don't COME WITH anything! You pay for all of it, cafeteria style. The basic XACT system is just the "back-end" place and route stuff. You have to buy your fornt-end design entry tool seperate, at additional cost.Article: 4598
In article <848425842snz@fpga.demon.co.uk> david@fpga.demon.co.uk (David Pashley) writes: >From: david@fpga.demon.co.uk (David Pashley) >Subject: Re: The best timing diagram editor/simulator? >Date: Tue, 19 Nov 96 17:50:42 GMT >IMHO, >Chronology: >Well established, professional EDA company with 30+ employees, and >significant patents on their timing diagram analysis tools, which I >have heard they are now seeking to enforce. >Synapticad: >V. small startup who have copied Chronology's products and marketed >the resulting efforts at cut-down prices. >Take your pick. >David Pashley David, can you please list your sources of information, explain why each of these points matters, and describe any affiliations with the companies involved?? Thanks in advance, David Fura Levetate Design SystemsArticle: 4599
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