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Rene Bakker wrote: I am running Procapture from the Xilinx PROflow task launcher and as soon as I select add component the system crashes. Whatever proglet it is that would browse through libraries seems to be broken. You also get this effect from (accidentally) double-clicking on the background of a schematic, which I believe ought to go to the component browser. The same happens if you mis-type a component name after typing 'com', as the browser attempts to spin up and offer you a different component. So long as you never double click and always know exactly what library component you want, you'll get away with it. (sigh). Also, don't be tempted to ansswer 'yes' to the seemingly helpful 'log exists, do you want to recover', as it'll do _exactly_ the same, ending in the same blow-up. An inspired piece of code throughout. Save often ! SteveArticle: 4626
We have without success been looking for a style formatter for VHDL (and C). Similar to the C-beautifier cb in UNIX. This could help in maintaining a company wide coding style. Any ideas? Henning Larsen, Risoe National Laboratories, DK Mike Harrison wrote: > > Vincent Rowley wrote: > > > > Hi, > > > > We are looking for a VHDL code editor for Windows NT platform. > > > > All information is welcome. > > > > If you reply to the group, send also a copy to the address > > vrowley@hexavision.com . > > > > Thanks, > > > > Vincent Rowley > > > > -- > > ----------------------------------------------------------------------- > > -- Vincent Rowley -- HexaVision Technologies Inc. -- > > -- -- 2050 Rene-Levesque ouest -- > > -- Email: vrowley@hexavision.com -- Bureau 101 -- > > -- Tel: 418-686-5000 (233) -- Sainte-Foy, Quebec, Canada -- > > -- Fax: 418-686-5043 -- G1V 2K8 -- > > ----------------------------------------------------------------------- > > Hi Vincent, > > We use a product called Sledgehammer, which is an HDL addon to CodeWright. > I have been quite satisfied as the editor is very easily customized - I > feel that emulation with whatever the user is most familiar is an extremely > important attribute. We only code Verilog here, but it color codes keywords > from both HDL's as well as smart indenting, etc. and emulates Brief, VI, and > Epsilon, as well as "Notebook" type editors. The company is VHDL Tech. > Group @ 610-882-3130. They are probably on the web somewhere too! Hope > this helps. > > Regards, > Mike Harrison > OIS > Northville, MIArticle: 4627
Richard Staley <rjs@hep.ph.bham.ac.uk> writes: > Has anyone made their own download cable for programming devices from an IBM PC > parallel board? The schematic is somewhere in Lattice data books (In-system Programmability Manual, I suppose). It contains nothing but a HCMOS logic chip and a few resistors and caps. Hardly possible to get it wrong, but don't forget the 10nF cap which is recommended between ispEN/ and GND near the isp chip - you'll run into problems otherwise sooner or later (typically program verification fails). No, I didn't build the cable myself, I bought the starter kit. Would go for the Synario kit now. -- http://www.hut.fi/~iisakkil/ - Rebi siitArticle: 4628
Mike, Thanks for the Kudos on Sledgehammer! Glad you like the product. Sledgehammer information can be obtained on our web site. http://www.vhdl.com While you're there, register for a chance to win "Snappy", a really nice video frame grabber. We're raffeling off a copy to some lucky chap who fills out our online registration form. -- Sincerely, ------------------------------------------------------------- William Billowitch e-mail: wdb@vhdl.com The VHDL Technology Group Web: http://www.vhdl.com 100 Brodhead Road, Suite 140 Phone : 610-882-3130 Bethlehem, PA 18017 Fax : 610-882-3133Article: 4629
P Nibbs <pnibbs@icd.com.au> writes: |> |> Can anyone tell me what the difference is between a course-grain netlist |> and a fine-grain netlist. |> e.g. what is a fine/course grain? |> |> What effect does synthesis, optimization have on this, and how can this |> effect the design process? The "grain" basically refers to the primitive element of the final netlist and the target silicon. From fine to coarse, it might go like this: ^ transistors | 2 input NAND gates | gates and flip flops | fpga logic block with lookup tables and flip flips v fpga logic blocks with fast carry and other inter-block communication The netlist produced by the synthesis tool will reflect the grain of the target. The problem was (and still is to some extent) that synthesis was originally designed for fine grain architectures like gate arrays. So that the result was optimized for outputting gates. When fpga synthesis came along, the first primitive approach was to map the fine grain synthesis gate output onto the coarse grain fpga architecture. This wasted many of the features of the fpga, and was inefficient in terms of utilization and performance. Synthesis tools now better understand the coarse grain fpga target architecture. So they can synthesize from HDL to coarse grain netlist without going down to gates and back up. But the science of synthesis is lagging the constant introduction of new coarse grain architectures. -- Ken Goldman kgold@watson.ibm.com 914-945-1466Article: 4630
A simple, one word answer - 'Marketing' Any relationship between FPGA vendors' claimed gate count and your real experience is pure coincidence! The only sure-fire way to evaluate whether or not your application will fit into a particular device is to compile/fit the design.... -- Regards AndyG ************************************************** *Any opinions expressed herein are entirely mine,* *unless expressly stated otherwise. * *(as if anybody else would admit to them.....) * **************************************************Article: 4631
david@lowrance.com wrote: > > In article <3293BB30.15B5@emf.net>, > Brad Taylor <blt@emf.net> wrote: > > > > The short answer is greed. > > The longer answer is that there really is no good way to relate FPGA > > features to ASIC nand gates. When the answer is undefined, the > > marketing guys will always promote the most optimistic estimate. It > > probably got started like this. > > Marketing: How big is that new FPGA thing? > > Engineering: Well, it has 400 4LUTS:DFFs and registers in the IO blocks. > > Marketing: No, I mean how big is it? > > Engineering: Well we have two design which just fit. One is from a 6K > > ASIC and the other is from a 4K ASIC. > > Marketing: (Lets see 6+4 = 10) OK, gotta go. At FPGA96 last spring, someone proposed that we use new nomenclature for the vendor's claims on gate capacity. Analogous to the idea that dogs seem to get more lifetime out of a year that we do--hence, a "dog year" being equivalent to about seven person years--he suggested that vendors be required to specify the capacity of their parts in "dog gates." Anyway. There is certainly a big difference between what the nomenclature says and what you can fit into a part, most of the time. There are in fact very ordered, repetitive designs that will come close to the nominal capacity on some FPGAs, but they are not common sorts of circuits. The problem, as other posters have said, is that the marketing department counts logic resources and adds them up, at so many "gates" per LUT, etc. If an FPGA has relatively fine grain, so that you are using most of the resources in each logic block, and it has a surplus of interconnect, so that you can in fact use nearly every logic block without getting a 10 kHz design, then this is a fair estimate of chip capacity. But trends are going the other way. With sub-micron processes and three-layer metal, the interconnect takes up all the chip area, and the logic just kind of lies there underneath. So there is no penalty for a vendor to make the logic block more complex than the average design can use. After all, the silicon is just sitting there otherwise. This is a big help in implementing some types of circuits, in fact, because is can reduce the number of blocks you need and localize some operations to a single block. But it makes the "count-'em-up" approach to capacity even less accurate. Now, you are very unlikely to use most of the stuff that is in the logic blocks. So the difference between dog gates and your gates gets even bigger, even though the FPGA may be better for your application than the previous generation would have been. There have been attempts to solve this. Actel used to rate their parts based on the number of gate-array gates necessary to implement a circuit that just fit in the FPGA. They have unfortunately abandoned this nobel idea. PREP, Stan Baker's organization, had an industry-wide benchmarking effort going for a while. It produced very useful data that did in fact give you an accurate picture of how a part would behave on a particular type of design. But, predictably, as soon as the results trod on marketing toes, companies began to withdraw from the group. Marketing departments came up with scalar "figures of merit" based on the whole suite of PREP benchmarks, with math that made the Minkovsky Metric look like arithmetic. And, to be fair, as FPGA capacities increased, the original benchmark circuits, used step-and-repeat fashion to fill the chips, became less useful. Baker is, I believe, working on a new benchmark methodology based on synthesis of real-world, large designs. If he is getting as much cooperation from the industry as he did last time, he can use all the independent support he can get. You might look him up. He posts here every once in a while, or is reachable at sbaker@best.com. ron wilson, ee timesArticle: 4632
I've tried to get the PROSeries to work under Win95 for a client, and could not do it reliably. I've since found out that Viewlogic does not support Win95 with this product, and that you must "upgrade" to the Workview Office series. The Workview Office series does run under Win95 and NT, but IMHO suffers from a severe case of "project controlitis", which is to say that it wants things to be located in its own place and time, not yours. Other problems are also obvious when you compare this product to offerings from OrCAD and Aldec. -- =============================================================== Louis P. Piche, PEng. Piche And Associates - Consulting Engineering Services (PAACES) Aero/Space Systems, Analog/Digital Electronics, Software Gordon McGregor <g.mcgregor@eee.strath.ac.uk> wrote in article <01bbd709$4ca9e220$35489f82@drl1.eee.strath.ac.uk>... > Hi, > does anyone happen to know if PRO series is compatable with > windows 95 ? I am running Procapture from the Xilinx PROflow > task launcher and as soon as I select add component the system > crashes. > > If you have managed to get PRO series working with win95 could > you get in touch, please ? > > -- > Gordon McGregor > --------------------------------------------------------------------- > Communications Division Email: g.mcgregor@eee.strath.ac.uk > Electronic & Electrical Eng. Dept. http://drl4.eee.strath.ac.uk/~gmcg > University of Strathclyde Tel: +44 (0)141 548 2250 > Glasgow G1 1XW Fax: +44 (0)141 552 4968 > >Article: 4633
In article <571akv$4lh@usenet.bham.ac.uk>
rjs@hep.ph.bham.ac.uk "Richard Staley" writes:
> Has anyone made their own download cable for programming devices from an IBM PC
> parallel board?
> If so , (and it was successful) could you describe the circuit?
I think the circuit is included in the documentation on the Lattice
CD-ROM, which you can get free from Lattice distributors. It also comes
with some nice software.
Leon
--
Leon Heller, G1HSM | "Do not adjust your mind, there is
E-mail leon@lfheller.demon.co.uk | a fault in reality": on a wall
Phone: +44 (0)118 9471424 | many years ago in Oxford.
Article: 4634
In short, if your design is register-intensive, you will get "good"
utilisation in an FPGA, perhaps 50% of what you might expect. If it
has a lot of combinational logic, you will do a lot worse.
I recently did a design which was a bit of each, which 70% filled a
3064 ("6400 gates") and finally fit into an ASIC in 2200 gates.
You can easily do a real gate count of an FPGA design by counting the
elements in the final flattened optimised netlist. With the .XTF file
from Xilinx this is particularly easy.
>> A while back one of my co-workers brought me an article he'd clipped
>> out of a magazine. Actel had a new part that would hold 20K gates
>> with 100% utilization... or so they claimed. At the time we were just
>> getting started on a small ASIC, about 14K gates. "Great", I said.
>> "We'll be able to create a prototype and use that one FPGA to test our
>> entire design." It was not to be. The problem was that the 20K gate
>> part would barely hold 10K 'real' gates.
Peter.
Return address is invalid to help stop junk mail.
E-mail replies to z80@digiserve.com.
Article: 4635david@lowrance.com wrote: > > A while back one of my co-workers brought me an article he'd clipped > out of a magazine. Actel had a new part that would hold 20K gates > with 100% utilization... or so they claimed. I have had mixed results with FPGA's. But recently we did a design that overran the utilization by 20%, we could keep removing bits and pieces of test logic until we got the design to fit and route with just one or two spare 'blocks', actel 14100. It was my impression that 'gate' comparsion is made more difficult by the granularity of the FPGA.Article: 4636
Has any body successfully manage to configure a number of FLEX 8000 devices in the MD-ASB (multi device active serial bit slice) configuration. I have been trying to do this recently, but without success. I can get the active device to provide a clock signal, which clocks a counter in a epm7064. But the flex devices will not open circuit the conifg_done signal to indicate a successful configuration. any ideas? cheers -- DerrickArticle: 4637
I agree with Peter's ( the other Peter's ) response. An analog PLL is a good approach. But I would implement everything except the integrating op-amp and the VCO inside the FPGA, since you have it already and the logic is therefore "free". See page 8-161 of the 1994 Xilinx data book for the schematics of a phase/frequency comparator.( Make sure you have the "1994, third edition", which gives you two different implementations on page 8-162. Peter Alfke, Xilinx ApplicationsArticle: 4638
Can anyone be specific about the advantages and / or disadvantages between using Moore or Mealy state machines in sequential circuit design. Text books seem to indicate that it is a matter of personal preference and convenience but I'd be interested to know if there are any speed, area or other trade offs. Thanks in advance Dave RennieArticle: 4639
Michael Ismert (izzy@salsa.salsa.lcs.mit.edu) wrote: : On a related note: has anyone given any thought to (or does there : exist) a site where people could put up FPGA designs more or less as : freeware? We have a slightly crufty PCI bus master/slave design that : we wouldn't mind making available for people who wanted to poke around : without spending the big bucks on Xilinx's prepackaged modules. I : suppose this sort of thing would be primarily targetted at university : research, where people weren't so concerned about giving away their : advantage over their competition, and also weren't making devices in : very large quantities. Perhaps such designs could be copy-lefted : under the GPL or some such thing to keep them freely available. I would be willing to host designs on my ftp site at no charge to all. --Alan ArnaudArticle: 4640
Has anyone managed to utilize Xilinx 4000e IOB FFs through Synopsys? I'm using FPGA Compiler v.3.4b and Xact 5.2.1. It seems like no matter what I try, all my I/O registers are mapped into the CLBs. I'm describing the I/O registers in the VHDL description in a normal D-flip-flop style. The flip-flops are controlled by the global reset for which I use the GSR net. I tell Synopsys: set_register_type -exact -flip_flop OFD_F find (design, stm4_out_reg) Performing set_register_type on design 'stm4_out_reg'. 1 but the flip_flops synthesize into 'FDC's. Thanks for any information that could help! MarkArticle: 4641
On Mon, 25 Nov 1996 14:24:31 +0200, Mark Sandstrom <Mark.Sandstrom@martis.fi> wrote: >Has anyone managed to utilize Xilinx 4000e IOB FFs through Synopsys? I have utilized Xilinx IOB FFs, but not through Synopsys per se. During optimization in the Xilinx tools, FFs are moved to IOBs independent of the Synopsys implementation. Although, on one design I noticed some I/Os didn't have the FFs moved into the IOBs. As of yet I haven't found out why. If you really want Synopsys to do this mapping, then I guess I can't help. -- Paul Dietrich MN65-2500 | Phone: (612) 951-7851 Honeywell Technology Center | FAX: (612) 951-7438 3660 Technology Dr., Mpls., MN 55418 | Inet: dietrich@htc.honeywell.comArticle: 4642
sjadam@trog.dra.hmg.gb wrote: > > Can anyone be specific about the advantages and / or disadvantages > between using Moore or Mealy state machines in sequential circuit > design. Text books seem to indicate that it is a matter of > personal preference and convenience but I'd be interested to know > if there are any speed, area or other trade offs. > > Thanks in advance > > Dave Rennie Here's a couple quick remarks: - Mealy machines have lower system latency since the outputs can be a function of the inputs. For a Moore machine, you get at least one clock longer latency due to needing to latch the input (or latching a term dependant on the input). If you really have to squeeze out every clock cycle, Mealy is better. - Moore machines can potentially run faster in a system since the output delay is simply the clock-to-Q of the state flip-flops; Mealy machines add in the additional combinational logic delays for any outputs which are functions of both the state and inputs. - For FPGA design, you should probably use one-hot FSMs for best speed -- the additional delays doing a state decode can really hurt performance (especially in dense designs with complex FSMs). Hope this helps, Bob Sugar Senior Engineer Advanced Technology Group Exabyte CorporationArticle: 4643
PREP was a good idea that went sour due to super-aggressive marketing. To accomodate all programmable devices, even the lowliest CPLD, the test circuits were made very small. ( e.g. loadable 16-bit counters ) and were then replicated until the device was full. Each circuit had as many inputs as outputs, so they could be concatenated like Lego blocks. Obviously, each company wanted to be the best,so we all put in a lot of effort to pack our devices and to achieve an impressive speed. Density was not much of an issue, since the routing was trivial, only neighbors talking to neighbors. ( How's that for meaningful benchmarks ?) Then came the dirty tricks. Altera managed to defeat the spirit of the exercise by exploiting an oversight in two of the circuits,where common logic could be pulled out and be implemented only once per device. This gave them great packing density, a victory of synthesis over benchmarking. In order to level the playing field, everybody else then had to do the same stupid thing. "To hell with meanigful data, as long as everybody can brag about some unrealistic achievement". This left such a bad taste in my mouth that I resigned from the committee. Peter Alfke,speaking for himself.Article: 4644
Do you guys ever wonder how this type of crap ever leaks out of the kindergarden play yard and into this news group ??? Philip. In article <56otch$h6o@newton.pacific.net.sg> Steven Esau <stevene@asymetrix.com> writes: >Hi, I'm Steven Esau <stevene@asymetrix.com> the general counsel of >Asymetrix Corporation. Mark J. Christie <mapsing@pacific.net.sg> is theArticle: 4645
>sjadam@trog.dra.hmg.gb wrote: >> >> Can anyone be specific about the advantages and / or disadvantages >> between using Moore or Mealy state machines in sequential circuit >> design. Text books seem to indicate that it is a matter of >> personal preference and convenience but I'd be interested to know >> if there are any speed, area or other trade offs. >> >> Thanks in advance >> >> Dave Rennie Mealy and Moore type state diagrams are alternate logic description methods. It is quite possible to make either type of description for a particular collection of gates and flops. Once a state machine has been reduced to equations or a schematic, the source format is irrelevant to the function of the machine. Apparent differences between machine "types" can result when an input register is considered to be part of the state register instead. [1] State machine theory is based on input synchronization. If an input to a non-trivial machine is not synchronized, unexpected results will likely occur at the worst possible moment. While input and output registers are most often required for synchronization, their states are not normally included on a Mealy type diagram. A Mealy description is thus more concise and I find it easier to understand. But don't forget to add the synchronization registers to the basic machine synthesis. A Moore description generally shows some states resulting from input or output synchronization registers. This description method enforces some synchronization, but state races are still possible if input synchronization is otherwise ignored. [2] [1] Treseler, Michael "Designing State Machine Controllers Using Programmable Logic" Prentice Hall, 1992, p89. [2] Ibid, p82-83. >Bob Sugar <bobsug@exabyte.com> writes: > - Mealy machines have lower system latency since the outputs can be > a function of the inputs. For a Moore machine, you get at least > one clock longer latency due to needing to latch the input (or > latching a term dependant on the input). If you really have to > squeeze out every clock cycle, Mealy is better. If you add the required input registers, latency is equivalent. > - Moore machines can potentially run faster in a system since the > output delay is simply the clock-to-Q of the state flip-flops; > Mealy machines add in the additional combinational logic delays > for any outputs which are functions of both the state and inputs. True for either machine but only if inputs are pre-synchronized and the output bit happens to match a state register bit. > - For FPGA design, you should probably use one-hot FSMs for best > speed -- the additional delays doing a state decode can really > hurt performance (especially in dense designs with complex FSMs). True for register-rich devices. >Hope this helps, >Bob Sugar >Senior Engineer >Advanced Technology Group >Exabyte Corporation Mike Treseler Staff Engineer Fluke Networks DivisionArticle: 4646
>Has anyone managed to utilize Xilinx 4000e IOB FFs through Synopsys? >I'm using FPGA Compiler v.3.4b and Xact 5.2.1. It seems like no matter >what I try, all my I/O registers are mapped into the CLBs. I'm >describing the I/O registers in the VHDL description in a normal >D-flip-flop style. The flip-flops are controlled by the global reset for >which I use the GSR net. Sorry I haven't used the 4000e, but does it allow resets in the OUTFFs? I know that the 4000 doesn't, so putting a reset on a flip-flop disqualifies it from going in an IOB. -- +===============================================================+ + Joe Samson (313) 994-1200 x2878 + + Research Engineer, ERIM + + P.O. Box 134001 email samson@erim.org + + Ann Arbor, MI 48113-4001 + +===============================================================+Article: 4647
Hi all, I'm using Xilinx's XACT to design FPGA . I haven't any experience with Xilinx's FPGA and have some problems . Hope you help me . 1. When use VHDL When use VHDL to design a FPGA , how to assign the pin number ? I heard of it is disable to assign the pin nubmer without using schematic .Is it right ? 2. When simulate How to set the input signals's level ? By Altera's MAX-Plus II , it is very easy . Thanks PaleyArticle: 4648
> I'm using Xilinx's XACT to design FPGA . I haven't any experience with Xilinx's > FPGA and have some problems . Hope you help me . > > 1. When use VHDL > When use VHDL to design a FPGA , how to assign the pin number ? I heard of > it is disable to assign the pin nubmer without using schematic .Is it right ? I'm afraid so. I never found a way, and Tech support just recommended a schematic veneer around the VHDL. You may end up using schematics anyway, as this is the only way I could ever get floorplanning to work sensibly. (without splitting your VHDL into separate modules in a schematic, all your logic has names consisting almost entirely of series of 1,l,S and $. (that's the number one, the letter 'L', the letter 's' and a dollar sign. This would be fine if the user had to spend less time grovelling around in the netlists, but as it is, caused extreme stress (to me anyway). The main problem with schematic veneers is that it's mind-numbing to do, and mistakes sometimes creep in, swapping pins. Despite the fact that the veneer is essentially content free, be prepared to suspect it when "simulation works, but the silicon doesn't" situations arise. The other 'benefit' of a schematic veneer is that it gives you somewere handy to put the PART= attribute, so Xmake works cleanly. Debugging may be easier if all the signals on your top-level VHDL are defined as inout pins, not signals. (I _know_ this is damned inelegant VHDL, but this it the real (flawed) world here, with customers who simply don't care that the toolset's crashed 8 times that morning, etc, etc, rant) This gives you a huge symbol (and viewgen may need a few attempts at this before it doesn't crash...), but allows you to bring extra lines out to pins without recompiling the VHDL. (Most times, you can find the nodes in editlca and bring them out yourself, so no PPR time, either!). > > 2. When simulate > How to set the input signals's level ? 'l' or 'h' signame if I remember, but don't hold me to it. I was never terribly impressed with the simulator, but it did work and seem to be trustable. I seem to remember that ProWave was _the_ tool that wouldn't work under NT, but I may be forgetting. I do remember that Workview Office's VHDL simulation was good, though. Same simulator interface for source as post-synthesis, a blessing! Another thought that surfaces here, it _may_ be that you need to use the internal names (gathered from a rummage round in editlca) for simulation, unless the signals are present on the top level schematic. Yes, that rings bells. That's another reason for a huge symbol with all its pins coming out to labelled stubs of wire. Another soul destroying job for you, there. (but, again, worth the effort) >By Altera's MAX-Plus II , it is very easy . I have since discovered this. (although the Max-PlusII simulator isn't something I'm deeply impressed by yet. The Max-Plus II VHDL tools _do_ however export VHDL with post-synthesis timing, so, again, the same simulation vectors can be used on source and object. Steve. (As per usual, I have no affiliation with anyone, I'm just a user of this stuff)Article: 4649
I use CodeWrite 32 from Premia (www.premia.com). Extensions (DLLs) are available over the net for adapting this editor for Verilog and VHDL. Kevin Steele Vincent Rowley wrote: > > Hi, > > We are looking for a VHDL code editor for Windows NT platform. > > All information is welcome.
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