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In article <3rlhvl$1ge@marina.cinenet.net> kirani@cinenet.net (kayvon irani) writes: > I am wondering if any one out there has tried out the Cypress's > FLASH series ? They're supposed to perform same as or better than > Altera parts but supposedly, they are much easier to re-route once > the pins are fixed. BTW, any comment on AMD suit against them ? Altera has a broad selection of parts so it's hard to tell what you mean by Altera parts. Their 7000 family has a deep secret which is never discussed in the data book: the interconnect matrix is quite sparse, the price they pay for their speed. That is probably the source of the re-routing concern you mention. Their so-called Flash Logic parts (so-called because only one member of the family is actually built with Flash technology and it's not really available right now) is what they euphemistically call "feature-rich". This translates as EXPENSIVE. Even if money and availability is not a concern, the fact is that a universal interconnect matrix is not the final answer to re-routing problems. When you have product-term sharing between adjacent macrocells like in the Altera Flash Logic and the Cypress 370 series, a change in product term usage COULD result in a locally starved product term shortage preventing fitting. (note: I think the 370 macrocells can only borrow from neighboring macrocells, I haven't convinced myself for sure of this from their literature yet) The best solution is that offered by Lattice and AMD: input/output switch matrixes. IOSMs allow you to avoid the problem of neighboring macrocells competing for product terms. There is a speed penalty but for many applications the speed is adequate and the flexibility is wonderful. (I think Lattice could use more internal routing, based on the studies I have done, but the Mach 445 will swallow almost anything reasonable.) -- Should the 1st amendment apply to the Internet? Ask Senator Feinstein.Article: 1401
I am going through some LATTICE eqns., and trying to understand the logic, without having the Lattice manual. Could somebody using Lattice explain to me the foll. queries : I only have the information about the foll. macrofunctions from the Lattice System Macro Library. The macrofunctions are 2/4/8 bit down counters CBD42, CBD44, CBD44_1, CBD44_2, CBD48, CBD48_1, CBD48_2, CBD48_3, CBD48_4. I could not understand the 'underscore' deviations of the respective counters. Moreover for CBD48_4(CAO,[Q0..Q7],CAI,EN), there is no clock. How can this be a down-counter ? The eqns. that I have use two successive lines as below : CBD48_2(pc4,pc5,[pc0..pc3],pd4,pd5,1,clk27,0,pcao,1,0); CBD48_3(pc6,pc7,[pc0..pc5],pd6,pd7,1,clk27,0,pcao,1,0); How can the output signals [pc0..pc3] be driven twice ? Thanks & Regards,Article: 1402
Has anyone built the Unified Library macros for Xilinx 5.0 or greater using FutureNet, and you be willing to share them? Or, would anyone want to be part of a team to construct these macros? Regards, Bob Bachus 904-373-6785 (voice) comtech@freenet.ufl.eduArticle: 1403
Hi all,
this will be a longer article about some experiences I got from
programing Altera FLEX logic using Max-II software and in the second
part some problems I can't solve at all.
What I have is a RIPP 10 board from Altera with a FLEX 8452
controlling the ISA bus interface and two FLEX 81188. Additionaly
there are 512Kx8 RAM (accessiable from the 81188's).
For programing I have the Max-II 5.2.
I should eventually mention, that I'm not a FPGA guru. Instead I'm
coming from computer science making my way educating myself... Since a
couple of weeks I try to create a small module without much luck.
* - I -
** When I compiled and simulated the first designs I created, I
figured that the "global logic synthesis style"s I can choose don't
behave as their names suggest. There is "normal", "fast" and
"wysiwyg". But it turned out, that fast seems to be only a little bit
faster than wysiwyg and normal seems to make the best speed. But both,
fast and normal do some things I can't understand. Therfore the result
has lots of glitches. Especially when I use state machines.
Is there any explanation for this?
** With the former version of the software (Max-II 5.1) I tried to
figure why some designs didn't work. Finaly I installed the update and
those designs happend to work. At least something about state machines
is affected, they don't enter unused states whithout any visible
reason anymore. Are there other problems known like this? Are there
experiences which constructs to use and which one should avoid?
** There seems to be no real correlation between the complexity of a
equation and the time nessesary to compute it. Are the any rules what
I can expect?
Well, obviewsly the fact whether the result is supposed to drive a pin
or is only used by the next equation is important. But also these
timings vary about as much their average value is. Normal?
** I would guess, that the following two AHDL excerpts (A, B) should
compile into the same code. But the simulation I get from is sometimes
quite different (in terms of the timing, not the logic).
A:
IF ena THEN
bus[N..0] = reg[N..0];
ELSE
bus[N..0] = GND;
ENd IF;
B:
bus[N..0] = reg[N..0] AND ena;
Does someone has an idea what will happen? (Unfortunatly I'm not
really able to reproduce those results, this seems to happen by
chance.)
** Is there any rule how to write state machines? Should I better use
Moore or Mealy automata? While the notation of those machines is
really convinient I never know what they'll do. See below.
* - II -
The designs I'm fighting at the moment had a state machine like this:
sm : MACHINE WITH STATES (res, wal, wah, wvl, rvl);
and later a logic table like this:
TABLE
sm, /iow, /ior => sm, (dd, dga, dgd, glbl_drv);
res, VCC, VCC => res, B"0000"; -- What should we do? Wait.
res, VCC, GND => wal, B"0000";
res, GND, VCC => wal, B"0000";
wal, VCC, GND => rvl, B"0101";
wal, GND, VCC => wvl, B"0101";
rvl, VCC, GND => rvl, B"1001"; -- Wait until host is away
wvl, GND, VCC => wvl, B"0011"; -- dto.
END TABLE;
The glbl_drv signal is immediatly connected to a pin, while the other
signals driven from this table (dd, dga, dgd) are used in other
equations.
This was almost fine except that I realized, that the time of one
clock cycle the dgd signal is active is too short. Therefore I changed
the above declaration like this:
sm : MACHINE WITH STATES (res, wal0. wal, wah, wvl, rvl);
and:
TABLE
sm, /iow, /ior => sm, (dd, dga, dgd, glbl_drv);
res, VCC, VCC => res, B"0000"; -- What should we do? Wait.
res, VCC, GND => wal0, B"0000";
res, GND, VCC => wal0, B"0000";
wal0, x, x => wal, B"0101";
wal, VCC, GND => rvl, B"0101";
wal, GND, VCC => wvl, B"0101";
rvl, VCC, GND => rvl, B"1001"; -- Wait until host is away
wvl, GND, VCC => wvl, B"0011"; -- dto.
END TABLE;
I expected the glbl_drv signal to be active from about 8-12ns or so
after sm enters the wal0 state until reset. (As it became active about
the same time after entering the wal state in the former design.)
Unfortunatly it takes about 25ns until active now. Also there is a
"glitch" of about 8.5ns one clock cycle after it became active for the
first time. Moreover the signals derived from dga and dgd are no
longer stable.
Is there any half the way general rule I am missing? As long as each
and every small change to the design requires a almost complete
rewrite I guess there must be something wrong with the way I go.
Any help appreciated!!!
Thanks for listening
/Jerry
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Article: 1404Joerg Wittenberger <joerg.wittenberger@inf.tu-dresden.de> writes :- >** I would guess, that the following two AHDL excerpts (A, B) should >compile into the same code. But the simulation I get from is sometimes >quite different (in terms of the timing, not the logic). > > A: > > IF ena THEN > bus[N..0] = reg[N..0]; > ELSE > bus[N..0] = GND; > ENd IF; > > B: > > bus[N..0] = reg[N..0] AND ena; Yes it will compile into the same code. The timing however is dependant on the routing resources used, although in the FLEX I would only expect small (+/- 1ns) deviations with the above. Are you using global clocking ? Product term clocking of the above registers may account for changes in timing. Stuff about state machines deleted. Observation 1) Are you using a clocked state machine, i.e. sm : MACHINE WITH STATES (res, wal, wah, wvl, rvl); sm.clk = clockinput; An unclocked state machine may explain your glitches. Observation 2) You may wish to make your glbl_drv output synchronous. This will stop any state machine decode glitches going to the 'outside world'. Observation 3) Again, have you told the compiler to use Global Clock, rather than product term clocking. Cheers, T.H.Article: 1405
Has anyone used the Orbit Semiconductor FPGA netlist conversion service? They call their process "Encore". ChrisArticle: 1406
80x51 in FPGA ? - results I have lots of email saying 'let me know if you find something' and some asking about the 6502 quoted, but alas, no 51 core yet.. :-) ( might be just too tough still .. ) The design ex of 6502 was from xilinx, pge 11-18 of their 'breakthru 95' road show manual. uses x8108 new device ( too big / complex for older parts :-)? vhdl source fits 96% OF 8106 FILLS 81% OF a1 15k gate cpld ( compeditor ?) fills 197% of 10k a1 fpga ( compeditor ?) 4000 lsi logic gates no speed spec mentioned... If anyone hits a 80x51, let me know... jimArticle: 1407
Plesae ignore. TestArticle: 1408
rose@src.honeywell.com (Fred Rose) writes:
> One data point which may help shed some light on the mind set of the two
> HDL conference organizers, and why they may not see eye to eye. The
> contest in question at the Verilog conference was the design of a counter.
> The design contest at a recent VHDL conference was the Denver Airport
> baggage handling system.
Kirk Anderson <kirka@ctron.com> wrote:
>AMEN !
Kirk, again I'd like to clarify, this design contest wasn't held at *any*
Verilog conference -- it was held at the Synopsys Users Group Meeting (which
is more of a synthesis oriented conference.) As I told Fred, if you wish to
catagorize the Synopsys meeting from historical company tastes, this meeting
would perhaps be seen as more VHDL than Verilog biased from a Synopsys, Inc.
point of view because they only sell a VHDL simulator. How the customers
see it is another story.
Also, I'd like to stress that this design contest was not crafted to be a
referendum on whether VHDL or Verilog is a better language for serious
hardware designers to use. The fact that 89% of the Verilog designers
completed while 100% of the VHDL design *didn't* complete it was a surprize
to an awful lot of us!
I know that this may seem like I'm nitpicking; but I just want to try to keep
the facts in this contest straight in the public's mind when this contest is
being discussed.
- John Cooley
Part Time EDA Consumer Advocate
Full Time ASIC, FPGA & EDA Design Consultant
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 3443 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 1409Hello Does anyone know the email address or phone number for the uk distributer of the MACH110 series? Does anyone know anyone cheap (free) development software? Thanks DominicArticle: 1410
In article <3rp1k7$t4a@lantana.singnet.com.sg>
eddie@merlion.singnet.com.sg "q" writes:
> I am going through some LATTICE eqns., and trying to understand the
> logic, without having the Lattice manual. Could somebody using Lattice
> explain to me the foll. queries :
>
> I only have the information about the foll. macrofunctions from the
> Lattice System Macro Library. The macrofunctions are 2/4/8 bit down
> counters CBD42, CBD44, CBD44_1, CBD44_2, CBD48, CBD48_1, CBD48_2,
> CBD48_3, CBD48_4.
>
> I could not understand the 'underscore' deviations of the respective
> counters. Moreover for CBD48_4(CAO,[Q0..Q7],CAI,EN), there is no clock.
> How can this be a down-counter ?
The underscore macrofunctions are called sub-macros and are what would
appear in each General Logic Block (GLB) if you placed them manually.
If you place the parent named macro into one GLB then you need not worry
about the underscore ones as they are placed automatically (certainly in
the pDS software). The submacros contain the actual equations for
a particular GLB.
The CBD48_4(..) only generates the combinatorial CAO carry out and hence
needs no clock.
>
> The eqns. that I have use two successive lines as below :
>
> CBD48_2(pc4,pc5,[pc0..pc3],pd4,pd5,1,clk27,0,pcao,1,0);
> CBD48_3(pc6,pc7,[pc0..pc5],pd6,pd7,1,clk27,0,pcao,1,0);
>
> How can the output signals [pc0..pc3] be driven twice ?
>
The grouping [pc0..pc5] does not imply that all are outputs of that GLB.
Each 1000 series Lattice GLB only has four normal outputs and so
couldn't possibly generate six registered outputs. The first four
[pc0..pc3] are generated in the CBD48_1 sub-macro. In this case the group
[pc0..pcn] comprises inputs to the GLB.
>
> Thanks & Regards,
>
Anytime.
--
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Article: 1411
In article <3s1ep3$4qb@mailer.york.ac.uk>
dp11@unix.york.ac.uk "D Plunkett" writes:
> Does anyone know the email address or phone number for the uk distributer of
> the MACH110 series?
>
> Does anyone know anyone cheap (free) development software?
Kudos Thame Ltd. has an advert. in the current Electronics Weekly for
the MACH devices. Their number is (01734) 351010. They have a BBS on
(01734) 352942.
Leon
--
Leon Heller, G1HSM | "Do not adjust your mind, there is
E-mail leon@lfheller.demon.co.uk | a fault in reality": on a wall
Phone: +44 (0)1734 266679 | many years ago in Oxford.
Article: 1412Hi every one! Any one out there has regular subscription to PREP newsletter? If so, for the benefit of all of us could some one let us know which FPGA and CPLD fared the best in terms of capacity and speed? I remember last time, Altera CPLDs came slighty ahead of Cypress's CPLDs and on FPGA catagory Quick-logic fared the best ahead of Actel and others. BTW, do you guys think that PREP has become too political? Some FPGA vendors think so. From: Kayvon Irani Lear Astronics Corp. 3400 Airport Ave. Santa Monica, Ca 90405 (310)915-6000 Ext. 3696 (310)915-8369 FaxArticle: 1413
Can someone tell me if Altera has a technical support email adress ? Thanx in advance !!!Article: 1414
There is one service in Leuven (Belgium(Europe)) called EASICS that does these conversions. If you are interested I can give you their address. Peter SelsArticle: 1415
In article <3s3olf$62r@rc1.vub.ac.be>, tw38966@vub.ac.be (SH.RYU KIM HOFMANS) says: > > >Can someone tell me if Altera has a technical support email adress ? > >Thanx in advance !!! > try at http://www.altera.com/ you 'll find it if it exists... Peter SelsArticle: 1416
Hi, I am using Viewlogic to synthesize very simple circuits using VHDL. I managed to analyze the vhld programs( by using VHDL vhdl.vhd) and do the simulation (by using viewsim). Howerer when I used the technology mapping command it give me core dump with different reasons. Case I: ====================================================== $ vhdldes VHDLDes - V2.2; Workview 4.1.3 062292, 6000 Series c Copyright 1985,1992 by Viewlogic Systems, Inc. 1: VHDLDes> tech x4000 -- reading library file /proj/iso/Powerview/standard/x4000.sml Processing Viewlogic X4000 Library, Version - 2/22/93 Bus error(coredump) $ ====================================================== Case II: ====================================================== $ vhdldes VHDLDes - V2.2; Workview 4.1.3 062292, 6000 Series c Copyright 1985,1992 by Viewlogic Systems, Inc. 1: VHDLDes> tech lsi10k -- reading library file /proj/iso/Powerview/standard/lsi10k.sml Processing Viewlogic LSI10K Library, Version - 3/3/93 Memory fault(coredump) $ ====================================================== lsi10k.sml and x4000.sml files are in /proj/iso/Powerview/standard/. Any help or suggections will be appreciated? -JohnArticle: 1417
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Article: 1418In article <D9zCMG.ILx@undergrad.math.uwaterloo.ca>, pdgray@undergrad.math.uwaterloo.ca (Peter D. Gray) wrote: >In article <1995Jun9.034024.4769@super.org>, >Steve Casselman <sc@vcc.com> wrote: >>We are designing a low cost ISA board for reconfigurable >>computing/prototype development and would like to have >>everyones thoughts on the subject like: >> >>Cost, functionality, programmablity, prototype area, >>mezzanine busses, external connectors, development software, >>driver software and type of projects you might want to do >>with such a card. >> >>This will help us design a product more in tune with what >>you all might need. Hmmm... Since the definition of the board is somewhat nebulous, I can't say defintively what features it should have. However, I can volunteer some of mmy own experience in designing such boards and the applications that run on them. First, I feel it would be really nice to have a very low-cost board out there. Just enough for people to whet there appetite on the technology. Something similar to TI's $99.00 TMS320C5x development kit. After all, the more individuals we can entice into using reconfigurable hardware - the better. I also realize this may not be easy, FPGAs are NOT cheap. Second, the ISA bus isn't a bad choice if your target market is low-end developers on PCs. In fact, it is an excellent choice for the hobbiest market. A market I feel has been much ignored. Obviously it will limit the boards capabilites, but for an introductory platform, that's probablt not a problem. I would reccommend against the PCI bus if this is an introductory low-cost board. The PCI bus can add a lot of complexity that would be unecessary at this level. My guess is that someone's first venture into reconfigurable hardware is not going to be video-rate computing. Third, functionality should be constrained enough that the novice won't be overwhelmed. We all know that just learning FPGA design is hard enough. Give them a basic platform that will allow them to learn and experiment cheaply and efficiently. Fourth, if by programmability you mean how many reconfigurable resources there should be, I'd say one. Simply put one FPGA on the board with some memory and I/O. This way the user can develop simple uP and controllers that use the ISA interface or an exteral interface without contending with multiple FPGAs on the board (bus contention, fires, smoke, etc.) A proptotype area would be very useful. In fact, I would like to see a great deal of space available for such things. For example, one could place a CODEC on the board with some basic analog circuitry and have a simple audio development platform. Or, the more courageous user could place a DSP or other coprocesor on the board. Of course, some I/O from the FPGA should be dedicated for this purpose. In terms of external connectors, it would be nice if I could hook a logic analyzer up easily to any busses I have on the board. In addition, expansion connectors for memory or whatever would be very nice. If you provice a good prototype area, the user can add his own connectors as well. Develpment software is very important. We all know that one of the biggest problems facing the Reconfigurable Hardware area is a lack of tools. At least provide routines the user can use to read/write the board. Reconfigure the FPGA, end perhaps even a sample application could be provided. As far as projects go. Individuals with backgrounds in other areas will no doubt want to compare reconfigurable solutions to the solutions they have used in the past. For example, a DSP engineer would like to be able to develop filters in the FPGA and compare them to DSPs. Audio projects, control, data acquisition and stored program uProcessors are all nice introductory projects that could be handled by such a board. My goal for such a board would be to help expose more people to reconfigurable hardware. Unfortunately, for this to work well, the board will have to be cheap, easy to use, simple, and come with some good documentation and support. This will be very difficult to do and maintainn profitability. Regards, Jeff HutchingsArticle: 1419
In case you have access to CompuServe and would like to use AMD's MACHs: Go MAGNA, section "Design & Elektronik". There you find MACHXL 2.0 including docu and download softare for Windows for FREEEEEE! Uwe Kremmin AMD Munich uwe.kremmin@amd.comArticle: 1420
Hello,
I want to simulate the whole circuite I has designed using Orcad or
Viewlogic. I have common chips with Xilinx devices. I would like to
do a "timing" simulation, but I'm not sure if this is possible.
Could anybody help me?
Thanks in advance.
Q.
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Article: 1421
Hi:
I want to find this paper:
"Circuit Clustering for Delay Minimization Under Area and Pin Constraints"
H. Yang and D.F. Wong
EDTC '95(European Design & Test Conference)
I can't find this proceeding in local library. Anyone or the author could
send me the ps file or text file or anything helpful?
Thanks!
--
===============================
Hsien-Ho Chuang
eea80593@yankees.ee.nctu.edu.tw
===============================
Article: 1422|> >In article <1995Jun9.034024.4769@super.org>, |> >Steve Casselman <sc@vcc.com> wrote: |> >>We are designing a low cost ISA board for reconfigurable |> >>computing/prototype development and would like to have |> >>everyones thoughts on the subject like: |> >> |> |> First, I feel it would be really nice to have a very low-cost board out there. |> Just enough for people to whet there appetite on the technology. Something |> similar to TI's $99.00 TMS320C5x development kit. After all, the more |> individuals we can entice into using reconfigurable hardware - the better. I |> also realize this may not be easy, FPGAs are NOT cheap. It seems to me that there are plenty of boards out there already with one or only a couple FPGAs. As has been said earlier in this newsgroup, what we really need is low cost tools. There has been some discussion on the one-FPGA board made by XESS corporation - for a low fee (I don't remember, but it is under $150), you get a board with an FPGA *and* free access to some tools. The tools may not provide you with all the fancy features of synthesis, partitioning, etc., but they are enough to get a design running. What makes such a board so attractive is not the board itself, but the tools that come at no additional cost. Boards are a dime-a-dozen, but decent and *low-cost* development tools are an "arm and a leg and then some". I think these discussions should follow the theme "what types of features should we put in a low-cost tool". Provide almost any kind of board with good and inexpensive tools, not the fanciest low-cost board with tools costing over $1k. On a slightly different subject, how many people would be interested in a >$200 FPGA based board over some of the commercially available DSP boards? If I had a choice between a single FPGA (small) based board with no software and a DSP board ($89) with a stereo codec, memory, compiler, windows interface, etc., there is no question - I would take the DSP board. Am I alone? - Mike -- Michael J. Wirthlin Brigham Young University - Electrical Engineering Department Reconfigurable Logic Laboratory (801) 378-7206Article: 1423
eddie@merlion.singnet.com.sg (q) writes: >I could not understand the 'underscore' deviations of the respective >counters. Moreover for CBD48_4(CAO,[Q0..Q7],CAI,EN), there is no clock. >How can this be a down-counter ? The XXX_N macros are submacros of the actual function block, which is too complex to fit into a single cell. The real thing is CBD48. The software links the submacros for you, and you only have to care about the signals given in the CBD48 declaration. -- Segmented Memory Helps Structure SoftwareArticle: 1424
In article <3s43nh$qsp@chaos.kulnet.kuleuven.ac.be>, Pete <peter.sels@student.kuleuven.ac.be> wrote: >In article <3s3olf$62r@rc1.vub.ac.be>, tw38966@vub.ac.be (SH.RYU KIM HOFMANS) says: >> >> >>Can someone tell me if Altera has a technical support email adress ? >> >>Thanx in advance !!! >> Try sos@altera.com. If you can't wait, call 1-800-800-EPLD ------------------------------------------------------------- - Name: Hing-Fai Lee Address: Bell-Northern Research - - Phone: 613-765-2097 Dept 1D15, Mail Stop 170 - - FAX: 613-763-2108 P.O. Box 3511, Station C - - Email: crm182c@bnr.ca Ottawa, Canada, K1Y 4H7 - ------------------------------------------------------------- - Disclaimer: I do not speak for BNR nor BNR speaks for me. - -------------------------------------------------------------
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