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In article <3u0sgi$bac@sun1000.ci.pwr.wroc.pl>, Jarek Lis <lis@asic.ict.pwr.wroc.pl> wrote: > > >Long time ago I heard about Intel Flexlogic, as a good chip for hobbyist. >I know it was sold to Altera. >Question: > >Does Altera still sell them? >Are tools for programming them still freely avalaible (where?). >When I can find short description of them? >Jaroslaw Lis >| lis@ict.pwr.wroc.pl | Institute of Engineering Cybernetics | ----------------------------------- Altera still gives away that Intel software PLDShell. The devices are still the same but Altera calls them FLASHlogic. Same numbers and such. -Steve Walz rstevew@armory.comArticle: 1576
> > Does anyone have feel for what FPGA software is good > and inexpensive for implementing decoders and counters etc. > I currently have Altera software but would like to use other > mfg's. I need more density and lower power. > > Thank-In-Advance. > > Try looking at Atmel "Figaro" software. It has a very good automatic macro generator.Article: 1577
In article <3ugv3l$24m@odb.rhein-main.de>, lebert@odb.rhein-main.de (Hans Jörg Lebert) writes:
>
>I'm programming a microcode-controlled processor in VHDL using Synopsys V3.3a and
>map it onto a Xilinx FPGA using XACT V5.0.
>
>This step works fine but recreation of VHDL code from the mapped and routed design
>with "xnf2vss" from XACT tools generates a VHDL code which cannot be compiled successfully
>with Synopsys.
>
>This abnormal behaviour comes into beeing when RAM16X1 or RAM31X1 instances are used.
>
>The Xilinx tool "xnf2vss" cannot make distinctions between RAM16X1 and RAM32X1 components!
>
> Does anybody detect the same error and if so does any workaround exist?
>
>Hans Joerg
Hi,
I don't know how to workaround your problem but I know that the bug is fixed in the
XILINX SYNOPSYS INTERFACE V3.3.0
Vincent Rowley
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Vincent Rowley Laboratoire de Vision et
Systemes Numeriques
Universite Laval
Cite Universitaire
Quebec, Canada
e-mail: gel101@gel.ulaval.ca G1K 7P4
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Article: 1578
Does anybody have the pinouts needed to program the >44 pin isp
(or non isp) 1000 series devices. I'll be dam*ed if I'm going to
pay hudreds of dollars for an adapter that I might use once.
I have a Data I/O 2900. And yes, I know that I won't be able to
run test vectors...
TIA, Keith Brown
PLD Designs (416)241-8846/kdbrown@bix.com/ac058@torfree.net
--
----------------------------------------------------------------------------------------------------------
Keith D. Brown |
kdbrown@bix.com | witticisms wanted
ac058@torfree.net |
Article: 1579Does anyone know what NeoCad means when it reports "xxx CIRCUIT LOOPS FOUND AND DISABLED" where xxx is some (often very large) number? I though it might be a reference to asynchronous loops in my design, though I don't think there are any. So, I created a test design containing several deliberate asynchronous loops. NeoCad did not report any "circuit loops found" in this design. My input file is EDIF created from Verilog by Exemplar CORE and my target technology is ORCA 2C26 an 2C40. If anyone has any suggestions or thoughts, I'd love to hear them. Thanks. Chuck Gollnick Arnet Corporation Nashville, TN chuckg@arnet.comArticle: 1580
Not to long ago, I posted a message re: meeting women of the former
soviet union through romance ads.
In August, Olga will travel to Moscow from her home in Kiev, Ukraine.
In Moscow, Olga will have a much easier and cost efficient means to place
your personal romance ad throughout Russia.
Last week I received the following from Olga:
"I have already sent your ad to the papers in such towns: Moscow,
St. Petersburg, Vladimir, Kazan. At nearest future I will send your ad to the
paper in some more 12 towns of Russia, where papers are published.
Some times (in winter, spring & now) I placed your ad in other papers,
but they are not most popular paper in Moscow and some large cities of Russia.
Besides, I am continuing to place your ad in papers of Ukraine. I
promise to place your ad in some other papers when I will come to Moscow in
August. I am glad that you have received fairly many letters from Russian &
Ukrainian girls and I think you will received some more ones and will find
your ideal in my country soon.
I thank you very much ones more for your kindness & your help.
My best wishes,
Olga"
This isn't a scam - call it panhandling if you want. . . I sent her $40
or $50 and I've received over 45 responses. Unlike placing romance ads in
the U.S., women from the former USSR respond. Although one would guess the
are doing so in the hopes of American citizenship, I haven't found it so.
Olga lives in Kiev, Ukraine (population 3 million) and will travel to
Moscow in August to visit her father. If you were to send a letter this
week, she would receive it in time. The population of Moscow is 10 million
-- (3 times the size of Los Angeles.)
Feel free to send a letter and ask her your questions. She will be happy
to respond.
Olga's address:
Ukraine
Kiev 253121
Dekabristov Street 5 - 178
Olga Kozmina
I am posting anonymously because of the flames and volume of inquiries
that would result otherwise. I think those who are truely interested will
take the time to write.
_____________________________________________________________________________
To: probable flamer
Subject: polite note
Although Olga has never seen a newsgroup nor heard of "net-etiquette,"
she believes that offering lonely singles the possibility of romance exceeds
the cost of angering those who feel the net shouldn't be used in this fashion.
IHA (I humbly ask) that you not flame the postmaster of this site.
peace. . .
Article: 1581Hi there, I'm looking for stuff on FPGA's/CPLD's comparison. Therefore: 1. Is there a PREP Web server somewhere? 2. Is PREP data posted somewhere else? 3. IS there other sources for comparative studies or results? Thanks in advance, MosheArticle: 1582
In article <1995Jul21.024121.15614@super.org> romance@in.the.former.USSR.ua writes: > loads of trully relevant stuff that is about as on topic as one could hope > This isn't a scam - call it panhandling if you want. . . I sent her $40 >or $50 and I've received over 45 responses. Unlike placing romance ads in If I was sending money , I would at least remember what I was sending :-) >_____________________________________________________________________________ >To: probable flamer >Subject: polite note > > Although Olga has never seen a newsgroup nor heard of "net-etiquette," >she believes that offering lonely singles the possibility of romance exceeds >the cost of angering those who feel the net shouldn't be used in this fashion. > IHA (I humbly ask) that you not flame the postmaster of this site. > >peace. . . > NO WAY..... ( :-) :-) ) How do I send a flame to the postmaster? this message seems to have been gatewayed thru super.org, so flames to them is probably not apropriate. And who is this *&^$%^%$^#$% that posts anonymously, writes !(polite) notes and then !(humbly) ask us not to be pissed with this flagrant waste of c-a-fpga with this crap???? Am I "angry" ??? you bet. Most people are, when a neighbour brings their dog onto your front lawn to do dodo. All the best (except to this num-nut) Philip Freidin (posting !(anonymously))Article: 1583
Has anybody experienced any difficulties with Xilinx XACT ver 6.0 ?Article: 1584
hi, we recently purchase Altera V 5.2 software which we are planning on installing on a DEC Alpha with OSF/1. the vendor told us that support for Alpha platforms will be removed in the future. can anybody confirm this ? also are other fpga/vlsi cad tool vendors also planning on removing support for DEC Alphas ? -- cheers, yadav email: yadav@cse.iitb.ernet.inArticle: 1585
From: suzanne@world.std.com (Suzanne Southworth)
>Jean, John and I are going to send you some dog-food for your hilarious
>drive. I am making up my own label with my face, my son's face and one
>of my shelties' faces on an alpo can!
>
> - Suzanne Southworth
Although 23 letters were positive reactions like Suzanne's, 2 were negative.
One of the two negative being from "dean@rb.unisys.com" (Dean Ranger) with:
>John, I'm puzzeled; why the dog food drive for Joe Costello? Do you also
>feel threatened by Cadence's Services Division or is this just a ploy to
>get more publicity for your consulting business? Since Art feels so
>threathened by Cadence's competion that he refuses to let Cadence Spectrum
>Design (formerly Unisys employees) use Synopsys software, might he not
>also consider your own "consulting" (services) business a threat and
>refuse to let you use Synopsys software? It seems to me that we need to
>realize that it's Art De Gues who is acting like a dog fighting over a
>bowl of dog food; so I propose a dog food drive for Art. Better yet,
>split the dog food between Cadence, Mentor, and Synopsys.
>
> - Dean Ranger, Unisys/Cadence Spectrum Design
Whoa! Dean! WHOA!!! I'm completely lost here. I didn't say a single word
about Cadence Spectrum Design in the dog food drive announcement. Joe's the
one who brought up the dog food metaphor which raised quite a few chuckles
and caused the humorous reactions. Everyone talked about it. It was even
in that week's EE Times. Joe & I have never been shy around each other. By
rights, since Joe created the metaphor, I felt he deserved the good natured
fun associated with it. (And I'm simply stumped as to *what* this has to do
with Cadence Spectrum services...)
- John Cooley
the ESNUG guy
P.S. Anyway, keep those cans of / checks for dog food coming! :^)
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 3567 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 1586Hi, If anyone has experience in programming FLEX 8000 chips, PLEASE read on. We're trying to register some of our outputs in the Input/Output Register Cells (I/O Cells or Peripheral Cells) that are built into the FLEX 8000 architecture. (We're using the 81188's) The Max+Plus II (v. 5.11) should automatically use this registers for optimization, since we are setting the I/O Cell Registers option under the Global Logic Synthesis OPtions Menu). However, the compiler is using regular flip-flops which don't give us the fast clock to output times we need. Has anyone had success in utilizing the I/O cell registers? Thanks in advance, Ross Yu MIT Media LaboratoryArticle: 1587
Hi, If anyone has experience in programming FLEX 8000 chips, PLEASE read on. We're trying to register some of our outputs in the Input/Output Register Cells (I/O Cells or Peripheral Cells) that are built into the FLEX 8000 architecture. (We're using the 81188's) The Max+Plus II (v. 5.11) should automatically use this registers for optimization, since we are setting the I/O Cell Registers option under the Global Logic Synthesis OPtions Menu). However, the compiler is using regular flip-flops which don't give us the fast clock to output times we need. Has anyone had success in utilizing the I/O cell registers? Thanks in advance, Ross Yu MIT Media LaboratoryArticle: 1588
Hi Anyone out there with feedback/comment/critism of Xilinx EPLD's? I need to make decision whether to use Altera or Xilinx in a new design. I am already using Xilinx XC3195A FPGA's but need fast CPLD/EPLD devices on the same board Thanks- PETER FENN.Article: 1589
I would like to know about (in)official documents of AMD or others on programming the Mach210 and Mach230 PLD's. Are they programmed like GALs (serial data and shifting) or like PALs (adressing of the fuse Matrix)? What's maximum speed of programming and how critical is the timing? Thank you. Jozsef Ludvig Lehrstuhl fuer Informatik V Universitaet Mannheim ludvig@mp-sun1.informatik.uni-mannheim.deArticle: 1590
> Hi > Anyone out there with feedback/comment/critism of Xilinx EPLD's? > I need to make decision whether to use Altera or Xilinx in a new design. > I am already using Xilinx XC3195A FPGA's but need fast CPLD/EPLD devices on the same board > > Thanks- > PETER FENN. We have been using the Lattice ispLSI parts for the past two years. The development tools are just easy to learn. They provide nice macros, and you can do a lot with them with much of ease. No schematics unless you are willing to spend a few thousand bugs. Programming them in-circuit is also a plus. On the otherhand if you have Xilinx EPLD tools, equations are the best way to do. I have the package and never used it. So no comments. We use Xilinx with the Viewlogic Interface and it is easy to do. Once the desing is fixed I think Xilinx is good - on the reliability aspects. jothi@singnet.com.sgArticle: 1591
Philip Freidin <fliptron@netcom.com> wrote: >In article <1995Jul21.024121.15614@super.org> romance@in.the.former.USSR.ua writes: [...] >If I was sending money , I would at least remember what I was sending :-) He did. It was money. :) [...] >How do I send a flame to the postmaster? this message seems to have been >gatewayed thru super.org, so flames to them is probably not apropriate. Flames no, but a notification yes. Since the "Sender" field is Super.org , the postmaster there should be interested in tracing it further (whether it did or did not originate there). From "whois" db: IDA/Supercomputing Research Center (NET-SUPER) 17100 Science Drive Bowie, MD 20715-4300 Netname: SUPER Netnumber: 192.31.192.0 Coordinator: Hammel, Randall S. (RSH) rsh@SUPER.ORG (301) 805-7414 -- Regards, victor holen@netcom.comArticle: 1592
The message will come from NeoCAD's TRACE tool or Timing Wizard. NeoCAD's TRACE static timing analysis tool will detect async circuit loops. It is a good practice to run TRACE after technology mapping to detect loops. It will also show you the design's logic limiting frequency and highlight excessive timing constraints. Fred Koons FPGA Applications Engineering AT&T MicroelectronicsArticle: 1593
zalc@eng.tau.ac.il (zalc) writes :- >Hi there, >I'm looking for stuff on FPGA's/CPLD's comparison. >Therefore: >1. Is there a PREP Web server somewhere? http://www.techwin.org/prep/prep.html Cheers, T.H.Article: 1594
zalc (zalc@eng.tau.ac.il) wrote:
: Hi there,
: I'm looking for stuff on FPGA's/CPLD's comparison.
: Therefore:
: 1. Is there a PREP Web server somewhere?
Not somewhere but - surprise, surprise - have a look at:
http://www.prep.org
Markus Wannemacher
Article: 1595
In article <1995Jul21.182843.964@media.mit.edu>, Ross Yu <rossyu> wrote:
>Hi,
>
> If anyone has experience in programming FLEX 8000 chips, PLEASE read on. We're
>trying to register some of our outputs in the Input/Output Register Cells
>(I/O Cells or Peripheral Cells) that are built into the FLEX 8000 architecture.
>(We're using the 81188's)
>
> The Max+Plus II (v. 5.11) should automatically use this registers for
>optimization, since we are setting the I/O Cell Registers option under the
>Global Logic Synthesis OPtions Menu). However, the compiler is using regular
>flip-flops which don't give us the fast clock to output times we need. Has
>anyone had success in utilizing the I/O cell registers?
>
Set individual logic option "I/O Cell Registers = ON" to I/O registers
, (not I/O pins !). Maxplus2 may or may not use IOC flops for IO if you only
set Global Logic Synthesis OPtions.
I am using MaxPlus2 v5.3. It works for me.
hope it helps,
Best Regards,
--------------------- My opinion only ------------------------------------------
Qian Zhang Bell-Northern Research, Ltd Ph.: (613) 765-2485
H/W System Modelling P.O. Box 3511, Station C Fax: (613) 763-4222
Ottawa, Ontario, Canada, K1Y 4H7 Email : qzhang@bnr.ca
--------------------------------------------------------------------------------
>Thanks in advance,
>
>Ross Yu
>MIT Media Laboratory
>
Article: 1596Ross Yu <rossyu> writes: > > We're trying to register some of our outputs in the Input/Output Register > Cells (I/O Cells or Peripheral Cells) that are built into the FLEX 8000 > architecture. > (We're using the 81188's) > > The Max+Plus II (v. 5.11) should automatically use this registers > for optimization, since we are setting the I/O Cell Registers option under > the Global Logic Synthesis OPtions Menu). However, the compiler is using > regular flip-flops which don't give us the fast clock to output times we > need. Has anyone had success in utilizing the I/O cell registers? > I had a hopefully similar problem when I wanted to use input flip flops. Here are my notes on what I did. Hope it gives you some clues. The documentation is certainly not clear on this. It took several calls to Altera support. get to top level save and check bring up compile window complete compile assign - logic options search all - (node name) - ok clock on name - ok individual logic options io cell register - ok okArticle: 1597
In article <DC1GCC.n10.0.queen@torfree.net>, ac058@torfree.net (Keith D. Brown) wrote: >Does anybody have the pinouts needed to program the >44 pin isp >(or non isp) 1000 series devices. I'll be dam*ed if I'm going to >pay hudreds of dollars for an adapter that I might use once. >I have a Data I/O 2900. And yes, I know that I won't be able to >run test vectors... > >TIA, Keith Brown > PLD Designs (416)241-8846/kdbrown@bix.com/ac058@torfree.net > I assume that you mean the Lattice 1032, 1048, 1048C devices. The isp1032, etc., are programmable via your computer's serial port. Lattice includes all the adapters and software you need when you buy the pds+ Fitter or Lattice isp starter kit. The pinouts are shown in the data book. I am confused a little by your question, are you using the pDS or pDS+ software for your designs. If not, how are you designing for these devices. Regards, Jeff HutchingsArticle: 1598
From: pwaddell@mfi.com (Pete Waddell)
>John, as Editor-in-Chief of Printed Circuit Design magazine I'm intimately
>familiar with all of the Cadence Allegro, Composer (Concept) and BoardQuest
>products. I alerted my associates upon hearing about your dog food drive
>for Joe Costello and we laughed so hard we cried. (John, you've outdone
>yourself this time!) I passed the hat around and collected $24.00, three
>washers, and one homemade Mentor POG disk for our beloved Joe. Please tell
>Joe we cheerfully wish him "Bon Appetit!"
>
> - Pete Waddell, Editor-in-Chief
> Printed Circuit Design magazine
From: "Anonymous" at Digital Equipment Corporation
>John, enclosed is a check for $11.00 to buy a 20 lb bag of "Kibbles'N Bits"
>as marked on your order form. Could you please take a marker & relabel the
>bag as "Quibbles On Bits" in "honor" of Cadence's decision to drop support
>of DEC platforms after protracted negotiations? Thanks for the relabeling!
In reference to my stating that I'll personally collect and deliver all the
dogfood to Cadence Chelmsford, Jeff Markham (markham@cadence.com) replied:
>I'll make sure the dobermans are aware of your delivery.
>
> - Jeff Markham, Cadence Design Systems
This explains much if Cadence has Dobermans wandering the hallways as part
of some sort of bizzare employee discipline/retention plan! :^)
- John Cooley
the ESNUG guy
P.S. Keep those letters with checks for / cans of dog food coming!
===========================================================================
Trapped trying to figure out a Synopsys bug? Want to hear how 3661 other
users dealt with it ? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
Article: 1599Let me try to answer: Non ISP MACHs are programmed in a parallel fashion (which is one reason to use non-isp parts in high volume production. Parallel always takes less time (and silicon area) than serial). It takes typically less than 15 secs to program the parts you mentioned, depending on the programmer. The specs are written conservatively. Timing is not critical. Delays can be longer, but not shorter. (There should be no unofficial docs available.) Hope that helps a bit. Greetings Uwe Kremmin AMD Munich
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