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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Authors (X)
X:
17797: 99/09/05: Newbie question: Reading FPGA programming?
17801: 99/09/06: Re: Newbie question: Reading FPGA programming?
18250: 99/10/10: Lattice 1016 replacement
18313: 99/10/14: Reading a Lattice ispLSI 1016
x:
51713: 03/01/20: Virtex2 configuration problem
55390: 03/05/07: Re: PCI Bridge Question
66497: 04/02/20: Re: Amontec problems...
x-guy:
28419: 01/01/12: Re: CRC - from long division to XOR, how?
28769: 01/01/24: Re: Xilinx will NEVER support Linux
x-guy@hotmail.com:
27943: 00/12/15: Re: Verilog or VHDL
28116: 00/12/21: Re: HOT AREAS IN FPGAs
X. Q.:
38687: 02/01/22: Gate level simu in ModelSim.
39601: 02/02/14: Spartan-II becomes Vertex.
39632: 02/02/15: Re: Spartan-II becomes Vertex.
39635: 02/02/15: Re: Spartan-II becomes Vertex.
39729: 02/02/18: Do I need to install software in order to use Multilinx?
39755: 02/02/19: Whether an FPGA & CPLD device has been spoiled.
39839: 02/02/21: Re: Do I need to install software in order to use Multilinx?
39842: 02/02/21: Need largest CPLD devices?
39903: 02/02/22: Re: Need largest CPLD devices?
40057: 02/02/26: Re: Need largest CPLD devices?
40060: 02/02/26: Spartan-2 chip;
40092: 02/02/27: Need comments on QuickWorks 9.1.
40571: 02/03/11: MP3 decoder.
X.Y.:
118137: 07/04/18: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals.
118172: 07/04/18: Re: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals.
118175: 07/04/18: Re: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals.
118273: 07/04/20: Re: Seeking the solutions of high speed interconnection for the long distance transmission of 3.3v/24MHz signals.
122352: 07/07/25: Question about Bottom-Up Incremental Compilation Methodology in Quartus II
122411: 07/07/27: Re: Question about Bottom-Up Incremental Compilation Methodology in Quartus II
122521: 07/07/30: Re: Question about Bottom-Up Incremental Compilation Methodology in Quartus II
122543: 07/07/31: Re: Question about Bottom-Up Incremental Compilation Methodology in Quartus II
122760: 07/08/06: Problem about clock switch in Quartus II 6.0
122805: 07/08/07: Re: Problem about clock switch in Quartus II 6.0
X0033$:
4292: 96/10/10: Re: FPGA for Reed-Solomon Codec
<16x20s@lv>:
6297: 97/05/10: gamma@arts
x86asm:
64940: 04/01/16: Good software to experiment with VHDL
65053: 04/01/19: Good/Affordable Stater kits
<x@thevoter.co.uk>:
31288: 01/05/17: The Voter 4957
<x@x.com>:
122034: 07/07/18: Re: Xilinx XC9536 current draw ?
<x@xxx.x>:
12364: 98/10/10: Re: Altera MAXPLUS2 V9 slow.
xabi:
145823: 10/02/25: Scrubbing in Virtex-4
145824: 10/02/25: Scrubbing in Virtex-4
Xanatos:
19215: 99/12/06: JTAG use after FPGA configuration on board
19295: 99/12/10: Altera APEX lpm modules in Synplify
19389: 99/12/17: Re: Altera Quartus 99.10
19465: 99/12/22: Working @ Home
19673: 00/01/07: Newbie question on CPU's
19962: 00/01/20: Re: Altera Quartus vs Xilinx Place and Route tools (help needed)
20637: 00/02/16: Simple (?) Question about FPGA Test/Demo Boards....
20645: 00/02/16: Re: Xilinx hold time problems...
21834: 00/04/03: Re: Error during synthesis
21999: 00/04/11: Clock Dividers
22085: 00/04/20: Re: PLD Timing, Tco?
22256: 00/05/03: Re: Beginner's Guide
22459: 00/05/09: Re: Altera Megafunction in Exemplar Leonardo
22475: 00/05/10: Re: Error with Quartus for Altera APEX20K device: clock skew is greater then data delay
23299: 00/06/21: Leonardo 2000 Comments?
23530: 00/06/28: PSN Generator
23533: 00/06/28: Re: PSN Generator
23544: 00/06/29: Re: PSN Generator
23769: 00/07/07: Re: Quattus Automatic clock Selection
45756: 02/08/05: Re: Gate level simulation in Quartus II
45775: 02/08/05: Re: Gate level simulation in Quartus II
45865: 02/08/08: Re: QUARTUS II V2.1 LINUX (C) ALTERA
45909: 02/08/10: Re: Does Altera Jam work?
47344: 02/09/24: Re: Altera Cyclone 'FPGA'
47369: 02/09/24: Re: Altera Cyclone low-cost FPGA chips?
48083: 02/10/10: Re: Sync Reset without clocks
48090: 02/10/10: Sync Reset without clocks
48689: 02/10/22: Re: High Performance FPGA's - Xilinx and ??????
48815: 02/10/24: Re: Quartus LogicLock problem
52235: 03/02/05: Re: Quartus II's VQM to EDIF.
55861: 03/05/22: Re: Xilinx announces 90nm sampling today!
57051: 03/06/22: Re: What's the difference between ASIC and FPGA?
Xateta:
52672: 03/02/18: Verilog failed,please help
52738: 03/02/20: Re: Verilog failed,please help
52812: 03/02/23: Force a rising edge of clk
52888: 03/02/25: Help,please,Verilog
Xavier:
75031: 04/10/25: ISE and Clocks
Xavier T:
94952: 06/01/19: Re: Raggedstone specifications ...
95320: 06/01/22: Re: Raggedstone specifications ...
95620: 06/01/24: Re: Raggedstone specifications ...
102295: 06/05/14: Raggedstone IO bracket ?
102296: 06/05/14: Amontec Komodo board ?
102578: 06/05/17: Re: Raggedstone IO bracket ?
xavier.tastet@gmail.com:
93268: 05/12/17: rs232 and picoblaze :)
94788: 06/01/17: Raggedstone specifications ...
94795: 06/01/17: Re: Raggedstone specifications ...
94798: 06/01/17: Re: Raggedstone specifications ...
xchecker:
40607: 02/03/11: FPGA download fails
xcr3064xl:
132076: 08/05/12: Programming XCR3064xl - voltage at output stuck at 0
132098: 08/05/13: Re: Programming XCR3064xl - voltage at output stuck at 0
132099: 08/05/13: Re: Programming XCR3064xl - voltage at output stuck at 0
132123: 08/05/14: Re: Programming XCR3064xl - voltage at output stuck at 0
132150: 08/05/15: Re: Programming XCR3064xl - voltage at output stuck at 0
xcv800:
155018: 13/03/29: xcv800 free design tools
xcvjb:
41469: 02/03/29: position
41489: 02/03/29: Re: position
0xdeadbeef:
131835: 08/05/03: Aldec Active-HDL 7.3 sp1 [stimulators]
131880: 08/05/06: Re: Aldec Active-HDL 7.3 sp1 [stimulators]
xdsd98123:
140072: 09/04/27: FPGA/DSP/Video Board
Xefteris Stefanos:
50718: 02/12/18: Power Estimation
<xeinth@hotmail.com>:
123306: 07/08/22: Re: Spartan-3A DSP vs. Cyclone III Power-wise
xenix:
123342: 07/08/24: OCM BRAM and PCC issues...
123740: 07/09/03: Help on ocm
123741: 07/09/03: Help on OCM BRAM intercafe and assembly code
123872: 07/09/06: load/read/ commands assembly PowerPC. Help Needed!
123901: 07/09/06: Re: load/read/ commands assembly PowerPC. Help Needed!
123934: 07/09/07: Re: load/read/ commands assembly PowerPC. Help Needed!
124054: 07/09/11: Re: load/read/ commands assembly PowerPC. Help Needed!
124104: 07/09/12: Re: Good VHDL reference?
124194: 07/09/14: Re: load/read/ commands assembly PowerPC. Help Needed!
124306: 07/09/18: Data-side BRAM
124740: 07/10/02: Re: load/read/ commands assembly PowerPC. Help Needed!
124901: 07/10/10: Compiler Options
124955: 07/10/12: Re: Xilinx OCM memory use limitations ?
125166: 07/10/17: IPs in MHS file
125224: 07/10/18: xilinx Edititons
125225: 07/10/18: Re: IPs in MHS file
125823: 07/11/06: ERROR:MDT - transparent bus interface connector
125862: 07/11/07: Re: ERROR:MDT - transparent bus interface connector
125933: 07/11/09: is marked OBSOLETE????
126043: 07/11/13: how to make ports visible?
126291: 07/11/19: Microblaze books
126294: 07/11/19: Re: VHDL language is out of date! Why? I will explain.
126536: 07/11/27: how to generate a linker script?
128767: 08/02/06: OPB timer Microblaze
128825: 08/02/07: Re: OPB timer Microblaze
130997: 08/04/08: MIG/Corgen to XPS core insertion
130998: 08/04/08: Re: MIG/Corgen to XPS core insertion
131085: 08/04/09: Re: MIG/Corgen to XPS core insertion
131172: 08/04/14: Re: MIG/Corgen to XPS core insertion
134799: 08/09/01: how to built a CCD camera + FPGA ???
145079: 10/01/25: simulation+configuration with Ethernet Lite MAC (xilinx)
xenos:
84991: 05/06/02: Basics FPGA
84996: 05/06/02: Re: Basics FPGA
84999: 05/06/02: Re: Basics FPGA
85000: 05/06/02: Re: Basics FPGA
Xesium:
105103: 06/07/13: Re: Micorblaze post place and route simulation...
105139: 06/07/14: Post Place and Route simulation for Microblaze....
105928: 06/08/02: How can we fully utilize available BRAMs...
105930: 06/08/02: Re: Post Place and Route simulation for Microblaze....
105967: 06/08/03: Re: How can we fully utilize available BRAMs...
105976: 06/08/03: Re: How can we fully utilize available BRAMs...
105977: 06/08/04: profiling my application in microblaze...
106092: 06/08/07: Re: verilog versus vhdl
106541: 06/08/14: Microblaze power estimation with external memory..
106603: 06/08/15: High rate data transfer from off-chip mem to FSL co-proc...
106673: 06/08/17: Re: FPGA Memory Power
107562: 06/08/30: FF1152 Development board....
107563: 06/08/30: power measurement on the board...
108320: 06/09/07: ML 310 on board power measurement...
111523: 06/11/04: FSL microblaze to co-processor write problem...
111604: 06/11/06: Re: FSL microblaze to co-processor write problem...
111726: 06/11/08: Static Power vs. Temperature
111740: 06/11/09: Re: Static Power vs. Temperature
116773: 07/03/17: XPower crashes....
116774: 07/03/17: Re: XPower crashes....
128628: 08/01/31: Loading the design from Compact Flash...
128663: 08/02/02: Loading from Compact Flash on ML310...
128699: 08/02/04: Re: Loading the design from Compact Flash...
128741: 08/02/05: Re: Loading the design from Compact Flash...
129559: 08/02/27: ICAP attached to Microblaze on Virtex 2-pro..
129563: 08/02/27: Re: Loading the design from Compact Flash...
129564: 08/02/27: Re: Loading from Compact Flash on ML310...
129648: 08/03/01: Re: ICAP attached to Microblaze on Virtex 2-pro..
129699: 08/03/03: ICAP for readback on Microblaze...
129700: 08/03/03: ICAP for readback on Microblaze...
129904: 08/03/08: Re: ICAP attached to Microblaze on Virtex 2-pro..
141853: 09/07/13: Adder size vs Register size
141867: 09/07/14: Minimal size 1-bit adder....
152502: 11/08/29: DSP power consumption in Virtex devices...
157631: 15/01/09: Re: Parallel execution of Systemc code
xess:
3485: 96/06/07: low-cost FPGA development system offer
xfpgas:
60403: 03/09/11: FPGA Reconfiguration Question
60428: 03/09/12: Re: FPGA Reconfiguration Question
63083: 03/11/13: Re: ICAP Virtex2
<xgeorg@my-deja.com>:
28560: 01/01/17: Rconfiguration of FPSLIC
28641: 01/01/19: Reconfiguration of Armel fpga
xhtml champs:
152529: 11/09/05: PSD to XHTML Conversion, PSD to HTML, Joomla, Drupal, Wordpress
xia:
71241: 04/07/12: speed in FPGA
Xiang Gu:
46426: 02/08/29: Is there any Development Board for developing a MIL-STD-1553B protocol chip?
Xiangdong Li:
4109: 96/09/11: How to Begin with FPGA design?
4424: 96/10/27: PCI-compliant VHDL module
Xiao Wang:
8826: 98/01/30: Introduction book on Verilog/VHDL
<xiaocong9313@my-deja.com>:
18745: 99/11/11: Re: looking for Xilinx/Actel Board
<xiaoling.li@fme.fujitsu.com>:
136833: 08/12/08: encrypted and unencrypted design in the same device
<xiaoqiang@my-deja.com>:
27723: 00/12/05: test
27993: 00/12/19: simulation with ActiveHDL
28000: 00/12/19: how to bind xilinx lib to activeHDL?
xiaoxiao008:
128411: 08/01/24: Re: problems with Ultra DMA operations with ATA HDD
Xiaqing Wu:
114045: 07/01/03: Re: ISE Simulator radix question
Xie Jubo:
49580: 02/11/15: about schmatic symbol
<xiibweb@hotmail.com>:
82404: 05/04/12: 2 bit multiplier
82410: 05/04/12: Re: 2 bit multiplier
82948: 05/04/20: And gate in Neural Network
83009: 05/04/21: And gate in Neural Network
83092: 05/04/23: multiplier with one fixed value other user defined
_Xilinx:
159845: 17/04/10: versatile_FFT core has no output
160117: 17/06/01: baud_generator (16x baud) used in UART transmitter logic
Xilinx CAE Cory:
23154: 00/06/15: Re: foundation
23153: 00/06/15: Re: VHDL synthesis.
Xilinx Edm Manager:
109990: 06/10/09: Re: Just a matter of time
109999: 06/10/09: Re: Just a matter of time
Xilinx FAE from Insight SANKET:
39940: 02/02/22: Re: Problem While Downloading to Spartan 2 FPGA using JTAG
39941: 02/02/22: Re: Whether an FPGA & CPLD device has been spoiled.
39945: 02/02/22: Re: cross clock domain signals
40022: 02/02/25: Re: Is it possible to have an output FF in IOB, but a tri-state control FF outside of IOB?
40023: 02/02/25: Re: RAM question
40024: 02/02/25: Re: Floorplanner and then ??
40056: 02/02/25: Re: Spartan 2E JTAG
40178: 02/03/01: Re: Altera FPGAs
40179: 02/03/01: Re: stuck in state in Spartan-II!
40297: 02/03/04: Re: Minimum Size and Logic Sharing
40498: 02/03/07: Re: Xilinx ISE 4.1
41848: 02/04/08: Re: bad experience with Xilinx ISE 4.1i and Xilinx hotline suppot
42855: 02/05/05: Re: PDH MUX (E2,E3) and frame (E1,T1,E2 ...) based device VHDL examples
42856: 02/05/05: Re: LVPECL question?
42857: 02/05/05: Re: SelectRAM and DCM
42860: 02/05/05: Re: State Machine output assignment
42878: 02/05/05: Re: SelectRAM and DCM
53854: 03/03/25: Re: xst removes useful signals
53856: 03/03/25: Re: Can ModelSim PE/SE and XE coexist?
53913: 03/03/27: Re: Translating 2 CLKDLLs for SpartanII architecture
53930: 03/03/27: Re: Differential LVPECL Inteface of Spartan IIE
60703: 03/09/19: Re: Some question about using FPGA
Xilinx User:
121194: 07/06/27: Xilinx Modelsim XE-III 6.2g no more Systemverilog support?
121214: 07/06/28: Re: Xilinx Modelsim XE-III 6.2g no more Systemverilog support?
121650: 07/07/10: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121669: 07/07/11: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
122104: 07/07/19: Xilinx XST 9.2i.01 - still incomplete support for always @*
125730: 07/11/01: Xilinx EDK and Windows Vista?
130013: 08/03/12: Re: Virtex-5 FX when ? (III)
130014: 08/03/12: Re: Cyclone III FPGA Starter Kit: As USB device? Using JTAG terminal without Nios2?
130015: 08/03/12: Xilinx ISE Evaluation DVD 10.1 request...
Xilinx user:
119145: 07/05/13: Xilinx Webpack 9.1i.03 Verilog synthesis bug?
119717: 07/05/24: Went from Xilinx to Altera: Cyclone-II and I/O pullup?
119718: 07/05/24: Re: Dual Core or Quad Core when running Quartus 7.1
119797: 07/05/25: Re: ModelSim Memory Content import from Intel Hex
119847: 07/05/28: Quartus-II 7.1 Systemverilog support define `` ?
<xilinx@xaloc.upc.es>:
1363: 95/06/07: Xblox oo !!!!
1367: 95/06/07: About your Xblox problem
xilinx_user:
75523: 04/11/08: diode recovery time for Spartan 3
75534: 04/11/08: Spartan 3 reverse recovery time
83282: 05/04/26: Proper use of BUFGMUX and DCM in Spartan 3
85770: 05/06/15: Availability of Spartan3
85771: 05/06/15: Re: Pissed off with Xilinx - Spartan 3 [The Rest of the Story]
85828: 05/06/16: Re: Availability of Spartan3
85830: 05/06/16: Re: Availability of Spartan3
85915: 05/06/17: Update on availability of Spartan3
86020: 05/06/20: Re: Spartan 3 availability
86021: 05/06/20: Re: : Parts Back on Xilinx Online Store (www.xilinx.com/store)
103797: 06/06/11: How do I use the DDS core in a verilog flow?
103809: 06/06/12: Re: How do I use the DDS core in a verilog flow?
103858: 06/06/13: Re: How do I use the DDS core in a verilog flow?
103871: 06/06/13: Re: How do I use the DDS core in a verilog flow?
103875: 06/06/13: Re: How do I use the DDS core in a verilog flow?
103991: 06/06/16: Re: How do I use the DDS core in a verilog flow?
104020: 06/06/16: Re: How do I use the DDS core in a verilog flow?
136808: 08/12/05: How to save added signals to waveform viewer
Xin Xiao:
127884: 08/01/09: Synthesizing big RAMs
127990: 08/01/12: Re: Synthesizing big RAMs
128667: 08/02/02: Internal signal names in ModelSim
139574: 09/04/05: Modulo-10 counter
139581: 09/04/05: Re: Modulo-10 counter
139630: 09/04/07: Re: Modulo-10 counter
140288: 09/05/07: FPGAs and Cryptography
Xin Yang:
148640: 10/08/11: Re: Best clock output pin in Spartan-3
<xing1234@yahoo.com>:
80823: 05/03/11: To estimate the maximum frequency?
80967: 05/03/15: Memory gate count in ASIC and in FPGA
80986: 05/03/15: Re: Memory gate count in ASIC and in FPGA
81021: 05/03/16: Re: Memory gate count in ASIC and in FPGA
xingzhi:
115262: 07/02/05: 9.1i in Red Hat Enterprise Linux AS 64-bit
xipn:
90391: 05/10/12: User Library in ISE
xiuser:
81987: 05/04/05: re:IPIF
Xizen:
88767: 05/08/27: connecting block ram to datapath using bidirectional lines
88819: 05/08/29: re:digilent spartan 3 kit example project
88831: 05/08/29: re:beginner [ query : resources and guidance for a newbie]
xkey:
72794: 04/09/01: ISO Low cost Fpga / high I/O rate (so prob spartan3 pci/USB2 solution)
<xkkdkx@webnetsolutions.it>:
30594: 01/04/18: gay 7019
<xlhnui@hotmail.com>:
xman:
80708: 05/03/10: Re: looking for PCI board with fpga and 1394 interface
<xmkong@gmail.com>:
125729: 07/11/02: code hang after loading through gdb
125754: 07/11/02: Re: code hang after loading through gdb
125805: 07/11/06: Re: code hang after loading through gdb
xno:
59199: 03/08/12: Re: Offshore engineering
<xptwfssa@bigfoot.com>:
12201: 98/10/05: Owning Your Own Adult Interent Business Is Easy
xpyttl:
87426: 05/07/23: Re: Best Practices to Manage Complexity in Hardward/Software Design?
<xrerrn@nowhere.com>:
XSports1:
7656: 97/10/01: TITANIUM DRIVER
7654: 97/10/01: TITANIUM DRIVER
XSterna:
131687: 08/04/29: Chirp generator / CORDIC algo ?
131696: 08/04/29: Re: Chirp generator / CORDIC algo ?
131756: 08/05/01: Re: Chirp generator / CORDIC algo ?
131793: 08/05/02: Re: Chirp generator / CORDIC algo ?
131943: 08/05/08: Re: Chirp generator / CORDIC algo ?
133069: 08/06/17: Virtex5 FPGA Board and USB interface
133095: 08/06/18: Re: Virtex5 FPGA Board and USB interface
133192: 08/06/20: Re: Virtex5 FPGA Board and USB interface
133277: 08/06/23: Xilinx and RAM/ROM monitoring
xsteve:
103218: 06/05/29: Re: fpga uclinux, good starter board ?
103243: 06/05/29: Re: fpga uclinux, good starter board ?
xtalca:
47881: 02/10/07: .13 micron - what does it indicate
<xToriSpelling@FamousChicksxx.com>:
11677: 98/08/31: ALL FREE MEMBERSHIP SITE 8253
<xtr>:
121042: 07/06/23: How to create simple design?
121078: 07/06/25: Re: How to create simple design?
121208: 07/06/28: Re: How to create simple design?
Xu Qijun:
47595: 02/09/30: Re: Large Multiplexer
47815: 02/10/04: Re: FPGA with an EPROM on it?
48025: 02/10/10: Re: Parallel bus interface to a SmartMedia card.
XU QIJUN:
44047: 02/06/11: Re: where did my MHz go!
44175: 02/06/13: Re: Digital FM demodulator in FPGA-continue
44475: 02/06/21: Multiply by 8 with DLL in Spaertan-II.
44477: 02/06/21: Re: Multiply by 8 with DLL in Spaertan-II.
44617: 02/06/25: Re: Multiply by 8 with DLL in Spaertan-II.
44657: 02/06/26: Re: Multiply by 8 with DLL in Spaertan-II.
44670: 02/06/26: Re: Multiply by 8 with DLL in Spaertan-II.
Xuan Binh:
117046: 07/03/22: CRC check error
#XUE ZHONG#:
20102: 00/01/27: Lattice isp & FPGA
xueqing:
44992: 02/07/09: Re: CLK/2
xuweijun1983@gmail.com:
103838: 06/06/12: Can i use "burstcount" in my userlogic while using Altera SOPC builder 5.1?
xvhdl:
89085: 05/09/05: Re: Problem with interfacingT-VPACK with ALTERA QUIP5.0
89086: 05/09/05: Re: Problem with interfacingT-VPACK with ALTERA QUIP5.0
<xx>:
113811: 06/12/22: Help with xilinx simulation?
113813: 06/12/22: Re: Help with xilinx simulation?
113816: 06/12/23: Re: Help with xilinx simulation?
113846: 06/12/25: Re: Help with xilinx simulation?
113847: 06/12/25: Re: Help with xilinx simulation?
113848: 06/12/25: Re: Help with xilinx simulation?
113849: 06/12/25: Re: Help with xilinx simulation?
<xyjiang@ncic.ac.cn>:
109324: 06/09/23: Re: downloading bitstream on FPGA
xyz:
70884: 04/06/30: Re: Programming Altera Devices
xyzzy:
81738: 05/03/30: Bi-directional Pin Use
<xzljie@mail.com>:
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Compare FPGA features and resources
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