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On Nov 1, 1:42 pm, fazulu deen <fazulu.v...@gmail.com> wrote: > Dear all, > > Is it possible to implement power management unit(idle and active) in > FPGA? > > pls give suggestions to implement clock generation unit in FPGA.... > > regards, > fazal If you mean can you reduce the power in the FPGA when it is idle by adjusting the clock, yes. For Xilinx FPGAs, there is the BUFGMUX that will let you switch between two clock sources glitch free. If you have a fast clock for when the FPGA is active, and a slow clock for when it is idle, you can switch between them. Give some more details about what you need to do, and you might get some more help. But make sure you convince everyone it is not a homework problem first :) Regards, John McCaskill www.fastertechnology.comArticle: 125726
Similar structures can be used for contact de-bouncing. Use a single-pole double-throw switch, connect the two poles to Vcc and ground, and the moving arm to the FPGA input/output. When input senses a Low, make the output drive low. When the input senses High, make the output drive High. The switch easily overrides the output driver (make it weak), and the current spike lasts only a few nanoseconds. Doesn't work with a single- throw switch... Peter Alfke On Nov 1, 10:26 am, Petrov_...@hotmail.com wrote: > Has anyone implemented a circuit similar to the one below? > > VCC > + > | > .---------------o > | | > | | > | .-. > | | | > | | | weak pullup > | '-' > | | > | | > | .-----o > | | | ----- > | |\| | | | > --------| >-----|-------| PIN | > |/ | | | > | ----- > | > | floating > | or > | GND > /| | > To Internal Fpga Logic <---------< |------- > \| > (created by AACircuit v1.28.6 beta 04/19/05www.tech-chat.de) > > When the input pin is floating, the weak pullup causes the output > buffer to drive Vcc out, negating any extraneous noise that may exist > on the external line. > > When the input pin is driven to ground, the buffer momentarily tries > driving Vcc to ground but stops once the tristate is disabled. > > I've always just used a weak pullup on the input (no tristate buffer > at all) but another engineer in our group says this is a good way to > protect input pins from noise on undriven inputs. I'm a little > concerned about the brief period of time when the tristate buffer is > driving ground but he assures me that the fpga can handle it. > > Do you agree?Article: 125727
Hi, It is mentioned in xilinx data sheets that the the CoreConnect PLB bus has lots of great capabilities (e.g. address pipelineing , bursts etc.). I wonder how can I (as a user) can bring the PPC to use these capabilities, saying how can I force a burst write or read ? or how can I start a write while a read is in progress ? Is there a special SW command/syntax that make the PPC PLB Date side master to write a burst or does it do it automatically ? I will be greatfull for any help on this.. Thanks, Mordeahy.Article: 125728
On Oct 31, 12:17 am, John Williams <jwilli...@itee.uq.edu.au> wrote: > Hi, > > me_2...@walla.co.il wrote: > > I would like to debug a system containing a microblze and a ppc405. > > I'm > > using the xmd (gdb) for both of these units. I have a single mdm unit > > and a jtagppc (a single jtag interface). > > Is there a way to debug both of the processors simultaneously (via > > two > > GDBs). > > You shld be able to do this - using xmd, connect to both CPUs: > > % connect mb mdm > % connect ppc hw > > you may need to add other options to each connect statement, depending > on your FPGA and JTAG setup etc. > > This sequence would make the MB target 0, and the PPC target 1 > > xmd should then be listening on two different ports, one for the mb, and > one for the ppc. > > Since xmd tends to allocate ports from 1234 upwards, my guess is that > the mb will be on port 1234, and the ppc on port 1235 - the actual port > no's will be printed by xmd after each connection is made. > > Then, start each gdb, issue a target command > > target remote localhost:1234 (for microblaze) > > and > > target remote localhost:1235 (for the ppc). > > Some minor details may remain for you to work out, but this is an > overview of the process > > Regards, > > John Hi John, Thanks for your detailed answer. Another little thing - can the mdm & jtagppc live together ? how does the jtag chain looks like ? Thanks again, Mordehay.Article: 125729
Hi, I'm trying to do a design with dual ppc on an ml410 board with virtex 4. I first followed an example given on xilinx website and everything seems to be ok. But after I add only one more uartlite (there is already one in the original design), when I load the code through gdb, the code hang there and don't stop at the breakpoint at the beginning of the main function. What could possibly cause the code hang? Since I didn't touch the software, it has to be hardware problem. I checked the mhs file and made sure the second uart has same parameter as the first one. I'm a newbie in using FPGA and don't know what else I should check. Could anybody give me some direction what I should try? Thanks.Article: 125730
I noticed that Xilinx EDK 9.1 can be installed on Windows Vista (32-bit only), but it requires Xilinx ISE 9.1i, which isn't compatible with Vista at all. Is there a timetable for EDK support or planned support for Vista (32/64-bit)?Article: 125731
On Nov 1, 5:48 pm, me_2...@walla.co.il wrote: > Hi, > It is mentioned in xilinx data sheets that the the CoreConnect PLB bus > has lots of great capabilities (e.g. address pipelineing , bursts > etc.). > I wonder how can I (as a user) can bring the PPC to use these > capabilities, saying how can I force a burst write or read ? or how > can I start a write while a read is in progress ? > Is there a special SW command/syntax that make the PPC PLB Date side > master to write a burst or does it do it automatically ? > I will be greatfull for any help on this.. > Thanks, Mordeahy. The PowerPC will do single beat transactions (8 bit,16 bit, and 32 bit) and cache line transactions. If it is addressing memory that has been mapped as cacheable, it will automatically do a cache line transaction.The default is to do 32 byte cache lines, but you can set it to do two other sizes as well via one of the special machine state registers. I think that it is 16 and 64 bytes, but I would have to double check that. The PPC does not do any of the other burst transaction. The data and instruction caches each have their own master PLB interface, so one of them can be doing a read while the other is doing a write. I do not believe that an individual PPC PLB interfaces will do simultaneous reads and writes, but I would have to look at the Xilinx PPC users guide to verify that. The PLB bus will indeed support these modes. We have a PLB to DDR2 interface, and a PLB master interface that support simultaneous reads and writes for the single beat, burst and cache transactions, and it is a thing of beauty to watch that in action. Regards, John McCaskill www.fastertechnology.comArticle: 125732
Hi.. i have the counter which have 100 clock pulses and therefore a period of 1usec. Its an assignment and the requirements state that i cant change the period of the counter. Below is my code which i am not able to compile, stated that COUNTER2 cannot be synthesized, bad synchronous description. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.numeric_std.all; use ieee.std_logic_arith.conv_std_logic_vector; entity dualEdge is GENERIC (T_PROP : REAL := 0.0); PORT ( CLK : IN STD_LOGIC; --IN BIT := '0'; RESET : IN BIT := '0'; -- RESET Out1 : OUT BIT := '0'; -- Phase 1 signal Out2 : OUT BIT := '0'; -- Phase 2 signal end dualEdge; architecture Behavioral of dualEdge is CONSTANT del : TIME := T_PROP * 1 sec; begin PROCESS(CLK, RESET) VARIABLE CLKOUT : STD_LOGIC; VARIABLE ontime : INTEGER RANGE 0 TO 99:= 0; -- Counters for genrating the pulses VARIABLE COUNTER : INTEGER RANGE 0 TO 2000 := 0; VARIABLE COUNTER1 : INTEGER RANGE 0 TO 99:= 0; VARIABLE COUNTER2 : INTEGER RANGE 0 TO 99:= 0; BEGIN -- WAIT ON CLK; IF RESET='0' then -- Counters for generating the delays. COUNTER1 := 0; -- 0 Offset COUNTER2 := 0; -- 0 Offset COUNTER := 0; -- 0 Offset -- ELSIF (rising_edge(CLK)) THEN CLKOUT := NOT(CLKOUT); IF(COUNTER = 0) THEN ontime := 10; END IF; IF (COUNTER1 >= 99) THEN -- MOD 100 Counter COUNTER1 := 0; ELSE COUNTER1 := COUNTER1 + 1; END IF; -- Generate the Pulse IF (COUNTER1 < ontime) THEN Out1 <= '1'; ELSE Out1 <= '0'; END IF; IF (COUNTER >= 99) THEN -- MOD 100 Counter COUNTER := 0; ELSE COUNTER := COUNTER + 1; END IF; ELSIF (falling_edge(CLK)) THEN IF (COUNTER2 >= 99) THEN -- MOD 100 Counter COUNTER2 := 0; ELSE COUNTER2 := COUNTER2 + 1; END IF; END IF; END PROCESS; end Behavioral; Basically, everything that i include in the falling_edge loop is unable to synthesize. Kindly point out my errors and advise on the correct way to write it. Thanks a million to every advise.Article: 125733
On 2 Nov., 05:04, raull...@hotmail.com wrote:
[..]
> ELSIF (rising_edge(CLK)) THEN
>
> CLKOUT := NOT(CLKOUT);
>
> IF(COUNTER = 0) THEN
> ontime := 10;
> END IF;
>
> IF (COUNTER1 >= 99) THEN -- MOD 100 Counter
> COUNTER1 := 0;
> ELSE
> COUNTER1 := COUNTER1 + 1;
> END IF;
> -- Generate the Pulse
> IF (COUNTER1 < ontime) THEN
> Out1 <= '1';
> ELSE
> Out1 <= '0';
> END IF;
>
> IF (COUNTER >= 99) THEN -- MOD 100 Counter
> COUNTER := 0;
> ELSE
> COUNTER := COUNTER + 1;
> END IF;
>
> ELSIF (falling_edge(CLK)) THEN
>
> IF (COUNTER2 >= 99) THEN -- MOD 100 Counter
> COUNTER2 := 0;
> ELSE
> COUNTER2 := COUNTER2 + 1;
> END IF;
> END IF;
> END PROCESS;
> end Behavioral;
>
> Basically, everything that i include in the falling_edge loop is
> unable to synthesize. Kindly point out my errors and advise on the
> correct way to write it. Thanks a million to every advise.
You have two complete independend counters. So you could just split
the process in two, having one process with pos edge and one with neg
edge.
BTW Why do you usee bit instead of std_logic(_vector) as IO?
I wouldn't mix numeric_std and std_logic_arith
bye Thomas
Article: 125734What Mbps speed does DDR LVDS serializer in XC3S400 transmission support? (for use with TFT screens or backplane)Article: 125735
Ray Andraka wrote: > mk wrote: >> Actually what the FPGAs has should be named "dedicated/hard-wired >> carry ripple logic & routing" as there is not much "fast" about it. >> What would've been fast is if they added some carry look ahead logic. > Within a CLB, there certainly is carry look-ahead. It is abstracted out > in the user's guides as an implementation detail that is not visible to > the user. Be assured however, that there is a carry look-ahead going on > in the physical hardware. The XC4000 carry logic was pretty well documented, unless they implemented it completely different than it was documented. I would have called it a form of carry select logic using special properties of pass transistors to minimize delay. The internal details of the current devices are not as well documented, but still the internal carry should be faster than CLB based carry lookahead for most reasonable length adders. -- glenArticle: 125736
hey guys, i managed to get two signals already.. thanks for all the help and advices...Article: 125737
This looks like "voodoo design" to me. See http://foldoc.org/?voodoo+programming for the software equivalent. If you know what the problem really is, design for that. Use series or parallel termination to mitigate ground-bounce, for instance.Article: 125738
> why don't you have a look at actel's Igloo family? > http://www.actel.com/products/IGLOO/ > Recently they added support for the ARM cortex core, with plently of > other interesting capabilities. Very interesting.....thanks!Article: 125739
On Nov 1, 9:44 pm, xmk...@gmail.com wrote: > Hi, > > I'm trying to do a design with dual ppc on an ml410 board with virtex > 4. I first followed an example given on xilinx website and everything > seems to be ok. But after I add only one more uartlite (there is > already one in the original design), when I load the code through gdb, > the code hang there and don't stop at the breakpoint at the beginning > of the main function. What could possibly cause the code hang? Since I > didn't touch the software, it has to be hardware problem. I checked > the mhs file and made sure the second uart has same parameter as the > first one. I'm a newbie in using FPGA and don't know what else I > should check. Could anybody give me some direction what I should try? > Thanks. Try accessing memory from XMD: mrd <address> <# of 32bit words> mwr <address> <value> <# of 32bit word repetitions> Also, you can perform a "sanity" check on the PPC by using 'rrd' to read all the standard registers. If the same value is "smeared" over all the registers, besides the PC which will always have the lowest 2 bits be 0, then it usually means that the accesses timed out. I've seen issues with memory not being accessible and that causes the situation you are describing. -- MikeArticle: 125740
Hello, I want to synthesize my VHDL code targeting an ASIC design, and I want to do this using as primitive elements only NAND gates and d-flip- flops. So, basically what I think I have to do is either build a new library for the synthesizer containing only what I want to use, or use an existing library excluding all the "building-blocks" I don't want. I should make clear that I am only interested in getting an RTL schematic of my synthesized-design, and not getting any back- annotation information. Does anyone have any suggestions on how to do this? I am using Mentor Graphics tools (Leonardo, Precision) but if someone can suggest a solution even with Cadence tools (or even the rtl- schematic viewer of xilinx-ISE) it would be greatly appreciated. Thanks in advance George (mail: giorgos.puiklis aat gmail.com )Article: 125741
You can probably find this kind of information on Xilinx' website and browsing through the apps notes. But more specifically, if you find a hardware serializer on Spartan3 (or derivates), please let us know. You've found a hidden component in this family. But I bet you meant generic DDR support datarate on the Spartan3 family I/O, didn't you? Luc On Fri, 02 Nov 2007 00:16:17 -0700, kgll8ss@yahoo.com wrote: >What Mbps speed does DDR LVDS serializer in XC3S400 transmission >support? >(for use with TFT screens or backplane)Article: 125742
On Fri, 02 Nov 2007 14:46:43 -0000, giorgos.puiklis@gmail.com wrote: >Hello, > >I want to synthesize my VHDL code targeting an ASIC design, and I want >to do this using as primitive elements only NAND gates and d-flip- >flops. > >So, basically what I think I have to do is either build a new library >for the synthesizer containing only what I want to use, or use an >existing library excluding all the "building-blocks" I don't want. I >should make clear that I am only interested in getting an RTL >schematic of my synthesized-design, and not getting any back- >annotation information. > >Does anyone have any suggestions on how to do this? > >I am using Mentor Graphics tools (Leonardo, Precision) but if someone >can suggest a solution even with Cadence tools (or even the rtl- >schematic viewer of xilinx-ISE) it would be greatly appreciated. > >Thanks in advance > >George (mail: giorgos.puiklis aat gmail.com ) Almost all synthesis tools have commands like set_dont_utilize or set_dont_use. You can set all the cells you don't want to don't use and do your synthesis. But I think you will find it difficult to convince most synthesizer without an inverter. They don't like making their inverters from nands so you need to add inverters and change them back to nands manually/scriptually (?) later.Article: 125743
<giorgos.puiklis@gmail.com> wrote in message news:1194014803.047020.254210@z9g2000hsf.googlegroups.com... > Hello, > > I want to synthesize my VHDL code targeting an ASIC design, and I want > to do this using as primitive elements only NAND gates and d-flip- > flops. > > So, basically what I think I have to do is either build a new library > for the synthesizer containing only what I want to use, or use an > existing library excluding all the "building-blocks" I don't want. I > should make clear that I am only interested in getting an RTL > schematic of my synthesized-design, and not getting any back- > annotation information. > > Does anyone have any suggestions on how to do this? > > I am using Mentor Graphics tools (Leonardo, Precision) but if someone > can suggest a solution even with Cadence tools (or even the rtl- > schematic viewer of xilinx-ISE) it would be greatly appreciated. > > Thanks in advance > > George (mail: giorgos.puiklis aat gmail.com ) If you're targeting an ASIC, use the ASIC synthesis tools. You'll get different synthesis results for the same code from XST, Quartus, Synplify, Synopsys, Mentor, Cadence.... I don't believe the results you get from an FPGA tool will give you a strong correspondence to your ASIC synthesis results. Good luck with your efforts, - John_HArticle: 125744
Be specific. What do you mean by "this" ? Your posting is #10 in a thread... Peter Alfke On Nov 2, 3:10 am, "RCIngham" <robert.ing...@gmail.com> wrote: > This looks like "voodoo design" to me. > Seehttp://foldoc.org/?voodoo+programmingfor the software equivalent. > > If you know what the problem really is, design for that. Use series or > parallel termination to mitigate ground-bounce, for instance.Article: 125745
On Nov 1, 8:40 pm, "Xilinx User" <anonym...@net.com> wrote: > I noticed that Xilinx EDK 9.1 can be installed on Windows Vista (32-bit > only), > but it requires Xilinx ISE 9.1i, which isn't compatible with Vista at all. > > Is there a timetable for EDK support or planned support for Vista > (32/64-bit)? The answer *should* be on this page: <http://www.xilinx.com/ise/ ossupport/index.htm>. But it's not. I always get quite grumpy when the EDK version lags the ISE version significantly. I've never seen the "other guy" do that. Nudge, nudge.Article: 125746
ISE 9.2i supports Vista32, so you'll have to use EDK 9.2. Our release in Q1 of next year will release all tools at the same time (ISE, EDK, Sysgen, AccelDSP, PlanAhead, ChipScope, MIG). Steve <ghelbig@lycos.com> wrote in message news:1194020895.679836.45540@e9g2000prf.googlegroups.com... > On Nov 1, 8:40 pm, "Xilinx User" <anonym...@net.com> wrote: >> I noticed that Xilinx EDK 9.1 can be installed on Windows Vista (32-bit >> only), >> but it requires Xilinx ISE 9.1i, which isn't compatible with Vista at >> all. >> >> Is there a timetable for EDK support or planned support for Vista >> (32/64-bit)? > > The answer *should* be on this page: <http://www.xilinx.com/ise/ > ossupport/index.htm>. But it's not. > > I always get quite grumpy when the EDK version lags the ISE version > significantly. > > I've never seen the "other guy" do that. Nudge, nudge. >Article: 125747
glen herrmannsfeldt wrote: > Ray Andraka wrote: > >> mk wrote: > > >>> Actually what the FPGAs has should be named "dedicated/hard-wired >>> carry ripple logic & routing" as there is not much "fast" about it. >>> What would've been fast is if they added some carry look ahead logic. > > >> Within a CLB, there certainly is carry look-ahead. It is abstracted >> out in the user's guides as an implementation detail that is not >> visible to the user. Be assured however, that there is a carry >> look-ahead going on in the physical hardware. > > > The XC4000 carry logic was pretty well documented, unless they > implemented it completely different than it was documented. > > I would have called it a form of carry select logic using special > properties of pass transistors to minimize delay. > > The internal details of the current devices are not as well documented, > but still the internal carry should be faster than CLB based carry > lookahead for most reasonable length adders. > > -- glen > The internal carry chain structure had a wholesale change when either Virtex or VirtexII was introduced (I don't recall which now).Article: 125748
On Nov 2, 12:50 pm, <steve.l...@xilinx.com> wrote: > ISE 9.2i supports Vista32, so you'll have to use EDK 9.2. > > Our release in Q1 of next year will release all tools at the same time > (ISE, EDK, Sysgen, AccelDSP, PlanAhead, ChipScope, MIG). > > Steve > > <ghel...@lycos.com> wrote in message > > news:1194020895.679836.45540@e9g2000prf.googlegroups.com... > > > > > On Nov 1, 8:40 pm, "Xilinx User" <anonym...@net.com> wrote: > >> I noticed that Xilinx EDK 9.1 can be installed on Windows Vista (32-bit > >> only), > >> but it requires Xilinx ISE 9.1i, which isn't compatible with Vista at > >> all. > > >> Is there a timetable for EDK support or planned support for Vista > >> (32/64-bit)? > > > The answer *should* be on this page: <http://www.xilinx.com/ise/ > > ossupport/index.htm>. But it's not. > > > I always get quite grumpy when the EDK version lags the ISE version > > significantly. > > > I've never seen the "other guy" do that. Nudge, nudge.- Hide quoted text - > > - Show quoted text - When is EDK 9.2 supposed to be released? I had heard October, but WebUpdate still tells me that there are no updates right now (currently using ISE 9.1 nad EDK 9.1)Article: 125749
Why not use a weak keeper instead? Older Xilinx part used that internally on tristate lines. You have a weak buffer that drives the line to the voltage seen on the line. An undriven line will quickly be driven to either 1 or 0 due to initial noise. Another circuit driving the line will need to overcome the keeper current (similar to a switching sram cell). The upside is: There is no static current (unlike the pullup resistor). Kolja Sulimma
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Compare FPGA features and resources
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z