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Dear I need to simulate my EDK (8.2) project. Simulator is Modelsim SE 6.1c. I did following steps: ------------------------------------------- In order to compile COMPXLIB, I used the EDK simulation library compilation wizard Project -> Project options -> HDL and Simulation -> Simulation library path EDK library = C:/EDK/EDK_LIB Xilinx library = C:/Xilinx/Xilinx_LIB ------------------------------------------- However, I could not proceed, because of the message "Modelsim is not found. Please ensure that the simulator is correctly installed and/or necessary environment settings are available". Could anyone tell me "how to set up the environment" (or, how to points to the location of the simulator)? in EDK 8.2 ? Thank you in advanceArticle: 126001
> I've been looking into this too. I want to add a 1x PCI-Express edge > connector on my board for programming. Programming and JTAG testing > will be done by inserting the board into a PCI-Express 1x slot on my > test bench. Anybody else doing this? I've thought of something similar, but probably with a 'bed of few nails' rather than an edge connector. If you standardised in a 'footprint' of pads on the bottom of the board you could use a standard test rig with moveable top/edge locating strips. The problem with the edge connector is that you're left with a protruding connector on your PCB. NialArticle: 126002
"Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message news:4737aee0$1@clear.net.nz... > > You never work at the JED fuse-file level ? > I did fifteen years ago, but not these days.Article: 126003
Hi
I have a simple package that looks as follows:
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package RISC_Pkg is
-- Clock type
subtype T_clk is std_logic;
-- Reset type
subtype T_rst is std_logic;
subtype T_PIPE_REG_CTRL is std_logic;
subtype T_PREG_FE_DC_dest_pi is unsigned(7 downto 0);
subtype T_FLAG_PREG_FE_DC_dest_pi is std_logic;
subtype T_DATABUS_FE_DC_dest_pi is unsigned(7 downto 0);
subtype T_FLAGBUS_FE_DC_dest_pi is std_logic;
.....
subtype T_DATABUS_data_mem is unsigned(31 downto 0);
subtype T_FLAGBUS_data_mem is std_logic;
end package RISC_Pkg;
When I am running it with Modelsim I get the following error:
Package_LTRISC32ca_gen.vhd(355): near "package": expecting: ';'
But there is clearly a semicolon at "end package LTRISC32ca_PKG". I
havent forgotten any semicolons in between? Anyone an idea what the
issue could be?
Many thanks!
Article: 126004Sascha Frank wrote: > > When I am running it with Modelsim I get the following error: > > Package_LTRISC32ca_gen.vhd(355): near "package": expecting: ';' > Just found the error, I just have to leave out the package in the end then it works. end RISC_Pkg; Cheers!Article: 126005
On Nov 12, 9:55 am, Sascha Frank <Sascha.Fran...@gmx.net> wrote: > Hi > > I have a simple package that looks as follows: > > library IEEE; > use IEEE.std_logic_1164.all; > use IEEE.std_logic_arith.all; > > package RISC_Pkg is > > -- Clock type > subtype T_clk is std_logic; > > -- Reset type > subtype T_rst is std_logic; > > subtype T_PIPE_REG_CTRL is std_logic; > > subtype T_PREG_FE_DC_dest_pi is unsigned(7 downto 0); > subtype T_FLAG_PREG_FE_DC_dest_pi is std_logic; > subtype T_DATABUS_FE_DC_dest_pi is unsigned(7 downto 0); > subtype T_FLAGBUS_FE_DC_dest_pi is std_logic; > > ..... > > subtype T_DATABUS_data_mem is unsigned(31 downto 0); > subtype T_FLAGBUS_data_mem is std_logic; > > end package RISC_Pkg; > > When I am running it with Modelsim I get the following error: > > Package_LTRISC32ca_gen.vhd(355): near "package": expecting: ';' > > But there is clearly a semicolon at "end package LTRISC32ca_PKG". I > havent forgotten any semicolons in between? Anyone an idea what the > issue could be? > > Many thanks! Maybe just use "end package;" instead of "end package RISC_Pkg;"?Article: 126006
"Nial Stewart" <nial*REMOVE_THIS*@nialstewartdevelopments.co.uk> writes: > The problem with the edge connector is that you're left with a > protruding connector on your PCB. In my application this is not a problem. I've worked on PCI and PCIe designs, but I have never seen the cost of actually cutting the edge connector. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 126007
> Maybe just use "end package;" instead of "end package RISC_Pkg;"? Thanks for your answer Dave. The problem is, that I am using Modelsim 5.7 and that I have a tool that is compatible with Modelsim 6.1. In other words, I have to do a lot of work by hand so that it works with the older Modelsim version. The tool outputs component TEST is whereas the older Modelsim just accepts component TEST so there are some issiues. Anyone an idea for a workaround? Or do I have to right a PERL script that parses me the VHDL file and corrects it accordingly? Many thanks!Article: 126008
> I want to add a 1x PCI-Express edge > connector on my board for programming. I thought of various edge connector ideas. For some reason I don't like it, although it could be the most sensible. Here's another thought, take a SOIC 8 test clip, like these: http://www.pomonaelectronics.com/pdf/d5250-54_5437_1_01.pdf and trim the plastic such that the pins that would normally contact the IC can go through holes in the PCB. One could lay out a very compact (narrower than 0.15in SOIC) hole pattern that the clip could go into. If you only need four pins you could place the holes near to the PCB edge and have only one side of the clip engage the holes while the other side simply clamps against the outer edge of the PCB (the holes being about 0.1in from the edge). In fact, in the four contact case I would probably opt for an 8 pin DIP clip simply because of it being a lot more rugged. No decision yet, just going through various permutations and ideas now. -MartinArticle: 126009
Hi All, I've got three Spartan3Es daisy chained together in slave serial mode. I'm attempting to configure the 3 devices from an Atmel AVR reading the configuration from an SDCard. The DONE line is not going high after all the data has been shifted. As shown in the device datasheet, done is commoned and pulled high with a 330R resistor, so any of the devices could be holding done low. Q1: Will the bitstream be forwarded to DOUT even if the FPGA thinks the data it has recieved so far is invalid? At the moment DOUT is staying high. (BTW, INIT_B stays high whilst the data is being shifted) Q2: Is this the correct way to generate a binary file from 3 separate bit files? promgen -w -p bin -u 0 device1.bit device2.bit device3.bit -o array.bin Q3: As for bit ordering, I'm pretty sure this is correct: I'm reading the generated binary file (array.bin) 1 byte at a time and shifting the MSB first. I'm also shifting some dummy data (DIN='1') after the bitstream. Q4: If one of the devices is holding DONE low, will it stop the others from starting up? Thanks for any help you can offer AndyArticle: 126010
Students, Please ask your professor to file a XUP webcase for you, if he/she agrees that yours is a problem that requires our help. It is impossible for Xilinx to support all students directly, so our XUP program includes a means of support, through your professor. As an ex-professor myself, I actually appreciated it when a student came to my office hours. It is a very boring time, when no one shows up, and yet you are well aware that everyone can't possibly be a genius! So, do your prof a favor: pay them a visit, and maybe he or she will agree that the problem is one that they should send to our support group. The best case is that they solve your problem right there. The worst case is that the professor realizes that you are not stupid, and are willing to ask for help (a real asset when you then go to work somewhere -- employers don't really want to hire people who beat their heads against the walls, and stay "stuck"). AustinArticle: 126011
Hi, I use the Spartan display board (spartan 3E 1600), and I try to save a complete video frame (1280*1024) in a DDR. But I have many problem to simulate my code with the controler (from Mig 1.72, VHDL). Do you have a example, I would like to verify all information about Adress ( a10 never used, etc...). Is it possible to save continualy a line (exept when refresh), and not need to stop the write after a *8 burst. There is an example with this card, http://www.xilinx.com/products/devkits/HW-SPAR3E-DISP-DK-UNI-G-PROMO.htm but I receive a black screen when i program the FPGA with the file.bit (I receive a correct screen in direct Rx-> TX, with RAM only+, without DDR). Thanks in advance. BHBArticle: 126012
"Sascha Frank" <Sascha.Frank23@gmx.net> wrote in message news:fh9si2$d8j$1@aioe.org... > >> Maybe just use "end package;" instead of "end package RISC_Pkg;"? > > Thanks for your answer Dave. The problem is, that I am using Modelsim 5.7 > and that I have a tool that is compatible with Modelsim 6.1. > > In other words, I have to do a lot of work by hand so that it works > with the older Modelsim version. > > The tool outputs > > component TEST is > > whereas the older Modelsim just accepts > > component TEST > > so there are some issiues. Anyone an idea for a workaround? > Or do I have to right a PERL script that parses me the VHDL file > and corrects it accordingly? You are using VHDL93 syntax with VHDL87, try vcom -93 xx.vhd Hans www.ht-lab.com > > Many thanks! >Article: 126013
On Nov 12, 11:04 am, Andrew Greensted <ajg...@ohm.york.ac.uk> wrote: > Hi All, > > I've got three Spartan3Es daisy chained together in slave serial mode. > I'm attempting to configure the 3 devices from an Atmel AVR reading the > configuration from an SDCard. > > The DONE line is not going high after all the data has been shifted. As > shown in the device datasheet, done is commoned and pulled high with a > 330R resistor, so any of the devices could be holding done low. > > Q1: Will the bitstream be forwarded to DOUT even if the FPGA thinks the > data it has recieved so far is invalid? At the moment DOUT is staying > high. (BTW, INIT_B stays high whilst the data is being shifted) > > Q2: Is this the correct way to generate a binary file from 3 separate > bit files? > promgen -w -p bin -u 0 device1.bit device2.bit device3.bit -o array.bin > > Q3: As for bit ordering, I'm pretty sure this is correct: > I'm reading the generated binary file (array.bin) 1 byte at a time and > shifting the MSB first. I'm also shifting some dummy data (DIN='1') > after the bitstream. > > Q4: If one of the devices is holding DONE low, will it stop the others > from starting up? > > Thanks for any help you can offer > Andy I seem to recall that "bin" files are actually ascii strings of 1's and 0's, not actual binaries. Take a look at your files and see if the size seems to approximately match the sum of the .bit files (which are raw binaries with a header) or if they're about 8 times too big. In the past I have always used the raw hex format to create a file that is about twice the size of a raw binary (two ascii hex characters per byte with no other formatting). Then I convert that to binary with a simple C program and use the output for embedded programming. My promgen looks like: promgen -w -p hex -b -c FF -o outfile -u 0 first.bit second.bit Regards, GaborArticle: 126014
Gabor wrote: > I seem to recall that "bin" files are actually ascii strings of 1's > and 0's, Hi Gabor, The ascii file (with 1s and 0s in text) is the .rbt. I'm pretty sure that the .bin is the binary bitsream. AndyArticle: 126015
On Nov 12, 6:22 am, Pasacco <pasa...@gmail.com> wrote: > Dear > > I need to simulate my EDK (8.2) project. > > Simulator is Modelsim SE 6.1c. > > I did following steps: > > ------------------------------------------- > In order to compile COMPXLIB, > > I used the EDK simulation library compilation wizard > > Project -> Project options -> HDL and Simulation -> Simulation > library > path > > EDK library = C:/EDK/EDK_LIB > Xilinx library = C:/Xilinx/Xilinx_LIB > ------------------------------------------- > > However, I could not proceed, because of the message "Modelsim is not > found. Please ensure that the simulator is correctly installed and/or > necessary environment settings are available". > > Could anyone tell me "how to set up the environment" (or, how to > points to the location of the simulator)? in EDK 8.2 ? > > Thank you in advance It sounds like the environment variable MODEL_TECH is not set. I believe that the ModelSim install program should have set this for you. Look in your environment variables to see if it is set. Also, can you already run ModelSim outside of EDK? EDK has help information that walks you through what you need to do to get set up for simulation. In EDK, go to: Help->Help Topics->Procedures for Embedded Processor Design-> Simulation This will tell you what to do to get setup, including how to set environment variables. Regards, John McCaskill, www.fastertechnology.comArticle: 126016
Amit wrote: > Hello group, > > I'm new to this field and currently learning how 16v8 architecture is > designed. Of course, pretty confused but as my first experiement I > need to implement a logical function and also design multiplier using > 61v8. > > > does anybody know where I can get some information to be able to > complete this? > > Regards, > amit > With only 8 registers and product terms, you'd have to make it a bit serial multiplier, and even then the parallel multiplicand is going to limited in size. See the multipliers page on my website for details.Article: 126017
austin wrote: > Students, > > Please ask your professor to file a XUP webcase for you, if he/she > agrees that yours is a problem that requires our help. > > It is impossible for Xilinx to support all students directly, so our XUP > program includes a means of support, through your professor. > > As an ex-professor myself, I actually appreciated it when a student came > to my office hours. It is a very boring time, when no one shows up, and > yet you are well aware that everyone can't possibly be a genius! > > So, do your prof a favor: pay them a visit, and maybe he or she will > agree that the problem is one that they should send to our support > group. The best case is that they solve your problem right there. The > worst case is that the professor realizes that you are not stupid, and > are willing to ask for help (a real asset when you then go to work > somewhere -- employers don't really want to hire people who beat their > heads against the walls, and stay "stuck"). I assume that you wrote this message partly in response to my recent "EDK 9.2 install problem", though I can't tell because you started a new thread rather than respond to mine. In fact I wrote to comp.arch.fpga /after/ speaking to my supervisor about the problem - he agreed asking here would be a good idea. Not only do I know that Xilinx has a presence here, I could also see if this was a common problem among other Xilinx users. It seems that it is not a common problem, and is probably a defective install disk, so no need to open a WebCase anyway. -- Philip Potter pgp <at> doc.ic.ac.ukArticle: 126018
Nothing's ever completely secure, it just gets more difficult to crack. A platform depending on an encrypted code memory interface can be vulnerable in many ways. For example, when the code memory interface doesn't also authenticate. Regards, MarcArticle: 126019
Philip, Yes, this was in part a reply to you, but I had marked the thread "ignore" as I had already made a note to contact the support group, and find out what we were doing. C.A.F. is a good place to ask if others have the same problem: yes. And, unlike a webcase, Peter and I do read all of the postings (even if we do not choose to reply). In the past, we did not have a specific link for questions that professors used, but as of last week, now we do. So, for your professor, it should be easier to enter a XUP webcase now. The only rumor I have heard is that now that we have software releases on DVDs, they are more susceptible to scratching and damage if left without their covers, and may be ruined much more easily than a CD would be. So, if those DVDs were left out, and got tossed about, they may well be scratched, and won't work. AustinArticle: 126020
"m" <martin.usenet@gmail.com> wrote in message news:1194844702.155568.195590@s15g2000prm.googlegroups.com... > Looking for ideas to eliminate the programming connector and replace > it with pads/contacts on the board. This is both for cost and size > reduction as well as simplifying programming during manufacturing and > testing. > > One idea is to build a programming jig for each candidate board > containing a connector like this: > > http://www.samtec.com/technical_specifications/overview.aspx?series=OPP&menu=STANDARD_PRODUCTS > > > Any ideas? > > Thanks, > > -Martin You can look at a closeup of a spring-pin connector on page 6 of the DesignCon 2005 paper http://www.coe.montana.edu/ee/lameres/vitae/publications/4_trade/trade_012_connectorless_probing_advantages_1.pdf Precision Interconnect appears to be the folks that worked with Agilent to get the "soft touch" Logic Analyzer probe up and running. http://www.precisionint.com/HighSpeedData/SpringPin/ Another paper I saw suggests the spring pins are good for "up to 500" contact cycles though spring pins in general can have much better mating life, so please double-check the suggested mating cycles in any of your solutions. Because you're so concerned about cost, I'll assume you have a very high production. I'd suggest just going straight to a good spring-pin source and making your own probe block. By using the appropriate crown or point style of pin, you can avoid the added expense of gold-plating your board as may be needed for many of the rounded-tip spring pins. The pins are available with replaceable contact points so you can have your pre-assembled contact block with fixed receptacles and just replace the individual spring-loaded points as they wear. These "pogo pins" are available from many sources but Interconnect Devices - www.idinet.com - is the source that I've seen in ATE for decades. These pins are available through distribution as well so getting them shouldn't be a problem. It is a shame there isn't a market of simple connector headers like this pre-made, providing a simple ribbon cable connection. I've wanted contacts like these for all those unpopulated programming connectors on production (or near production) boards. Since my own needs are just the occasion board trouble-shoot rather than programming, I've considered putting something very rough together at various times but never managed to make it happen. If you want some custom stuff done for you and you're willing to go for the expense now for the savings in hassle and cost later, places like http://www.ironwoodelectronics.com do custom work and have experience with the pogo pins and the mechanics needed for a robust solution. Good luck, - John_HArticle: 126021
"Andrew Greensted" <ajg112@ohm.york.ac.uk> wrote in message news:fh9tm0$1ud$1@netty.york.ac.uk... > Hi All, > > I've got three Spartan3Es daisy chained together in slave serial mode. I'm > attempting to configure the 3 devices from an Atmel AVR reading the > configuration from an SDCard. > > The DONE line is not going high after all the data has been shifted. As > shown in the device datasheet, done is commoned and pulled high with a > 330R resistor, so any of the devices could be holding done low. > > Q1: Will the bitstream be forwarded to DOUT even if the FPGA thinks the > data it has recieved so far is invalid? At the moment DOUT is staying > high. (BTW, INIT_B stays high whilst the data is being shifted) > > Q2: Is this the correct way to generate a binary file from 3 separate bit > files? > promgen -w -p bin -u 0 device1.bit device2.bit device3.bit -o array.bin > > Q3: As for bit ordering, I'm pretty sure this is correct: > I'm reading the generated binary file (array.bin) 1 byte at a time and > shifting the MSB first. I'm also shifting some dummy data (DIN='1') after > the bitstream. > > Q4: If one of the devices is holding DONE low, will it stop the others > from starting up? > > Thanks for any help you can offer > Andy I use the GUI to generate my programming files. There are two styles of .bin files that can be generated through the GUI - one is MSbit first, the other is byte-reversed for LSbit first. My recollection is that the DOUT will only pass data once the first device is programmed so your file order will be from the first device to the last. If the DOUT on the first device never changes, assume the first programming file is bad and troubleshoot that situation first. If the first device programms bot the others don't, insert a couple hundred cycles of logic-1 data between the files. If you want to try both auto-generated .bin files through the Xilinx GUI, one is generated from the Generate Programming File property "Create Binary Configuration File" and the other by using the IMPACT tool directly through the Generate PROM, ACE, or JTAG File under the Generate Programming File process. If you "Prepare a PROM File" you get the option to generate a BIN Prom File Format. It's this .bin file that has the bits reversed in the byte relative to the promgen version. The low DONE shouldn't keep the other devices from programming. The DOUT stuck high should keep the other devices from programming. - John_HArticle: 126022
On Sat, 10 Nov 2007 19:00:18 +0000, Amit wrote: > On Nov 10, 10:49 am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> > wrote: >> On Sat, 10 Nov 2007 18:25:35 -0000, Amit <amit.ko...@gmail.com> wrote: >> >> >Hello group, >> >> >I'm new to this field and currently learning how 16v8 architecture is >> >designed. Of course, pretty confused but as my first experiement I >> >need to implement a logical function and also design multiplier using >> >61v8. >> >> >does anybody know where I can get some information to be able to >> >complete this? >> >> A GAL16V8, which I guess is what you mean, has only... - 8 bits of >> storage >> - 18 user I/O pins, of which one must be taken as a clock >> in most cases >> so your multiplier surely cannot be very big! You could make a >> multiplier with two 4-bit inputs and an 8-bit result... probably. If >> you have *lots* of 16V8s on a board, you could make a bigger >> multiplier. >> >> When I did a Google search for GAL16V8, the first hit I found was the >> Lattice data sheet. (I used to know those devices inside-out, but I >> haven't used one for so long that I thought I'd better remind myself of >> the details.) Not a bad place to start. -- >> Jonathan Bromley, Consultant >> >> DOULOS - Developing Design Know-how >> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services >> >> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK >> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com >> >> The contents of this message may contain personal views which are not >> the views of Doulos Ltd., unless specifically stated. > > > Hello Jonathan, > > Thanks for your response. you are right, I did download it but one > thing that I need to know how can I find a right flow? and associate it > with a multiplier 4 by 4? > it seems there are other controlling inputs such as Vcc (or maybe I'm > wrong) but is there any example of an adder for instance? > > Once again thanks. > amit The 16V8 is a 30 year old part, it's very tiny. Your question is like asking how to build a house out of one brick, you can't do it. However you can build a house out of a lot of bricks and in the same way you can build a multiplier out of a lot of 16V8s. You can implement 4 carry save adders in a 16v8 which you can use to build a Wallace tree. You can also implement a 6 bit look ahead adder with a V8 which you can use to sum up the carry save terms at the end of the pipe.Article: 126023
HT-Lab wrote: > "Sascha Frank" <Sascha.Frank23@gmx.net> wrote in message > news:fh9si2$d8j$1@aioe.org... >>> Maybe just use "end package;" instead of "end package RISC_Pkg;"? >> Thanks for your answer Dave. The problem is, that I am using Modelsim 5.7 >> and that I have a tool that is compatible with Modelsim 6.1. >> >> In other words, I have to do a lot of work by hand so that it works >> with the older Modelsim version. >> >> The tool outputs >> >> component TEST is >> >> whereas the older Modelsim just accepts >> >> component TEST >> >> so there are some issiues. Anyone an idea for a workaround? >> Or do I have to right a PERL script that parses me the VHDL file >> and corrects it accordingly? > > You are using VHDL93 syntax with VHDL87, try vcom -93 xx.vhd Or in the project.mpf file, in the [vcom] section, add or uncomment the line: VHDL93 = 1Article: 126024
Pasacco wrote:
> Could anyone tell me "how to set up the environment" (or, how to
> points to the location of the simulator)? in EDK 8.2 ?
Click up a shell, bash or cmd.exe
mkdir play
cd play
vcom
If this doesn't give you the vcom usage,
type "exit" to close the shell,
find vcom, and add it's location
to your path and try again.
-- Mike Treseler
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