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On Nov 14, 3:23 pm, "Symon" <symon_bre...@hotmail.com> wrote: > OK, but the point I'm trying to make is that schematics can be a good tool > to learn how the circuit is implemented _in_an_FPGA_. No they can't. Unless you are dealing strictly in terms of vendor megafunctions (and often even then), what you see or enter gets completely refactored by the tools when they go to implement what you've asked for. In contrast, something like a minimum sum of products expression, which students should learn to write by hand, is actually quite close to what really happens in a primitive PAL type architecture. Not that I'm arguing for HDL coding in MSP either - put in the unsimplified expressions that describe what you want; the tools are better at simplifying them (hand in hand with duplicating and expanding for fanout and speed) than you are. > The > correlation between what is drawn in the schematic and what ends up in the > FPGA's LUTs is closer than with an equivalent RTL design, helping the > beginner see which structures are good, and which are bad. Define "bad". Some things that are simple to enter will get expanded, but sometimes the expansion is an intentional optimization to compensate for fanout or propogation delay. You shouldn't design for that. Design simple expressions, which are what the tools are tested to compile. > > Nobody should be instantiating discrete gates in an FPGA (iobuffers > > and other special ones exempted), instead they should be writing > > equations - HDL code - that accomplish the intended function in a > > concise and comprehensible way. > > Usually this is true. However, some designs require extracting the fastest > possible timing from the FPGA, or the smallest resource usage. A designer > can code the design in RTL appropriately and hope the synthesis tool gets > the message or they can instantiate FPGA primitives in their RTL. You can't outsmart the tools by hand coding the general logic of your design entry like that, as they will refactor what you've done anyway. If you want something, you get it by using the constraints interface to the tools to specify what you need. > It's my > contention that a designer who has a grounding of the underlying structure > of the FPGA will be at an advantage, and one way to get that knowledge is to > design as a beginner with schematics. For architectures of the past, yes. For todays' architectures, the only designers who understand the underlying structure in the necessary details are those privy to the silicon vendor's trade secrets. Everybody else gets to work with the interface they provide - and most of their effort goes into the HDL interface and constraints mechanism, not the schematic entry. > Which is my point. Sometimes instantiation is useful for the reasons I > outlined above. Except that when you are coding the ficticious architecture offered, mostly you are fooling yourself.Article: 126101
cs_posting@hotmail.com wrote:
> On Nov 14, 3:23 pm, "Symon" <symon_bre...@hotmail.com> wrote:
>> OK, but the point I'm trying to make is that schematics can be a good tool
>> to learn how the circuit is implemented _in_an_FPGA_.
>
> No they can't. Unless you are dealing strictly in terms of vendor
> megafunctions (and often even then), what you see or enter gets
> completely refactored by the tools when they go to implement what
> you've asked for.
Any FPGA design source other than
a pure technology netlist is
completely refactored by the tools.
It's all abstraction.
The subject says "FPGA for hobby use".
If I fixed up cars for fun, I might
not want to also own a machine shop.
If I wanted to invest a few hours
wiring up some pseudo-TTL blocks
on a schematic just to make an LED flash,
I might just do it.
No worse than crossword puzzles or
posting on usenet :)
-- Mike Treseler
Article: 126102<cs_posting@hotmail.com> wrote in message news:1195073458.863809.291210@v3g2000hsg.googlegroups.com... > On Nov 14, 3:23 pm, "Symon" <symon_bre...@hotmail.com> wrote: >> OK, but the point I'm trying to make is that schematics can be a good >> tool >> to learn how the circuit is implemented _in_an_FPGA_. > > No they can't. Unless you are dealing strictly in terms of vendor > megafunctions (and often even then), what you see or enter gets > completely refactored by the tools when they go to implement what > you've asked for. > I disagree! Because I know that FPGAs consist of 4 input LUTs that feed FFs, I can design pipelined structures that are faster and smaller than if I had no clue as to how the logic is implemented in an FPGA. > > Not that I'm arguing for HDL coding in MSP either - put in the > unsimplified expressions that describe what you want; the tools are > better at simplifying them (hand in hand with duplicating and > expanding for fanout and speed) than you are. > Speak for yourself! ;-) > >> The >> correlation between what is drawn in the schematic and what ends up in >> the >> FPGA's LUTs is closer than with an equivalent RTL design, helping the >> beginner see which structures are good, and which are bad. > > Define "bad". > Slower, bigger, longer P&R, ... > > Some things that are simple to enter will get expanded, but sometimes > the expansion is an intentional optimization to compensate for fanout > or propogation delay. You shouldn't design for that. Design simple > expressions, which are what the tools are tested to compile. > > > You can't outsmart the tools by hand coding the general logic of your > design entry like that, as they will refactor what you've done > anyway. If you want something, you get it by using the constraints > interface to the tools to specify what you need. > Again, please speak for yourself. I can and do 'outsmart' the tools, particularly in pipelined designs. If I structure my VHDL so it can pipeline logic that neatly fits the 4 LUT followed by a FF, my design has fewer space and timing problems, and P&R runs faster. Or, if I code my design so that a clock enable signal gets routed directly to the FFs CE pin, I can take advantage of multi-cycle paths much more easily. > > > For architectures of the past, yes. For todays' architectures, the > only designers who understand the underlying structure in the > necessary details are those privy to the silicon vendor's trade > secrets. Everybody else gets to work with the interface they provide > - and most of their effort goes into the HDL interface and constraints > mechanism, not the schematic entry. > >> Which is my point. Sometimes instantiation is useful for the reasons I >> outlined above. > > Except that when you are coding the ficticious architecture offered, > mostly you are fooling yourself. > > I think that's nonsense. The basic structure of a V4 FPGA is still a 4-LUT followed by a FF the same as it was in an XC3000 20 years ago. To illustrate, here's a problem where you can search C.A.F. for examples. Population count. A circuit to count the number of '1's in a vector. If you know the FPGA is made of 4-LUTs you can do a much better job of coding it than if you don't. Anyway, I see from Google you had a brief exchange on a similar subject on comp.arch.embedded Oct.3rd with Ray Andraka. If he didn't change your mind, I'm sure I'm wasting my time also. :-( This thread is getting way off topic, and I think I've outlined my position fairly clearly. Good luck, Syms.Article: 126103
"austin" <austin@xilinx.com> wrote in message news:fhfgoh$m7b2@cnn.xilinx.com... > Symon, > > > You could play it through a sound card, and you could immediately tell > the difference, for example. > Hi Austin, That reminds me of the technician guys who can listen to PRBS patterns sent over PCM channels and tell you which of several PRBS's it is. You're right, the pattern matching of the brain is remarkable. Cheers, Symon.Article: 126104
Symon, The 'sush-sush' of 2E20-1 is very easy to hear, as it repeats every ~.75 or ~.5 seconds (T1 or E1) so that was not such a remarkable feat! And anything shorter (2E7-1) had audible tones that the tech could hear! After all, a LFSR (linear feedback shift register) is a PRBS (pseudo-random bit source) is only a PRNS (pseudo-random noise source), and not really random at all. Like any amazing feat, there is likely to be something simple behind it, so that any idiot can do it. Reminds me of what I saw on the news this morning, a fish market vendor was asked about the ban on crab fishing in the SF bay area, and were SF bay crabs really different?: her answer? "Grandpa Alioto swore that they tasted better from the SF bay, but we snuck some from Washington onto Mom's plate, and when told of what we had done, she said - never could tell the difference really ... dad couldn't either." AustinArticle: 126105
Hi, I apologize if this gets double-posted; I think that Google Groups may have eaten my first reply. (So this is attempt #2 :) > > You might find that Actel suits your needs ... > > >http://www.actel.com/documents/selguide.pdf > > > (It looks as though Actel carries some smaller ProASICPlus parts in a > > TQFP 100 package. Those parts have 2 PLLs and are Flash-based > > [reprogrammable, immune to SEUs, etc.].) > > Yes, however there's a big differnece between developing for these vs. > Altera or Xilinx SRAM parts: the toolchain is less integrated and thus > much slower, I'm not entirely sure what you mean by "less integrated" -- Actel's toolflow is completely integrated inside the Libero GUI, and is also completely automatable/scriptable from the command line, using TCL scripts. (While the toolflow *does* use Synplify for RTL synthesis, this is often viewed as a strong point due to the high quality of results achievable using Synplicity's software.) Work is being done all the time to improve the runtime and performance of the designs produced by the toolsuite; if you have a strangely-slow case, I would urge you to bring this to Actel's attention so that engineering can take a look at it. > and the programmer is outrageously slow and pricey for > what you get. If you are used to fully integrated toolflow, and to I believe that the FlashPro programmer comes with most of the Starter Kits, which I've always found were pretty well-priced. (I think that you can also purchase the standalone programmer separately, but to be honest, I don't recall its price or how it compares to other companies.) That said, if you've encountered any strange, slow-programming cases, you should bring it to Actel's attention. > It also seems that you can't get pullups on inputs, and instead of Not true :) I/Os in Proasic/Fusion/Igloo can be configured for numerous different I/O standards and have various features, including low power mode, internal pull-up resistors, Schmitt trigger for inputs, and selectable drive strength and slew rate. > merely being cautioned against using non-clock inputs as clocks, you > literally can't do it - meaning board designs with stupid mistakes Not true :) In general, non-clock I/Os in Proasic/Fusion/Igloo can drive internal clock buffers from basically any input. (There are some minor caveats where only certain I/Os can be used when employing specialized features, like quadrant clocks and certain PLL configurations and/or I/O bank configurations.) > On the other hand, if you prefer to do everything in simulation and > not make incremental trials in hardware, and you value synopsis over X Incremental trials in hardware are certainly encouraged :) Actel's Flash products are reprogrammable, and in practice, the toolflow is heavily optimized for high-quality, fast runtime. Again, if you've encountered an oddly slow case, it can't hurt to bring it to Actel's attention so that the problems can be looked and rectified. (Also, a minor point of note -- I don't know if Synopsis' tools work with Libero. I know that Synplicity's Synplify ships with all versions of Libero, and some versions are also compatible with Magma's Palace software.) cheers, K.Article: 126106
A large asynchronous FIFO will always most efficiently be implemented in a dual-ported BlockRAM, and have a width of 1, 2, 4, 9, 18, or 36 bits. If you need a different width, just pad it to the higher value. Also Din and Dout have the same width. Anything different will get very complicated... The main problem in the design of asynchronous (2-clock) FIFOs is the reliable generation of the Full and Empty flags at high clock rates. Peter Alfke, Xilinx On Nov 14, 11:37 am, "zlotawy" <paraliczb@NO_SPAM_orange.pl> wrote: > Hello, > I have generated a block-ram based FIFO queue (2 independent clocks, 2 > inputs, 1 output) with the use of Core Generator. In the creator I used the > 36 bit data bus. Is it possible to parameterize this variable? > I think, that the Xilinx doesn't give such possibility. The generated code: > > LIBRARY ieee; > USE ieee.std_logic_1164.ALL; > -- synthesis translate_off > Library XilinxCoreLib; > -- synthesis translate_on > ENTITY fifa IS > port ( > din: IN std_logic_VECTOR(35 downto 0); > rd_clk: IN std_logic; > rd_en: IN std_logic; > rst: IN std_logic; > wr_clk: IN std_logic; > wr_en: IN std_logic; > dout: OUT std_logic_VECTOR(35 downto 0); > empty: OUT std_logic; > full: OUT std_logic); > END fifa; > > ARCHITECTURE fifa_a OF fifa IS > -- synthesis translate_off > component wrapped_fifa > port ( > din: IN std_logic_VECTOR(35 downto 0); > rd_clk: IN std_logic; > rd_en: IN std_logic; > rst: IN std_logic; > wr_clk: IN std_logic; > wr_en: IN std_logic; > dout: OUT std_logic_VECTOR(35 downto 0); > empty: OUT std_logic; > full: OUT std_logic); > end component; > > -- Configuration specification > for all : wrapped_fifa use entity > XilinxCoreLib.fifo_generator_v4_1(behavioral) > generic map( > c_has_int_clk => 0, > c_rd_freq => 1, > c_wr_response_latency => 1, > c_has_srst => 0, > c_has_rd_data_count => 0, > c_din_width => 36, > c_has_wr_data_count => 0, > c_full_flags_rst_val => 1, > c_implementation_type => 2, > c_family => "virtex2p", > c_use_embedded_reg => 0, > c_has_wr_rst => 0, > c_wr_freq => 1, > c_underflow_low => 0, > c_has_meminit_file => 0, > c_has_overflow => 0, > c_preload_latency => 1, > c_dout_width => 36, > c_rd_depth => 1024, > c_default_value => "BlankString", > c_mif_file_name => "BlankString", > c_has_underflow => 0, > c_has_rd_rst => 0, > c_has_almost_full => 0, > c_has_rst => 1, > c_data_count_width => 10, > c_has_wr_ack => 0, > c_use_ecc => 0, > c_wr_ack_low => 0, > c_common_clock => 0, > c_rd_pntr_width => 10, > c_use_fwft_data_count => 0, > c_has_almost_empty => 0, > c_rd_data_count_width => 10, > c_enable_rlocs => 0, > c_wr_pntr_width => 10, > c_overflow_low => 0, > c_prog_empty_type => 0, > c_optimization_mode => 0, > c_wr_data_count_width => 10, > c_preload_regs => 0, > c_dout_rst_val => "0", > c_has_data_count => 0, > c_prog_full_thresh_negate_val => 1020, > c_wr_depth => 1024, > c_prog_empty_thresh_negate_val => 3, > c_prog_empty_thresh_assert_val => 2, > c_has_valid => 0, > c_init_wr_pntr_val => 0, > c_prog_full_thresh_assert_val => 1021, > c_use_fifo16_flags => 0, > c_has_backup => 0, > c_valid_low => 0, > c_prim_fifo_type => "1kx36", > c_count_type => 0, > c_prog_full_type => 0, > c_memory_type => 1); > -- synthesis translate_on > BEGIN > -- synthesis translate_off > U0 : wrapped_fifa > port map ( > din => din, > rd_clk => rd_clk, > rd_en => rd_en, > rst => rst, > wr_clk => wr_clk, > wr_en => wr_en, > dout => dout, > empty => empty, > full => full); > -- synthesis translate_on > > END fifa_a; > > There are 2 parameters: c_din_width =>36 and c_dout_width => 36. I can't > use here values greater than 36. What is the use of this parameters? Can I > change this parameters values to i.e. 20? > I would like to use the queue with different sizes of the data bus. Is it a > good solution to create a maximum size data bus and use it to write there > smaller data? > Or maybe it is better to create a 1bit queue, and with the use of GENERATE > command generate N 1 bit queues to have a N-bit queue? > > Device is Virtex2Pro. > > Regards, > zlotawyArticle: 126107
Hi, I think the OP wanted to know if he could parallel a width-2 and a width-18 to make a width-20. I've never tried it, but I can't think of a reason that it wouldn't work. And I would not be surprised to find that the logic optimizer found the two identical FIFO controllers, and collapsed them. G. On Nov 14, 2:35 pm, Peter Alfke <pe...@xilinx.com> wrote: > A large asynchronous FIFO will always most efficiently be implemented > in a dual-ported BlockRAM, and have a width of 1, 2, 4, 9, 18, or 36 > bits. If you need a different width, just pad it to the higher value. > Also Din and Dout have the same width. > Anything different will get very complicated... > The main problem in the design of asynchronous (2-clock) FIFOs is the > reliable generation of the Full and Empty flags at high clock rates. > Peter Alfke, Xilinx > > On Nov 14, 11:37 am, "zlotawy" <paraliczb@NO_SPAM_orange.pl> wrote: > > > Hello, > > I have generated a block-ram based FIFO queue (2 independent clocks, 2 > > inputs, 1 output) with the use of Core Generator. In the creator I used the > > 36 bit data bus. Is it possible to parameterize this variable? > > I think, that the Xilinx doesn't give such possibility. The generated code: > > > LIBRARY ieee; > > USE ieee.std_logic_1164.ALL; > > -- synthesis translate_off > > Library XilinxCoreLib; > > -- synthesis translate_on > > ENTITY fifa IS > > port ( > > din: IN std_logic_VECTOR(35 downto 0); > > rd_clk: IN std_logic; > > rd_en: IN std_logic; > > rst: IN std_logic; > > wr_clk: IN std_logic; > > wr_en: IN std_logic; > > dout: OUT std_logic_VECTOR(35 downto 0); > > empty: OUT std_logic; > > full: OUT std_logic); > > END fifa; > > > ARCHITECTURE fifa_a OF fifa IS > > -- synthesis translate_off > > component wrapped_fifa > > port ( > > din: IN std_logic_VECTOR(35 downto 0); > > rd_clk: IN std_logic; > > rd_en: IN std_logic; > > rst: IN std_logic; > > wr_clk: IN std_logic; > > wr_en: IN std_logic; > > dout: OUT std_logic_VECTOR(35 downto 0); > > empty: OUT std_logic; > > full: OUT std_logic); > > end component; > > > -- Configuration specification > > for all : wrapped_fifa use entity > > XilinxCoreLib.fifo_generator_v4_1(behavioral) > > generic map( > > c_has_int_clk => 0, > > c_rd_freq => 1, > > c_wr_response_latency => 1, > > c_has_srst => 0, > > c_has_rd_data_count => 0, > > c_din_width => 36, > > c_has_wr_data_count => 0, > > c_full_flags_rst_val => 1, > > c_implementation_type => 2, > > c_family => "virtex2p", > > c_use_embedded_reg => 0, > > c_has_wr_rst => 0, > > c_wr_freq => 1, > > c_underflow_low => 0, > > c_has_meminit_file => 0, > > c_has_overflow => 0, > > c_preload_latency => 1, > > c_dout_width => 36, > > c_rd_depth => 1024, > > c_default_value => "BlankString", > > c_mif_file_name => "BlankString", > > c_has_underflow => 0, > > c_has_rd_rst => 0, > > c_has_almost_full => 0, > > c_has_rst => 1, > > c_data_count_width => 10, > > c_has_wr_ack => 0, > > c_use_ecc => 0, > > c_wr_ack_low => 0, > > c_common_clock => 0, > > c_rd_pntr_width => 10, > > c_use_fwft_data_count => 0, > > c_has_almost_empty => 0, > > c_rd_data_count_width => 10, > > c_enable_rlocs => 0, > > c_wr_pntr_width => 10, > > c_overflow_low => 0, > > c_prog_empty_type => 0, > > c_optimization_mode => 0, > > c_wr_data_count_width => 10, > > c_preload_regs => 0, > > c_dout_rst_val => "0", > > c_has_data_count => 0, > > c_prog_full_thresh_negate_val => 1020, > > c_wr_depth => 1024, > > c_prog_empty_thresh_negate_val => 3, > > c_prog_empty_thresh_assert_val => 2, > > c_has_valid => 0, > > c_init_wr_pntr_val => 0, > > c_prog_full_thresh_assert_val => 1021, > > c_use_fifo16_flags => 0, > > c_has_backup => 0, > > c_valid_low => 0, > > c_prim_fifo_type => "1kx36", > > c_count_type => 0, > > c_prog_full_type => 0, > > c_memory_type => 1); > > -- synthesis translate_on > > BEGIN > > -- synthesis translate_off > > U0 : wrapped_fifa > > port map ( > > din => din, > > rd_clk => rd_clk, > > rd_en => rd_en, > > rst => rst, > > wr_clk => wr_clk, > > wr_en => wr_en, > > dout => dout, > > empty => empty, > > full => full); > > -- synthesis translate_on > > > END fifa_a; > > > There are 2 parameters: c_din_width =>36 and c_dout_width => 36. I can't > > use here values greater than 36. What is the use of this parameters? Can I > > change this parameters values to i.e. 20? > > I would like to use the queue with different sizes of the data bus. Is it a > > good solution to create a maximum size data bus and use it to write there > > smaller data? > > Or maybe it is better to create a 1bit queue, and with the use of GENERATE > > command generate N 1 bit queues to have a N-bit queue? > > > Device is Virtex2Pro. > > > Regards, > > zlotawyArticle: 126108
> What you are asking for is outside the abilities of the Virtex-II > FPGA. Since the FPGA only contains dual-ported memories (either > SelectRAM-based or BlockRAM-based), there is no possible way to map > such a HDL description to the FPGA device. Thanks for your answer Nathan, so I cant have a register file that has 4 read ports and 2 write ports with a Virtex II? Well, unfortunately I need these number of ports else my ISA is not working. Perhaps do you know any FPGA boards that support Register Files which would allow such a design as I have it? Would be very thankful for feedback! Cheers AndrewArticle: 126109
> Are you sure that you need 4 read and 2 write ports? Do you need to > assign the data read at the time - at the same clock edge? In that > case you could just assign the same data read to multiple signals. > > How big is your register file? Thanks for your answer Dan, I need a data and instruction RAM with one read/write port each but I would need a register file with 4 read ports and 2 write ports. Is such a thing feasable with Virtex II? If not, are there any FPGA Boards that would support 4 Read Ports and 2 Write Ports Register Files? The register File itself contains 16 registers, each of 32bits.And in the worst case it can happen that at the same clock cycle I have to read 4 registers and to write back 2 values. Cheers, AndrewArticle: 126110
In a BlockRAM implementation, this does not make any sense, for width 18 and width 2 have the same cost. Widt 2 is just 9 times deeper, whether you want that or not. Paralleling or cascading FIFO-BlockRAMs only makes sense when one BlockRAM is insufficient, and the designer is experienced and understand the trade-off. Remember, excessive depth or width has no impact, as long as the FIFO fits into one BlockRAM. Stitching together RAM-based and LUT-based FIFOs is something for the brave and experienced. Peter Alfke On Nov 14, 2:45 pm, ghel...@lycos.com wrote: > Hi, > > I think the OP wanted to know if he could parallel a width-2 and a > width-18 to make a width-20. > > I've never tried it, but I can't think of a reason that it wouldn't > work. And I would not be surprised to find that the logic optimizer > found the two identical FIFO controllers, and collapsed them. > > G. > > On Nov 14, 2:35 pm, Peter Alfke <pe...@xilinx.com> wrote: > > > A large asynchronous FIFO will always most efficiently be implemented > > in a dual-ported BlockRAM, and have a width of 1, 2, 4, 9, 18, or 36 > > bits. If you need a different width, just pad it to the higher value. > > Also Din and Dout have the same width. > > Anything different will get very complicated... > > The main problem in the design of asynchronous (2-clock) FIFOs is the > > reliable generation of the Full and Empty flags at high clock rates. > > Peter Alfke, Xilinx > > > On Nov 14, 11:37 am, "zlotawy" <paraliczb@NO_SPAM_orange.pl> wrote: > > > > Hello, > > > I have generated a block-ram based FIFO queue (2 independent clocks, 2 > > > inputs, 1 output) with the use of Core Generator. In the creator I used the > > > 36 bit data bus. Is it possible to parameterize this variable? > > > I think, that the Xilinx doesn't give such possibility. The generated code: > > > > LIBRARY ieee; > > > USE ieee.std_logic_1164.ALL; > > > -- synthesis translate_off > > > Library XilinxCoreLib; > > > -- synthesis translate_on > > > ENTITY fifa IS > > > port ( > > > din: IN std_logic_VECTOR(35 downto 0); > > > rd_clk: IN std_logic; > > > rd_en: IN std_logic; > > > rst: IN std_logic; > > > wr_clk: IN std_logic; > > > wr_en: IN std_logic; > > > dout: OUT std_logic_VECTOR(35 downto 0); > > > empty: OUT std_logic; > > > full: OUT std_logic); > > > END fifa; > > > > ARCHITECTURE fifa_a OF fifa IS > > > -- synthesis translate_off > > > component wrapped_fifa > > > port ( > > > din: IN std_logic_VECTOR(35 downto 0); > > > rd_clk: IN std_logic; > > > rd_en: IN std_logic; > > > rst: IN std_logic; > > > wr_clk: IN std_logic; > > > wr_en: IN std_logic; > > > dout: OUT std_logic_VECTOR(35 downto 0); > > > empty: OUT std_logic; > > > full: OUT std_logic); > > > end component; > > > > -- Configuration specification > > > for all : wrapped_fifa use entity > > > XilinxCoreLib.fifo_generator_v4_1(behavioral) > > > generic map( > > > c_has_int_clk => 0, > > > c_rd_freq => 1, > > > c_wr_response_latency => 1, > > > c_has_srst => 0, > > > c_has_rd_data_count => 0, > > > c_din_width => 36, > > > c_has_wr_data_count => 0, > > > c_full_flags_rst_val => 1, > > > c_implementation_type => 2, > > > c_family => "virtex2p", > > > c_use_embedded_reg => 0, > > > c_has_wr_rst => 0, > > > c_wr_freq => 1, > > > c_underflow_low => 0, > > > c_has_meminit_file => 0, > > > c_has_overflow => 0, > > > c_preload_latency => 1, > > > c_dout_width => 36, > > > c_rd_depth => 1024, > > > c_default_value => "BlankString", > > > c_mif_file_name => "BlankString", > > > c_has_underflow => 0, > > > c_has_rd_rst => 0, > > > c_has_almost_full => 0, > > > c_has_rst => 1, > > > c_data_count_width => 10, > > > c_has_wr_ack => 0, > > > c_use_ecc => 0, > > > c_wr_ack_low => 0, > > > c_common_clock => 0, > > > c_rd_pntr_width => 10, > > > c_use_fwft_data_count => 0, > > > c_has_almost_empty => 0, > > > c_rd_data_count_width => 10, > > > c_enable_rlocs => 0, > > > c_wr_pntr_width => 10, > > > c_overflow_low => 0, > > > c_prog_empty_type => 0, > > > c_optimization_mode => 0, > > > c_wr_data_count_width => 10, > > > c_preload_regs => 0, > > > c_dout_rst_val => "0", > > > c_has_data_count => 0, > > > c_prog_full_thresh_negate_val => 1020, > > > c_wr_depth => 1024, > > > c_prog_empty_thresh_negate_val => 3, > > > c_prog_empty_thresh_assert_val => 2, > > > c_has_valid => 0, > > > c_init_wr_pntr_val => 0, > > > c_prog_full_thresh_assert_val => 1021, > > > c_use_fifo16_flags => 0, > > > c_has_backup => 0, > > > c_valid_low => 0, > > > c_prim_fifo_type => "1kx36", > > > c_count_type => 0, > > > c_prog_full_type => 0, > > > c_memory_type => 1); > > > -- synthesis translate_on > > > BEGIN > > > -- synthesis translate_off > > > U0 : wrapped_fifa > > > port map ( > > > din => din, > > > rd_clk => rd_clk, > > > rd_en => rd_en, > > > rst => rst, > > > wr_clk => wr_clk, > > > wr_en => wr_en, > > > dout => dout, > > > empty => empty, > > > full => full); > > > -- synthesis translate_on > > > > END fifa_a; > > > > There are 2 parameters: c_din_width =>36 and c_dout_width => 36. I can't > > > use here values greater than 36. What is the use of this parameters? Can I > > > change this parameters values to i.e. 20? > > > I would like to use the queue with different sizes of the data bus. Is it a > > > good solution to create a maximum size data bus and use it to write there > > > smaller data? > > > Or maybe it is better to create a 1bit queue, and with the use of GENERATE > > > command generate N 1 bit queues to have a N-bit queue? > > > > Device is Virtex2Pro. > > > > Regards, > > > zlotawyArticle: 126111
> Is it possible to implement power management unit(idle and active) in > FPGA? Just as a follow-up on what some others have mentioned in this thread .... Actel's Igloo FPGAs come with a pin which allow the FPGA to (effectively) power-down for idle periods. (Actel refers to this as "Flash*Freeze".) Similarly, and as mentioned elsewhere in this thread, these devices contain glitchless muxes (the NGMUX macro) which allows you to switch between high-and-low-speed clocks for power management. K.Article: 126112
On Nov 2, 2:37 am, "MMJ" <S...@aldrig.com> wrote: > > why don't you have a look at actel's Igloo family? > >http://www.actel.com/products/IGLOO/ > > Recently they added support for the ARM cortex core, with plently of > > other interesting capabilities. > > Very interesting.....thanks! Given your requirements, you may find that Actel's Fusion products are more in-line with what you need. (They're generally larger devices than Igloo, so they usually have a bit more RAM on-chip and more I/ Os. Fusion also comes with some other goodies that you may use, like a built-in oscillator, ADC/DAC, etc.) K.Article: 126113
On Nov 14, 11:15 am, Andrew Ganger <Andre...@yahoo.co.uk> wrote: > Hello, > > I am in some way a newbie in getting things to run on an FGPA, so I > would be helpful if someone could help me a little bit out how to get > started. > > I have implemented a simple processor architecture in VHDL and I > successfully simulated it with Modelsim. Now my next goal would be > to get this processor running on a Xilinx Virtex-II PMC FPGA board. > > For synthesis I am going to use Xilinx ISE 7.1i. So to see if the > processor on the FPGA is doing what it should do I could use Chipscope > and the Jtag interface. However, I am a little bit lost with the > following tasks. > > 1) I had some kind for simple RAM for simulation. How can I implement > this RAM correctly so that it be sythesizable and will correctly run on > the FPGA? > > 2) When I start the processor, I should have my instructions loaded into > the Instruction RAM? How can I do this, really no clue :( > > I am sorry for these basis questions, but I would be thankful if someone > could give me a hint where and how to start! > > Many thanks!! > Andi Are you sure that you need 4 read and 2 write ports? Do you need to assign the data read at the time - at the same clock edge? In that case you could just assign the same data read to multiple signals. How big is your register file? You may create an vhdl component that includes an array of registers (check how to create arrays of signals it is pretty straightforward). With a process inside this component you can assign values to this array where the index of the array represents the location of the register in the register file (address input of the component). You can create another process for reading that can use same or different clock (of different phase) for reading of this array using the input address as an index again. Within this component you can also manually specified the initial values of those registers. This way you can also create an instruction memory that contains some array of instructions - these instructions you would also need to specify manually within the vhdl code. Chipscope with Jtag interface you can use to probe any signals within the FPGA when it is configured. This way you can also read the register file or memory that you created in VHDL. Hope that this helps, DanArticle: 126114
>The problem is that you seem to want to use the graphical layout to >represent the wrong aspect of the design. >...HDL level is far superior for managing the the kinds of complexity >involved in accomplishing real functionality I don't want to use graphical layout at all. As I suggested, the tools aren't yet good enough, so I feel much more comfortable with text. But we would be wrong to suggest that text communication is "far superior" a priori. That makes as much sense as saying that GOTO is bad "a priori". In both cases, it's just good practical advice in certain circumstances. Some engineers (perhaps including the original poster) will always feel more comfortable with a graphical representation. It makes it possible, after all, to take in at a glance a great deal more of the "complexity" which you mention. I don't see that text (as we know it) will ever achieve that. Apart from syntax colouring and screens bigger than 80x25, we're just where we were 30 years ago. If you listen to Swahili for a week, you might conclude that it's not a practical means of communication. That doesn't mean that others won't find it perfectly usable (and preferable to your method, which they might find intolerably complex). This isn't because either side is right. It's because it's impossible properly to evaluate alternative systems until you've used both a great deal and, even then, your preference depends on you. The comfort you feel with what's familiar and the discomfort with what isn't are not a good basis for comparison.Article: 126115
I know of no tools or FPGAs that currently support inference or instantiation of 4-ported memory. Sorry. On Nov 14, 2:49 pm, Andrew Ganger <Andrew.Gan...@yahoo.co.uk> wrote: > > What you are asking for is outside the abilities of the Virtex-II > > FPGA. Since the FPGA only contains dual-ported memories (either > > SelectRAM-based or BlockRAM-based), there is no possible way to map > > such a HDL description to the FPGA device. > > Thanks for your answer Nathan, so I cant have a register file that has 4 > read ports and 2 write ports with a Virtex II? Well, unfortunately I > need these number of ports else my ISA is not working. Perhaps do you > know any FPGA boards that support Register Files which would allow such > a design as I have it? Would be very thankful for feedback! > > Cheers > AndrewArticle: 126116
However, to be slightly more helpful, you still can "fake it." Xilinx suggests such a mechanism here: http://www.xilinx.com/support/documentation/application_notes/xapp228.pdf Again, it comes down to creatively multiplexing ports. - Nathan On Nov 14, 2:49 pm, Andrew Ganger <Andrew.Gan...@yahoo.co.uk> wrote: > > What you are asking for is outside the abilities of the Virtex-II > > FPGA. Since the FPGA only contains dual-ported memories (either > > SelectRAM-based or BlockRAM-based), there is no possible way to map > > such a HDL description to the FPGA device. > > Thanks for your answer Nathan, so I cant have a register file that has 4 > read ports and 2 write ports with a Virtex II? Well, unfortunately I > need these number of ports else my ISA is not working. Perhaps do you > know any FPGA boards that support Register Files which would allow such > a design as I have it? Would be very thankful for feedback! > > Cheers > AndrewArticle: 126117
This error is because you dont have Xilinx UNISIM and XILINXCORELIB libraries mapped in Modelsim. -- Generate the libraries in EDK -- Add your libraries to your Modelsim.ini file -- Then when you are using "vcom" (equivalent of "Start Simulation" button in Modelsim) , add "-L XILINXCORELIB_VER -L UNISIM" to your command line flow. This will link your Xilinx components against these libraries. Then you should be able to simulate.. Hope this helps.. -- parag On Nov 13, 12:58 pm, Pasacco <pasa...@gmail.com> wrote: > Dear > > I would like to ask some help, for simulating EDK project. > > I did following steps: > > -------------------------------------------------------------------------------- > 1. Generate "simulation model and compiler script" using EDK 8.2 tool. > > 2. Compile design. > " do system.do" > > Following error ocurred: > > ----------------------- > # ** Error: C:/Work/TEST/SimpleEDK8.2/pcores/mem_main/hdl/vhdl/ > clock_dcm.vhd(19): Library virtex2 not found. > # ** Error: C:/Work/TEST/SimpleEDK8.2/pcores/mem_main/hdl/vhdl/ > clock_dcm.vhd(20): (vcom-1136) Unknown identifier "virtex2". > ----------------------- > > In the "clock_dcm.vhd", I commented following library definition: > ----------------------- > -- synopsys translate_off > -- library virtex2; > -- use virtex2.all; > -- synopsys translate_on > ----------------------- > > Now "system.do" is compiled. > > 3. Load design > > "vsim system" > > Following warning occurred: > > ----------------------- > Warning: Component instance "ramx32 : ramb16_s36_s36" is not bound. > ----------------------- > > This means that BRAM block is present. > I ignored this warning and proceeded to next step: > > 4. Run simulation > > Finally, following error occurred: > > ----------------------- > # ** Fatal: (vsim-3421) Value 127 is out of range 0 to 5. > # Time: 0 ns Iteration: 12 Process: /testbench/uut/buffer/out_mux > File: C:/Work/TEST/SimpleEDK8.2/pcores/Buffer_Wrapper_v1_00_a/hdl/vhdl/ > buffer.vhd > # Fatal error in Process out_mux at > ----------------------- > > This looks like a logical error in VHDL. > But this VHDL file is provided by the board vendor. > I think I made mistake in the simulation process. > > -------------------------------------------------------------------------------- > > My question is that > > If I need to use following library "virtex2", how can I generate this > library "virtex2"? > > ----------------------- > -- synopsys translate_off > library virtex2; > use virtex2.all; > -- synopsys translate_on > ----------------------- > > Thank you again.Article: 126118
On Nov 14, 2:49 pm, Andrew Ganger <Andrew.Gan...@yahoo.co.uk> wrote: Virtex-2 or any other Virtex FPGA can implement a RAM with any desired number of ports, if you are willing to time-share operation and multiplex addresses and data. So it is just a trade-off. The BlockRAMs in all Virtex devices have two independent ports, so you can perform two independent accesses simultaneously (two writes, two reads, or a mixture of write and read). Further ports can be created by time-sharing and multiplexing, which of course costs chip area and increases access time. But those are the usual trade-offs that smart engineers are asked to evaluate and implement every day. What else is new? Peter Alfke, Xilinx > > What you are asking for is outside the abilities of the Virtex-II > > FPGA. Since the FPGA only contains dual-ported memories (either > > SelectRAM-based or BlockRAM-based), there is no possible way to map > > such a HDL description to the FPGA device. > > Thanks for your answer Nathan, so I cant have a register file that has 4 > read ports and 2 write ports with a Virtex II? Well, unfortunately I > need these number of ports else my ISA is not working. Perhaps do you > know any FPGA boards that support Register Files which would allow such > a design as I have it? Would be very thankful for feedback! > > Cheers > AndrewArticle: 126119
> My question should be: do you have instructions that use 4 register > operands? Yes, I have defined an own ISA. There are instructions that take up to 4 src operands and can write up to two results back to the register file. So I need these 4 read ports for some, not all, instructions!Article: 126120
> What CPU are you using ? Well, in some way I have defined my own ISA. The instructions can take up to 4 src registers and can produce 2 results. Else it is a classical 5 stage pipeline with 16 registers in the register file.Article: 126121
Andrew Ganger wrote: > Andrew Ganger wrote: > >> UNfortuantely I just have version 7.1 and I should have a RAM that has >> 4 read ports and 2 write ports? Is that somehow to realise with ISE >> 7.1 or do I need to upgrade to version 8.1? > > > Mixed something up, my Register File should have 4 read ports and two > write ports :) Two write ports sounds dangerous :) - but classic RISC devices might need 3 read ports, and one write port Rd = Ra OPERAND Rb OPERAND Rc one fast/simple idea I had for emulating this on dualport memory is to use two blocks and simply parallel the one write port - so the two have identical info, and would actually give 4 read ports Yes, it's a little redundant, but easy to implement, and the RegFiles are small anyway. -jgArticle: 126122
On Nov 14, 5:55 pm, Andrew Ganger <Andrew.Gan...@yahoo.co.uk> wrote: > > Are you sure that you need 4 read and 2 write ports? Do you need to > > assign the data read at the time - at the same clock edge? In that > > case you could just assign the same data read to multiple signals. > > > How big is your register file? > > Thanks for your answer Dan, I need a data and instruction RAM with one > read/write port each but I would need a register file with 4 read ports > and 2 write ports. Is such a thing feasable with Virtex II? If not, are > there any FPGA Boards that would support 4 Read Ports and 2 Write Ports > Register Files? The register File itself contains 16 registers, each of > 32bits.And in the worst case it can happen that at the same clock cycle > I have to read 4 registers and to write back 2 values. > > Cheers, > Andrew Are you implementing MIPS32? Do you have instructions that have two register operands?Article: 126123
On Nov 14, 9:12 pm, EEngineer <mari...@gmail.com> wrote: > On Nov 14, 5:55 pm, Andrew Ganger <Andrew.Gan...@yahoo.co.uk> wrote: > > > > > > Are you sure that you need 4 read and 2 write ports? Do you need to > > > assign the data read at the time - at the same clock edge? In that > > > case you could just assign the same data read to multiple signals. > > > > How big is your register file? > > > Thanks for your answer Dan, I need a data and instruction RAM with one > > read/write port each but I would need a register file with 4 read ports > > and 2 write ports. Is such a thing feasable with Virtex II? If not, are > > there any FPGA Boards that would support 4 Read Ports and 2 Write Ports > > Register Files? The register File itself contains 16 registers, each of > > 32bits.And in the worst case it can happen that at the same clock cycle > > I have to read 4 registers and to write back 2 values. > > > Cheers, > > Andrew > > Are you implementing MIPS32? Do you have instructions that have two > register operands? My question should be: do you have instructions that use 4 register operands?Article: 126124
On Nov 12, 8:57 am, Ray Andraka <r...@andraka.com> wrote: > Amit wrote: > > Hello group, > > > I'm new to this field and currently learning how 16v8 architecture is > > designed. Of course, pretty confused but as my first experiement I > > need to implement a logical function and also design multiplier using > > 61v8. > > > does anybody know where I can get some information to be able to > > complete this? > > > Regards, > > amit > > With only 8 registers and product terms, you'd have to make it a bit > serial multiplier, and even then the parallel multiplicand is going to > limited in size. See the multipliers page on my website for details. Hi Ray, Thank your response. what is your webiste's domain? Thanks, ak
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