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On 7 Dec, 02:35, John Williams <jwilli...@itee.uq.edu.au> wrote: > Hi, > > ratemonotonic wrote: > > Is it possible to use FSL read on an interrupt basis rather than > > polling? > > Sure, you can connect the FSL_is_data signal to an interrupt port in the > MHS file. > > > I have a scenario where i only want to read data using get instruction > > if there is data on the bus. > > You need to design your interrupt handler carefully - to disable the FSL > interrupt immediately and only re-enable it when it has drained the channel. > > > Are there any example projects ? > > Not that I am aware of. > > Regards, > > John Thanks john , >You need to design your interrupt handler carefully - to disable the FSL > interrupt immediately and only re-enable it when it has drained the channel. Else interrupt gets hit circularly. I think this should suit my reqs perfectly. BR RateArticle: 126976
On Dec 6, 9:00 am, wei.wang.can...@googlemail.com wrote:
> Hi,
>
> Is it possible to define clocks in the .sdc file of a design, while
> those clocks only appear in a peripheral or a core, i.e., clocks not
> in the top level of the design.
>
> Thanks,
> -J
Yes. This is how I have defined an internal clock:
define_clock -name {n:otherclock} -freq 100.0000 -clockgroup
otherclock_clkgroup
Article: 126977On Dec 7, 3:54 am, KJ <Kevin.Jenni...@unisys.com> wrote: > > Anywhere I can find some same for the "FSM" master in Avalon bus?- Hide quoted text - > > > - Show quoted text - > > You're going to have a hard time if you're not willing to pick up and > read and attempt to understand the Avalon bus. If you have read it > and are still asking about how to find a "FSM" master then it's > apparent that you do not understand it so I would suggest some further > study on your part. Spot on! TommyArticle: 126978
I'm relatively new to FPGA. I've learnt vhdl and done few designs in xilinx Spartan II fpga, xsa v1.2 board. I've been involved in robotics and have designed some robotic system (basically line tracking, odometry, PID etc) but those were microcontroller based. Now I'm trying to work and do some research in FPGA based robotics system especially in vision systems and control system. Want to make a working robot with motion control, vision systems to what ever level I can within a year. (well that's the time I've to complete at least one robot with some basic systems.), I've few questions, and hope I'll get the answers!!!!! i) The design loaded in FPGA is lost when the power goes out. So how can we preserve the hardware designed so that it need not be loaded again and again from PC. ii) The robots we're going to make must be autonomous, and we can't use PC. So what would be the best FPGA board (preferebly from Xilinx), well I'm thinking of one supporting the microblaze.Article: 126979
On Dec 7, 10:15 am, Andy <jonesa...@comcast.net> wrote: > On Dec 7, 8:14 am, Anuja <thakkar.an...@gmail.com> wrote: > > > > > > > On Dec 7, 4:02 am, "RCIngham" <robert.ing...@gmail.com> wrote: > > > > >On Dec 6, 9:43 am, "RCIngham" <robert.ing...@gmail.com> wrote: > > > >> >On Dec 4, 5:56 pm, Eric Smith <e...@brouhaha.com> wrote: > > > >> >> Anuja wrote: > > > >> >> > assign Q = (rst==0)?Q_int:1'do; > > > > >> >> > How do i convert this to vhdl? I have to use a concurrent > > > statement > > > >> as > > > > >> >> Q <= Q_int when rst = '0' else '0'; > > > > >> >Hi, > > > > >> >I am having simulation problems with my code. I am trying to convert > > > >> >Verilog code to VHDL. I can compile correctly. When i simulate the > > > >> >following code in VHDL, value of Q_int is stuck at "00". It does not > > > >> >change at all. Please let me know what the problem could be. > > > > >> Remove the line: > > > > >> Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else "00"; > > > > >> after the BEGIN of the architecture.- Hide quoted text - > > > > >> - Show quoted text - > > > > >How do i implement the logic assign Q = (rst == 0)? Q_int : 2'd0; > > > > >if i remove Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else > > > >"00"; > > > > Sorry, my bad. I read your code too quickly, and thought you were > > > assigning to Q in the clocked precess as well. > > > > Try: > > > Q(1 downto 0) <= Q_int(1 downto 0) when rst = '0' else "00"; > > > Or better: > > > Q(1 downto 0) <= "00" when rst = '1' else Q_int(1 downto 0);- Hide quoted text - > > > > - Show quoted text - > > > neither one works. I am still having the same problem > > I'm not sure where you got the code, but it looks like it is a flop > with a synchronous reset and enable, and then anding the output with > reset after the register. > > I would convert it as follows to a standard asynchronous reset > circuit. The only difference in behavior would be if rst is high for > less than a clock cycle, but not while the clock is actually rising > (in which case the original circuit output would be 0 while rst, but > return to whatever q_int was afterwards, whereas the new circuit will > stay at 0 until something is clocked into q). > > process (clk, rst) is > begin > if rst = '1' then > q <= (others => '0'); > elsif rising_edge(clk) and (en = '1') then > q <= d; > end if; > end process; > > Hints: you don't need to write "(1 downto 0)" when that is the entire > range of the array/vector. In a clocked process, you also don't need > to reassign q (or q_int) to itself when it needs to remain the same. > > and get rid of that concurrent statement (it is handled now by the > async reset) > > Andy- Hide quoted text - > > - Show quoted text - I cannot change the reset to ssynchronous. My employer wants it to be synchronous. The wait statement did not help. I have clk_temp <= not clk_temp after 5 ns; So, the clock is definately moving forward. _Article: 126980
On Dec 7, 6:23 am, Andre van der Avoird <an...@becanus.nl> wrote: > Thanks John, Can I upgrade with an online update from 9.1 or do I need a > complete new install ? > Problem is my webupdate doesn't work. > > Andre > > > > John_H wrote: > > Andre van der Avoird wrote: > >> Hi All, > > >> I have a XupV2P board, ISE 9.1 and Windows Vista. > >> I can't find the right driver for my USB cable to download my bitstream. > >> Does anyone know where to find it ? > > >> Thanks, Andre. > > > ...in the Xilinx ISE installation program. I noticed it in the 9.2i > > setup.exe on XP when the items are checked by the user for installation > > of the components. In addition to the various CPLD and FGPA families, > > there are check-boxes for "standalone programmer" and "cable driver." > > That last item is critical. Maybe it's time to upgrade to 9.2i since > > you need to reinstall this item anyway. > > > - John_H- Hide quoted text - > > - Show quoted text - If you do a fresh install of 9.2i, it'll be everything. If you do a reinstall of 9.1i, you can probably just install the cable drivers through I haven't gone through that exercise myself. The tools are already up to service pack 3 on 9.2i.Article: 126981
axalay wrote:
> In UCF I write:
> NET "RefClkp" LOC = "AB4" | IOSTANDARD = "LVDS_25" ;
> NET "RefClkn" LOC = "AB3" | IOSTANDARD = "LVDS_25" ;
>
> In project:
> IBUFDS ref_clk_buffer (Test, RefClkp, RefClkn);
>
> But ISE swear in mapping:
>
> ERROR:Pack:1107 - Unable to combine the following symbols into a
> single IOB
> component:
> PAD symbol "2RefClkn" (Pad Signal = RefClkn)
> SlaveBuffer symbol "ref_clk_buffer/SLAVEBUF.DIFFIN" (Output Signal
> =
> ref_clk_buffer/SLAVEBUF.DIFFIN)
> Each of the following constraints specifies an illegal physical
> site for a
> component of type IOB:
> Symbol "RefClkn" (LOC=AB3 [Physical Site Type = IPAD])
> The component type is determined by the types of logic and the
> properties and
> configuration of the logic it contains. Please double check that
> the types of
> logic elements and all of their relevant properties and
> configuration options
> are compatible with the physical site type of the constraint.
> Please correct the constraints accordingly.
> ERROR:Pack:1107 - Unable to combine the following symbols into a
> single IOB
> component:
> PAD symbol "RefClkp" (Pad Signal = RefClkp)
> DIFFAMP symbol "ref_clk_buffer/IBUFDS" (Output Signal = Test_OBUF)
> Each of the following constraints specifies an illegal physical
> site for a
> component of type IOB:
> Symbol "RefClkp" (LOC=AB4 [Physical Site Type = IPAD])
> The component type is determined by the types of logic and the
> properties and
> configuration of the logic it contains. Please double check that
> the types of
> logic elements and all of their relevant properties and
> configuration options
> are compatible with the physical site type of the constraint.
> Please correct the constraints accordingly.
>
> In UG196 (v1.3) May 25, 2007 I see in page 51 that:
> This section shows key elements of a UCF that instantiates seven
> GTP_DUAL tiles. The file
> implements the example configuration shown in Figure 5-5, page 71. The
> device and
> package combination chosen in this example is an XC5VLX110T-FF1136.
> ;
> ; Instantiate the GTP_DUAL tiles in locations X0Y7 to X0Y1
> ;
> INST design_root/gtp_dual[1]/gtp_dual LOC=GTP_DUAL_X0Y1;
> INST design_root/gtp_dual[2]/gtp_dual LOC=GTP_DUAL_X0Y2;
> INST design_root/gtp_dual[3]/gtp_dual LOC=GTP_DUAL_X0Y3;
> INST design_root/gtp_dual[4]/gtp_dual LOC=GTP_DUAL_X0Y4;
> INST design_root/gtp_dual[5]/gtp_dual LOC=GTP_DUAL_X0Y5;
> INST design_root/gtp_dual[6]/gtp_dual LOC=GTP_DUAL_X0Y6;
> INST design_root/gtp_dual[7]/gtp_dual LOC=GTP_DUAL_X0Y7;
> ;
> ; Connect the REFCLK_PAD_(N/P) differential pair to the middle
> ; GTP_DUAL tile (GTP_DUAL_X0Y4)
> ;
> NET refclk_pad_n LOC=P4;
> NET refclk_pad_p LOC=P3;
> The instantiation of the GTP_DUAL tiles and the IBUFDS primitive is
> typically done in
> HDL code within the design hierarchy. That code also connects the
> output of the IBUFDS
> primitive to the CLKIN inputs of the GTP_DUAL tiles, as illustrated by
> the following
> Verilog code fragment:
> //
> // Instantiate the GTP_DUAL tiles
> //
> genvar tile_num;
> generate for (tile_num = 1; tile_num <= 7; ++tile_num)
> begin: gtp_dual
> GTP_DUAL gtp_dual
> (
> .CLKIN(refclk),
> ... The remaining GTP_DUAL ports are not shown
> )
> end
> endgenerate
> //
> // Instantiate the IBUFDS for the reference clock
> //
> IBUFDS ref_clk_buffer
> (
> .IN(refclk_pad_n),
> .IP(refclk_pad_p),
> .O(refclk)
> )
>
> Question:
> If I dont put in project GTP_DUAL I may use MGTREFCLK pins. I want
> first see that clock after IBUFDS correctly and after that include
> GTP_DUAL in my project.
A couple of comments on this:
1) You have given an incomplete description of your problem as you
did not specify which part/package was being used. After looking
through all of the package files the only possible on with AB3/AB4
is a FF665. If you are using another package that these locations
are not valid.
2) The MGTREFCLK inputs do not have alternative standards so you should
not attach a IOSTANDARD=LVDS_25 in the UCF constraint.
3) IMHO, you should always use .PORT mappings when instantiating a module
in Verilog to ensure that the you do get the right NET to PORT connection.
4) The only allowed connection from the MGT REFCLK pins is to a GTP_DUAL
CLKIN pin. You can not be routed this to any other source. You can use
the REFCLKOUT pin from the GTP_DUAL to pass the signal through to the
fabric resources.
Ed McGettigan
--
Xilinx Inc
Article: 126982On Dec 6, 11:40 pm, Alex Freed <al...@mirrow.com> wrote: > Did anyone get the DDR SDRAM work on the Xilinx Spartan 3E Starter board? > > I have tried to load the pre-built BIT file specifically for this board: > s3e_starter_revD_mig_ddr. The readme file states that the LED1 should be > slightly lit while LED0 should be OFF. In my case the LED1 is fine, but > the LED0 is constantly ON. I tried to load the ChipScope - enabled > version of the bitstream and get the same result. Also the lfsr_data has > nothing in common with read_data_reg in ChipScope. > > I tried running on 100, 50 and even 32 MHz (should be 80-133). Same effect. > > And help highly appreciated. > > -Alex. Hello, I extracted the VHDL sources from the example and prepared a project for ISE 9.2 webpack. It works on my S3E rev.D with on-board 50MHz oscillator. The original bitfiles do not work here too (LEDs are off) but I don't know why :-( You can download the ISE project with sources and bitfiles here: http://uloz.to/106699/ddr-s3e.tar.gz -- JaraArticle: 126983
The modern Xilinx FPGAs can be loaded from a serial flash memory and the unused portion of that memory can be used for code storage for a processor like MicroBlaze. It is a good compact way to achieve a microprocessor circuit. We do this on a number of our products and a range of users, including some doing robotics, who are using ours boards in exactly this way. We are actively looking at doing a derivative of our Craignell/ Drigmorn1 boards with some capabilities to control motors etc. and some basic ADC capability for robotic type applications. These boards are very small and can fit into small spaces if that is one of your limitations have a look at what we are doing. Details on these boards here: http://www.enterpoint.co.uk/component_replacements/drigmorn1.html http://www.enterpoint.co.uk/component_replacements/craignell.html I'm interested to gauge interest in this type of product so that we can decide whether to bring a specialist product to market so if anyone else has interest please do contact us. John Adair Enterpoint Ltd. - Home of Craignell. The obsolete component solution. On 7 Dec, 16:48, bish <bishes...@gmail.com> wrote: > I'm relatively new to FPGA. I've learnt vhdl and done few designs in > xilinx Spartan II fpga, xsa v1.2 board. I've been involved in > robotics and have designed some robotic system (basically line > tracking, odometry, PID etc) but those were microcontroller based. > > Now I'm trying to work and do some research in FPGA based robotics > system especially in vision systems and control system. Want to make a > working robot with motion control, vision systems to what ever level I > can within a year. (well that's the time I've to complete at least one > robot with some basic systems.), I've few questions, and hope I'll get > the answers!!!!! > > i) The design loaded in FPGA is lost when the power goes out. So how > can we preserve the hardware designed so that it need not be loaded > again and again from PC. > > ii) The robots we're going to make must be autonomous, and we can't > use PC. So what would be the best FPGA board (preferebly from Xilinx), > well I'm thinking of one supporting the microblaze.Article: 126984
glen herrmannsfeldt wrote: > Ray Andraka wrote: > >> glen herrmannsfeldt wrote: > > (snip) > >>> There are many things I would like to see added to FPGAs >>> before analog delay lines. > > >> Not to mention that it is usually considered poor form to use delay >> lines in digital design. > > > Yes. I did used to see them in DRAM controllers, though. > > Also, in NTSC decoders to get the chrominance and luminance > signals right. (That isn't a digital design, though.) > > -- glen > I remember seeing them in DRAM controllers too. That doesn't make it good design though. There were fewer choices then since the DRAM generally ran off the processor clock making it difficult and expensive to get a multiplied clock (PLLs of the day were much slower than the clock rates for DRAM) needed to get clock edges placed at fractional cycle points without using delay lines to generate those clocks. The better DRAM designs used the delay line to generate a delayed clock rather than delaying memory signals.Article: 126985
Hi, I'am trying to set up an Interface for an A/D - D/A Codec on an virtex II pro plattform using the (ppc) plb bus. What i want is to connect two interrupt pins from this A/D codec to an INT-Controller. Is it possible to it this way, without using the intterupt support implemented in the ipif-interface. I don't want to do a polling onto one of the isr-flags in the ipif- interupt controller. I't would be veryy helpful if anyone colud help me out. I'm using Xilinx EDK 9.1 Cheers SvenArticle: 126986
> i) The design loaded in FPGA is lost when the power goes out. So how > can we preserve the hardware designed so that it need not be loaded > again and again from PC. A few strategies ... (1) If you want to use Xilinx devices, you could always employ your own nonvolatile device (like an EEPROM) on the PCB, and hook it up to the FPGA. There are various app notes to show you how to do this. Alternately, some SRAM-based FPGAs come with nonvolatile components (built into the FPGA) to hold the configuration during power cycling. This solution is similar to the former case, except that the nonvolatile part is basically embedded in the FPGA. It shares the same drawbacks, though -- chiefly, the FPGA has to reprogram itself when the power cycles, and this may be a downside in terms of the downtime and current consumption required to reprogram. (2) Alternatively, Actel produces flash-based FPGAs (where all of the configuration bits are flash cells) -- these devices hold their configuration when the power goes out. Since there is no need to reprogram the FPGA, this solution offers very minimal downtime during power cycling and has only minimal impact on current draw (since the FPGA doesn't have to reprogram itself). K.Article: 126987
Reinstalling the drivers of 9.1 didn't work but the full 9.2 WebPack does the trick. Once the driver was ok I went back to using 9.1 to be able to keep my EDK 9.1. Now the downloading works. Now I've only to find a way to get my IO without having a serial port on my laptop. Thanks again, Andre. John_H wrote: > On Dec 7, 6:23 am, Andre van der Avoird <an...@becanus.nl> wrote: >> Thanks John, Can I upgrade with an online update from 9.1 or do I need a >> complete new install ? >> Problem is my webupdate doesn't work. >> >> Andre >> >> >> >> John_H wrote: >>> Andre van der Avoird wrote: >>>> Hi All, >>>> I have a XupV2P board, ISE 9.1 and Windows Vista. >>>> I can't find the right driver for my USB cable to download my bitstream. >>>> Does anyone know where to find it ? >>>> Thanks, Andre. >>> ...in the Xilinx ISE installation program. I noticed it in the 9.2i >>> setup.exe on XP when the items are checked by the user for installation >>> of the components. In addition to the various CPLD and FGPA families, >>> there are check-boxes for "standalone programmer" and "cable driver." >>> That last item is critical. Maybe it's time to upgrade to 9.2i since >>> you need to reinstall this item anyway. >>> - John_H- Hide quoted text - >> - Show quoted text - > > If you do a fresh install of 9.2i, it'll be everything. If you do a > reinstall of 9.1i, you can probably just install the cable drivers > through I haven't gone through that exercise myself. The tools are > already up to service pack 3 on 9.2i.Article: 126988
Hey folks, I'm working on a PCB that will have an Altera FPGA (Cyclone II in 672 ball FBGA). There is no code to be loaded to the FPGA yet so it makes testing the pin assignment hard (impossible?). On the PCB I'm planning to have a 256Mb of DDR SDRAM (16-bit wide DQ bus). I'm concerned that some of my other signals to and from the FPGA may cause problems with the DDRA SDRAM lines. What I was hoping to do was open up Quartus II and assign my pins for given directions, drive strengths, IO standards etc. The run the assignment checking tool to see if any of the signals were brought in on pins that are not acceptable. Does anyone know how to do this kind of testing when there is no RTL code driving the pins (yet)? Thanks, SteveArticle: 126989
On Dec 7, 3:22 pm, steve_blah <srpen...@gmail.com> wrote:
> Hey folks,
>
> I'm working on a PCB that will have an Altera FPGA (Cyclone II in 672
> ball FBGA). There is no code to be loaded to the FPGA yet so it makes
> testing the pin assignment hard (impossible?). On the PCB I'm
> planning to have a 256Mb of DDR SDRAM (16-bit wide DQ bus). I'm
> concerned that some of my other signals to and from the FPGA may cause
> problems with the DDRA SDRAM lines. What I was hoping to do was open
> up Quartus II and assign my pins for given directions, drive
> strengths, IO standards etc. The run the assignment checking tool to
> see if any of the signals were brought in on pins that are not
> acceptable. Does anyone know how to do this kind of testing when
> there is no RTL code driving the pins (yet)?
>
> Thanks,
>
Create a 'dummy' design. Use all of the same signal names and signal
directions (in/out/inout) that will be on the final FPGA design. Make
up any sort of dummy logic that uses all of the inputs to drive all of
the outputs and inouts. Run it through Quartus and make sure that it
doesn't generate any warnings about inputs that are not used or
outputs that are driven to a constant. Now you have something that
you do pin placement on and from that point simply run the I/O
assignment analysis every now and then as you get pins assigned,
Quartus will complain if you have any errors.
About the only considerations you'll need to make in creating the
dummy logic has to do with clocks and PLLs. Make sure that any input
clocks that will be connected to flip flops at least clock in
'something' in your dummy logic. If you'll be using PLLs instantiate
them and configure them for the estimated design frequency that you
intend to run it at, and if those PLL outputs will be driving output
pins (like the DDR clock as an example) make sure the PLL output is
connected to the appropriate output signal. By doing this, Quartus
will generate errors or warnings when running the I/O assignment
analysis if you try to do something that you shouldn't or can't do.
Lastly, since you're using some form of DDR controller, refer to the
Altera documentation on the preferred pins to use for the controller I/
O otherwise you may have trouble getting the proper DDR performance
that you need for your project. Quartus won't generate any warnings
about this ('specially since the dummy logic won't have any DDR
controller), you'll have to manually check it.
Kevin Jennings
Article: 126990On Dec 7, 10:15 am, Andy <jonesa...@comcast.net> wrote: > On Dec 7, 8:14 am, Anuja <thakkar.an...@gmail.com> wrote: > > > > > > > On Dec 7, 4:02 am, "RCIngham" <robert.ing...@gmail.com> wrote: > > > > >On Dec 6, 9:43 am, "RCIngham" <robert.ing...@gmail.com> wrote: > > > >> >On Dec 4, 5:56 pm, Eric Smith <e...@brouhaha.com> wrote: > > > >> >> Anuja wrote: > > > >> >> > assign Q = (rst==0)?Q_int:1'do; > > > > >> >> > How do i convert this to vhdl? I have to use a concurrent > > > statement > > > >> as > > > > >> >> Q <= Q_int when rst = '0' else '0'; > > > > >> >Hi, > > > > >> >I am having simulation problems with my code. I am trying to convert > > > >> >Verilog code to VHDL. I can compile correctly. When i simulate the > > > >> >following code in VHDL, value of Q_int is stuck at "00". It does not > > > >> >change at all. Please let me know what the problem could be. > > > > >> Remove the line: > > > > >> Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else "00"; > > > > >> after the BEGIN of the architecture.- Hide quoted text - > > > > >> - Show quoted text - > > > > >How do i implement the logic assign Q = (rst == 0)? Q_int : 2'd0; > > > > >if i remove Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else > > > >"00"; > > > > Sorry, my bad. I read your code too quickly, and thought you were > > > assigning to Q in the clocked precess as well. > > > > Try: > > > Q(1 downto 0) <= Q_int(1 downto 0) when rst = '0' else "00"; > > > Or better: > > > Q(1 downto 0) <= "00" when rst = '1' else Q_int(1 downto 0);- Hide quoted text - > > > > - Show quoted text - > > > neither one works. I am still having the same problem > > I'm not sure where you got the code, but it looks like it is a flop > with a synchronous reset and enable, and then anding the output with > reset after the register. > > I would convert it as follows to a standard asynchronous reset > circuit. The only difference in behavior would be if rst is high for > less than a clock cycle, but not while the clock is actually rising > (in which case the original circuit output would be 0 while rst, but > return to whatever q_int was afterwards, whereas the new circuit will > stay at 0 until something is clocked into q). > > process (clk, rst) is > begin > if rst = '1' then > q <= (others => '0'); > elsif rising_edge(clk) and (en = '1') then > q <= d; > end if; > end process; > > Hints: you don't need to write "(1 downto 0)" when that is the entire > range of the array/vector. In a clocked process, you also don't need > to reassign q (or q_int) to itself when it needs to remain the same. > > and get rid of that concurrent statement (it is handled now by the > async reset) > > Andy- Hide quoted text - > > - Show quoted text - I tried the solution you gave me. I am still having the same problem, Q or Q_int is still "00" at all timeArticle: 126991
steve_blah wrote:
> Does anyone know how to do this kind of testing when
> there is no RTL code driving the pins (yet)?
KJ explained it well.
But note that rushing to make a circuit board
does not always save any time or money.
Having some working FPGA code before starting
a layout can eliminate one or two
board spins.
-- Mike Treseler
Article: 126992On Dec 7, 10:15 am, Andy <jonesa...@comcast.net> wrote: > On Dec 7, 8:14 am, Anuja <thakkar.an...@gmail.com> wrote: > > > > > > > On Dec 7, 4:02 am, "RCIngham" <robert.ing...@gmail.com> wrote: > > > > >On Dec 6, 9:43 am, "RCIngham" <robert.ing...@gmail.com> wrote: > > > >> >On Dec 4, 5:56 pm, Eric Smith <e...@brouhaha.com> wrote: > > > >> >> Anuja wrote: > > > >> >> > assign Q = (rst==0)?Q_int:1'do; > > > > >> >> > How do i convert this to vhdl? I have to use a concurrent > > > statement > > > >> as > > > > >> >> Q <= Q_int when rst = '0' else '0'; > > > > >> >Hi, > > > > >> >I am having simulation problems with my code. I am trying to convert > > > >> >Verilog code to VHDL. I can compile correctly. When i simulate the > > > >> >following code in VHDL, value of Q_int is stuck at "00". It does not > > > >> >change at all. Please let me know what the problem could be. > > > > >> Remove the line: > > > > >> Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else "00"; > > > > >> after the BEGIN of the architecture.- Hide quoted text - > > > > >> - Show quoted text - > > > > >How do i implement the logic assign Q = (rst == 0)? Q_int : 2'd0; > > > > >if i remove Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else > > > >"00"; > > > > Sorry, my bad. I read your code too quickly, and thought you were > > > assigning to Q in the clocked precess as well. > > > > Try: > > > Q(1 downto 0) <= Q_int(1 downto 0) when rst = '0' else "00"; > > > Or better: > > > Q(1 downto 0) <= "00" when rst = '1' else Q_int(1 downto 0);- Hide quoted text - > > > > - Show quoted text - > > > neither one works. I am still having the same problem > > I'm not sure where you got the code, but it looks like it is a flop > with a synchronous reset and enable, and then anding the output with > reset after the register. > > I would convert it as follows to a standard asynchronous reset > circuit. The only difference in behavior would be if rst is high for > less than a clock cycle, but not while the clock is actually rising > (in which case the original circuit output would be 0 while rst, but > return to whatever q_int was afterwards, whereas the new circuit will > stay at 0 until something is clocked into q). > > process (clk, rst) is > begin > if rst = '1' then > q <= (others => '0'); > elsif rising_edge(clk) and (en = '1') then > q <= d; > end if; > end process; > > Hints: you don't need to write "(1 downto 0)" when that is the entire > range of the array/vector. In a clocked process, you also don't need > to reassign q (or q_int) to itself when it needs to remain the same. > > and get rid of that concurrent statement (it is handled now by the > async reset) > > Andy- Hide quoted text - > > - Show quoted text - I FOUND THE SOLUTION. INSTEAD OF USING TEMPORARY SIGNAL Q_INT, I DIRECTLY UPDATED THE VALUE OF OUTPUT Q. IT IS WORKING FINE NOW. Andys tip of not reassigning signals to itself really helped. Thanks everybody.Article: 126993
Yes, I found that bypassing the generated IPIF when working with interrupts was the only way to go. Just drive the interrupt output signal in the top level code directly with your own interrupt from your own interrupt controller. ---Matthew Hicks > Hi, I'am trying to set up an Interface for an A/D - D/A Codec on an > virtex II pro plattform using the (ppc) plb bus. > What i want is to connect two interrupt pins from this A/D codec to an > INT-Controller. Is it possible to it this way, without using the > intterupt support implemented in the ipif-interface. I don't want to > do a polling onto one of the isr-flags in the ipif- interupt > controller. > I't would be veryy helpful if anyone colud help me out. I'm using > Xilinx EDK 9.1 > > Cheers > > Sven >Article: 126994
Two very simple options, use a USB to RS-232 converter or use the built-in BSCAN primitive and the user register to communicate over JTAG. If you use the latter, you can have a virtual development board on a computer and all you need in hardware is a PCB with a FPGA and a JTAG header (i.e. no buttons, no LEDs, no switches, no slow comm. interfaces). ---Matthew Hicks > Reinstalling the drivers of 9.1 didn't work but the full 9.2 WebPack > does the trick. > Once the driver was ok I went back to using 9.1 to be able to keep my > EDK 9.1. > Now the downloading works. > Now I've only to find a way to get my IO without having a serial port > on my laptop. > Thanks again, Andre. > John_H wrote: > >> On Dec 7, 6:23 am, Andre van der Avoird <an...@becanus.nl> wrote: >> >>> Thanks John, Can I upgrade with an online update from 9.1 or do I >>> need a >>> complete new install ? >>> Problem is my webupdate doesn't work. >>> Andre >>> >>> John_H wrote: >>> >>>> Andre van der Avoird wrote: >>>> >>>>> Hi All, >>>>> I have a XupV2P board, ISE 9.1 and Windows Vista. >>>>> I can't find the right driver for my USB cable to download my >>>>> bitstream. >>>>> Does anyone know where to find it ? >>>>> Thanks, Andre. >>>> ...in the Xilinx ISE installation program. I noticed it in the >>>> 9.2i >>>> setup.exe on XP when the items are checked by the user for >>>> installation >>>> of the components. In addition to the various CPLD and FGPA >>>> families, >>>> there are check-boxes for "standalone programmer" and "cable >>>> driver." >>>> That last item is critical. Maybe it's time to upgrade to 9.2i >>>> since >>>> you need to reinstall this item anyway. >>>> - John_H- Hide quoted text - >>> - Show quoted text - >>> >> If you do a fresh install of 9.2i, it'll be everything. If you do a >> reinstall of 9.1i, you can probably just install the cable drivers >> through I haven't gone through that exercise myself. The tools are >> already up to service pack 3 on 9.2i. >>Article: 126995
hi all:
Recently i'm doing the FPGA gate way. I have a smsc netcard(MAC
+PHY). My main task is the gateway can receive and transmit the data
package with the smsc chip.
Generally this task is well done using a driver on a OS (such
Linux). Now my aim is implement the same work of driver with VHDL.
Is some guy have done same work before? Or give me some advice?
thanks all.
Article: 126996On Dec 7, 12:22 pm, steve_blah <srpen...@gmail.com> wrote: > Hey folks, > > I'm working on a PCB that will have an Altera FPGA (Cyclone II in 672 > ball FBGA). There is no code to be loaded to the FPGA yet so it makes > testing the pin assignment hard (impossible?). On the PCB I'm > planning to have a 256Mb of DDR SDRAM (16-bit wide DQ bus). I'm > concerned that some of my other signals to and from the FPGA may cause > problems with the DDRA SDRAM lines. What I was hoping to do was open > up Quartus II and assign my pins for given directions, drive > strengths, IO standards etc. The run the assignment checking tool to > see if any of the signals were brought in on pins that are not > acceptable. Does anyone know how to do this kind of testing when > there is no RTL code driving the pins (yet)? > > Thanks, > > Steve Hi Steve, Please read the Early Pin Planning section in the Pin Planner section of the handbook http://www.altera.com/literature/hb/qts/qts_qii52013.pdf and the section on Validating Pin Assignments in the same section. This will answer a lot of your questions. Hope this helps, Subroto Datta Altera Corp.Article: 126997
I need to build a sort of a simple video processor to drive a TFT LCD screen in an embedded system. The plan is to use a small and cheap FPGA with some memory. Low cost is very important, so fast SRAM is not an option. I want to test the concept on an off-the-shelf board before making my own, so I got the Spartan 3E "starter kit" that comes with DDR SDRAM. Unfortunately I can't make the memory work using the core generator. Most likely I'm not doing something right, but maybe there is some problem with the hardware. While searching for info on SDRAM interfacing I got an impression that the DDR SDRAM is very difficult to use and the board layout is very critical. For my application 133 MHZ DDR is a heck of an overkill as I only need to read 16 bits of consecutive data at 50 MHz (burst) max. So regular SDRAM is probably a better choice. I'm also using Micron SDRAM elsewhere on my device (with the PXA255 CPU). Looking for a board with built in SDRAM I came across the $150 Altera DE1. Traditionally I used X more than A, but those were CPLDs rather than FPGAs. The data sheet looks promising. Only 2 power voltages. Same cost (Cyclone 2 vs. Spartan 3e). There is also PSRAM as an option and a Digilent board with S3e and PSRAM, but it is more expensive than plain SDRAM by far. My volume is about 10,000 a year. I figure about $5 for FPGA and $1.5 for SDRAM (8 MB). PSRAM is more like $5. Am I missing something? I'd like to hear opinions before making the next move. Thanks. -Alex.Article: 126998
Hi Ed, you wrote: > 2) The MGTREFCLK inputs do not have alternative standards so you should > not attach a IOSTANDARD=LVDS_25 in the UCF constraint. So the clock to the GTPs does always have to be LVDS_25, no LVPECL supported directly, like in the "regular" IOs? So I guess I need external termination resistors like described in xapp696 if I want to use a LVPECL clock source for the MGTs? cu, Sean -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 126999
Hi all, I'm trying to implement an analoge capturing project using Xilinx sx55 fpga and AD9510 as ADC. But I'v difficulty to program AD9510 clock distribution IC via its serial controller port to set divider parameters. The problem is that no handshake signal is recieved from serial port. because the signaling between SCP of AD9510 and V4-sx55 can not be simulated, I can not debug my code. I'd like to know has anyone worked with this A/D or other similar ICs? any App-note or practical code? any comment will be appreciated Thanks
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