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Hi Mike, I tried sending you a mail there. If you are still interested send me a mail as we can set you up with an Eval board. EoinArticle: 126926
I recall someone had figured out the schematics of the builtin USB based Jtag programmer on the Xilinx/Digilent Spartan-3E starter kit. Anyone happends to know where it is? Especially where and how the builtin usb-programmer is located in the jtag chain. (would be nice if one could reuse the usb port for other things aswell) I also looking for how to program it under Linux without unknown binary blobs. Is there already a solution for this (using libusb etc..) ? The alternative is to use a Parallel cable-III attached to J28.Article: 126927
On Dec 5, 6:19 pm, John Adair <g...@enterpoint.co.uk> wrote: > We have been promising this for a while and I am finally pleased to > show first images and details of Drigmorn1 herehttp://www.enterpoint.co.uk/component_replacements/drigmorn1.html. We > are aiming this to be the cheapest develoment board out there so if > know any cheaper do let me know. We have some more testing to do > before we let it out in the wild but hopefully that will be complete > before Christmas to allow shipment before the holidays. > > Use of this board is simplistic. A simple 5v jack for power and a > RS232 interface to allow control by a PC using a terminal emulator Why use 40 MHz when most other Xilinx FPGA boards are fitted with 50 MHz.? (would ease code portability) * Maybe you could leave some TSSOP54 or similar pad for soldering on a SDRAM chip..? * What are the three larger chips for? (one is M25P40 I assume) A further simplification would be to rid of the rs232, leds, and the dc power jack. Dc power can be had from the dil-40 pins.Article: 126928
On Dec 4, 5:56 pm, Eric Smith <e...@brouhaha.com> wrote:
> Anuja wrote:
> > assign Q = (rst==0)?Q_int:1'do;
>
> > How do i convert this to vhdl? I have to use a concurrent statement as
>
> Q <= Q_int when rst = '0' else '0';
Hi,
I am having simulation problems with my code. I am trying to convert
Verilog code to VHDL. I can compile correctly. When i simulate the
following code in VHDL, value of Q_int is stuck at "00". It does not
change at all. Please let me know what the problem could be.
Thanks for all your help
Verilog code =>
module Reg2(Q, D, en, rst, clk);
parameter REGWIDTH = 2;
input clk, en, rst;
input [(REGWIDTH-1):0] D;
output [(REGWIDTH-1):0] Q;
reg [(REGWIDTH-1):0] Q_int;
assign Q = (rst == 0)? Q_int : 2'd0;
always @ (posedge clk)
begin
if (rst == 1)
Q_int <= 2'd0;
else if (en == 1)
Q_int <= D;
else
Q_int <= Q_int;
end
endmodule
VHDL code =>
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Reg2 IS
PORT( clk, rst, en : IN std_logic;
D : IN std_logic_vector(1 downto 0);
Q : OUT std_logic_vector(1 downto 0)
);
END Reg2;
ARCHITECTURE behavioral OF Reg2 IS
-- register and constant declaration
SIGNAL Q_int : std_logic_vector(1 downto 0);
CONSTANT LO : std_logic := '0';
CONSTANT HI : std_logic := '1';
BEGIN
Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else "00";
one : PROCESS (clk)
BEGIN
IF (clk = HI and clk'event) THEN
IF (rst = HI) THEN
Q_int(1 downto 0) <= "00";
ELSIF (en = HI) THEN
Q_int(1 downto 0) <= D(1 downto 0);
ELSE
Q_int(1 downto 0) <= Q_int(1 downto 0);
END IF;
END IF;
END PROCESS one;
END behavioral;
Test Bench for above code is as follows =>
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_Reg2 is
-- testbench entity is ALWAYS EMPTY
END tb_Reg2;
ARCHITECTURE tb of tb_Reg2 is
-- temporary signals
SIGNAL clk_temp : std_logic := '0';
SIGNAL rst_temp, en_temp : std_logic := '0';
SIGNAL D_temp, Q_temp : std_logic_vector(1 downto 0):= "00";
-- component declaration
COMPONENT Reg2 is
PORT( clk, rst, en : IN std_logic;
D : IN std_logic_vector(1 downto 0);
Q : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
BEGIN
UUT : Reg2
PORT MAP( clk => clk_temp,
rst => rst_temp,
en => en_temp,
D => D_temp,
Q => Q_temp
);
-- Passing values to inputs
clk_temp <= (not clk_temp) after 5 ns;
rst_temp <= '0' after 0 ns, '1' after 3 ns, '0'
after 15 ns;
en_temp <= '1' after 5 ns,'0' after 36 ns;
D_temp <= "10" after 4 ns, "01" after 16 ns,
"11" after 32 ns,
"00" after 55 ns;
END tb; -- test bench ends
Article: 126929On Wed, 5 Dec 2007 09:19:21 -0800 (PST), John Adair <g1@enterpoint.co.uk> wrote: >We have been promising this for a while and I am finally pleased to >show first images and details of Drigmorn1 here >http://www.enterpoint.co.uk/component_replacements/drigmorn1.html. We >are aiming this to be the cheapest develoment board out there so if >know any cheaper do let me know. We have some more testing to do >before we let it out in the wild but hopefully that will be complete >before Christmas to allow shipment before the holidays. > >Use of this board is simplistic. A simple 5v jack for power and a >RS232 interface to allow control by a PC using a terminal emulator >etc. like Hyperterminal. Special variants do allow use as part of >customer boards or prototypes and we should have some application >notes coming on these more unusual uses of this board. > >I am also interested in what features everyone would like as and when >we do a Drigmorn2 bearing in mind it is a very cost sensative design. > >It's a derivative of the new version Craignell family (obsolete and >enhanced DIL/DIP component replacements) and pictures of those will be >available soon too. We have done a lot of work to improve >manufacturing yield on these and the Drigmorn1 and some of the work we >have done here will allow the even smaller narrow version Craignells >to made Q1/2008. > >John Adair >Enterpoint Ltd. I would guess that the through-hole parts are a not-insignificant part of the assembly cost - I would think most users wouldn't have a problem soldering these, and supplying the board without then would also allow flexibility e.g. to fit straight headers to plug into a prototyping board.Article: 126930
<posedge52@yahoo.com> wrote in message news:c9307fa4-e5a1-425c-80ee-09d517025732@w34g2000hsg.googlegroups.com... > On Dec 5, 6:19 pm, John Adair <g...@enterpoint.co.uk> wrote: >> We have been promising this for a while and I am finally pleased to >> show first images and details of Drigmorn1 >> herehttp://www.enterpoint.co.uk/component_replacements/drigmorn1.html. We >> are aiming this to be the cheapest develoment board out there so if >> know any cheaper do let me know. We have some more testing to do >> before we let it out in the wild but hopefully that will be complete >> before Christmas to allow shipment before the holidays. >> >> Use of this board is simplistic. A simple 5v jack for power and a >> RS232 interface to allow control by a PC using a terminal emulator > > Why use 40 MHz when most other Xilinx FPGA boards are fitted with 50 > MHz.? > (would ease code portability) > > * Maybe you could leave some TSSOP54 or similar pad for soldering on a > SDRAM chip..? > > * What are the three larger chips for? (one is M25P40 I assume) > > A further simplification would be to rid of the rs232 I would keep the RS232 or at least the line driver since RS232 is still one of the simplest method to connect the board to a PC. If you don't have a serial port than you can buy a low-cost (I paid £5 for mine) RS232-USB cable. Hans www.ht-lab.com PS Looks like a very nice board! >, leds, and the > dc power jack. Dc power can be had from the dil-40 pins.Article: 126931
On Thu, 06 Dec 2007 12:41:36 GMT, "HT-Lab" <hans64@ht-lab.com> wrote: > ><posedge52@yahoo.com> wrote in message >news:c9307fa4-e5a1-425c-80ee-09d517025732@w34g2000hsg.googlegroups.com... >> On Dec 5, 6:19 pm, John Adair <g...@enterpoint.co.uk> wrote: >>> We have been promising this for a while and I am finally pleased to >>> show first images and details of Drigmorn1 >>> herehttp://www.enterpoint.co.uk/component_replacements/drigmorn1.html. We >>> are aiming this to be the cheapest develoment board out there so if >>> know any cheaper do let me know. We have some more testing to do >>> before we let it out in the wild but hopefully that will be complete >>> before Christmas to allow shipment before the holidays. >>> >>> Use of this board is simplistic. A simple 5v jack for power and a >>> RS232 interface to allow control by a PC using a terminal emulator >> >> Why use 40 MHz when most other Xilinx FPGA boards are fitted with 50 >> MHz.? >> (would ease code portability) >> >> * Maybe you could leave some TSSOP54 or similar pad for soldering on a >> SDRAM chip..? >> >> * What are the three larger chips for? (one is M25P40 I assume) >> >> A further simplification would be to rid of the rs232 > >I would keep the RS232 or at least the line driver since RS232 is still one >of the simplest method to connect the board to a PC. If you don't have a >serial port than you can buy a low-cost (I paid £5 for mine) RS232-USB >cable. > >Hans >www.ht-lab.com > >PS Looks like a very nice board! > > >>, leds, and the >> dc power jack. Dc power can be had from the dil-40 pins. > Another suggestion - put a footprint for a 6-pin o.1" header for a FTDI TTL-232 cable - this is a nice quick way to get high-speed serial comms and 5V power. http://www.ftdichip.com/Products/EvaluationKits/TTL-232R.htmArticle: 126932
Hi, Is it possible to define clocks in the .sdc file of a design, while those clocks only appear in a peripheral or a core, i.e., clocks not in the top level of the design. Thanks, -JArticle: 126933
u_stadler@yahoo.de wrote: > hmm i'm still struggling with the clock gating. > i looked it up in the datasheet again : > http://www.xilinx.com/support/documentation/user_guides/ug070.pdf > > and on page 32 there is the timing diagramm for the bufgce. it appears > to > me that if the enable signal goes high the next clock edge should bee > seen > on the output. (if the enable signal is soon enough before that edge > of course). > but in my simulation it is not. any ideas what i'm doing wrong here or > don't > understand ? I'd suggest calling the support hotline. I suspect that the lone timing diagram you refer to is incorrect whereas the simulation (and real hardware) give different results than what that diagram communicates. If the user guide's information is valid, it's only valid because of an option set in the hardware which isn't the normal way the BUFCE operates. It's probable that the user guide documentation is just wrong and needs to be changed: something that can be effected by opening a case.Article: 126934
On Nov 24, 1:04 pm, "HT-Lab" <han...@ht-lab.com> wrote: > "fl" <rxjw...@gmail.com> wrote in message > > news:ccb086d1-775c-44cf-8666-bc357a309d93@b15g2000hsa.googlegroups.com... > > > Hi, > > I want to learn the implementation ofCORDIC. I find the following > > website has some code which I would like begin with it. > > >http://www.ht-lab.com/freecores/cordic/cordic.html > > > But I cannot simply simulate it in my Modelsim PE (student version) > > because of the setup problem. Could you, the FPGA and VHDL experts can > > tell me how to simulate it? Especially could you tell me how its > > structure about the behaviour and synthesis files arranged? > > > Thanks in advance. > > Send me an email and I will create a standalone Modelsim version for you. I > wrote this code some time ago using HDL Designer and Modelsim. > > Regards, > Hanswww.ht-lab.com We do appreciate, if it be possible to use a standalone Modelsim version of project. Would U plz upload it or give some clue. Sincerely. MrMArticle: 126935
>On Dec 4, 5:56 pm, Eric Smith <e...@brouhaha.com> wrote: >> Anuja wrote: >> > assign Q = (rst==0)?Q_int:1'do; >> >> > How do i convert this to vhdl? I have to use a concurrent statement as >> >> Q <= Q_int when rst = '0' else '0'; > >Hi, > >I am having simulation problems with my code. I am trying to convert >Verilog code to VHDL. I can compile correctly. When i simulate the >following code in VHDL, value of Q_int is stuck at "00". It does not >change at all. Please let me know what the problem could be. > Remove the line: Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else "00"; after the BEGIN of the architecture.Article: 126936
The M25P40 is the standard serial flash memory fitted. So there is some capacity to run a Microblaze etc.. I'll have to check the footprints but I think we can go to 16Mbit and possibly 32/64 Mbit as options. Power can be put in the pin header as an option and variants of the board with straight pins are an option we are considering offering. If you don't want the RS232, pins etc, then maybe the Craignell series are better for your application. They are smaller take the shape of a standard DIL/DIP (28,32,36,40 pins available) and very minimalist. Otherwise they are identical to the Drigmorn1. Leaving a site for something else is a possibility the future. We may also do a companion board to do some more. John Adair Enterpoint Ltd. On 6 Dec, 10:54, posedg...@yahoo.com wrote: > On Dec 5, 6:19 pm, John Adair <g...@enterpoint.co.uk> wrote: > > > We have been promising this for a while and I am finally pleased to > > show first images and details of Drigmorn1 herehttp://www.enterpoint.co.uk/component_replacements/drigmorn1.html. We > > are aiming this to be the cheapest develoment board out there so if > > know any cheaper do let me know. We have some more testing to do > > before we let it out in the wild but hopefully that will be complete > > before Christmas to allow shipment before the holidays. > > > Use of this board is simplistic. A simple 5v jack for power and a > > RS232 interface to allow control by a PC using a terminal emulator > > Why use 40 MHz when most other Xilinx FPGA boards are fitted with 50 > MHz.? > (would ease code portability) > > * Maybe you could leave some TSSOP54 or similar pad for soldering on a > SDRAM chip..? > > * What are the three larger chips for? (one is M25P40 I assume) > > A further simplification would be to rid of the rs232, leds, and the > dc power jack. Dc power can be had from the dil-40 pins.Article: 126937
On Dec 6, 9:43 am, "RCIngham" <robert.ing...@gmail.com> wrote: > >On Dec 4, 5:56 pm, Eric Smith <e...@brouhaha.com> wrote: > >> Anuja wrote: > >> > assign Q = (rst==0)?Q_int:1'do; > > >> > How do i convert this to vhdl? I have to use a concurrent statement > as > > >> Q <= Q_int when rst = '0' else '0'; > > >Hi, > > >I am having simulation problems with my code. I am trying to convert > >Verilog code to VHDL. I can compile correctly. When i simulate the > >following code in VHDL, value of Q_int is stuck at "00". It does not > >change at all. Please let me know what the problem could be. > > Remove the line: > > Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else "00"; > > after the BEGIN of the architecture.- Hide quoted text - > > - Show quoted text - How do i implement the logic assign Q = (rst == 0)? Q_int : 2'd0; if i remove Q(1 downto 0) <= Q_int(1 downto 0) when rst = LO else "00";Article: 126938
Mike As with any of our products if there is a demand we will offer the variant. We can build variants as part of a main build at relatively little cost. For specific customer needs we already do variants of chips in say industrial grade, or special pinning like our OVERCOAT option for board stacking and so on. Unlike many of competitors who offer a very fixed product, unless you want 10K+ units, we do special builds down at volumes as low as a few units. As always if someone wants something different it's always worth talking to one of my team in the office. John Adair Enterpoint Ltd. On 6 Dec, 12:02, Mike Harrison <m...@whitewing.co.uk> wrote: > On Wed, 5 Dec 2007 09:19:21 -0800 (PST), John Adair <g...@enterpoint.co.uk> wrote: > >We have been promising this for a while and I am finally pleased to > >show first images and details of Drigmorn1 here > >http://www.enterpoint.co.uk/component_replacements/drigmorn1.html. We > >are aiming this to be the cheapest develoment board out there so if > >know any cheaper do let me know. We have some more testing to do > >before we let it out in the wild but hopefully that will be complete > >before Christmas to allow shipment before the holidays. > > >Use of this board is simplistic. A simple 5v jack for power and a > >RS232 interface to allow control by a PC using a terminal emulator > >etc. like Hyperterminal. Special variants do allow use as part of > >customer boards or prototypes and we should have some application > >notes coming on these more unusual uses of this board. > > >I am also interested in what features everyone would like as and when > >we do a Drigmorn2 bearing in mind it is a very cost sensative design. > > >It's a derivative of the new version Craignell family (obsolete and > >enhanced DIL/DIP component replacements) and pictures of those will be > >available soon too. We have done a lot of work to improve > >manufacturing yield on these and the Drigmorn1 and some of the work we > >have done here will allow the even smaller narrow version Craignells > >to made Q1/2008. > > >John Adair > >Enterpoint Ltd. > > I would guess that the through-hole parts are a not-insignificant part of the assembly cost - I > would think most users wouldn't have a problem soldering these, and supplying the board without then > would also allow flexibility e.g. to fit straight headers to plug into a prototyping board.- Hide quoted text - > > - Show quoted text -Article: 126939
Hi all , Is it possible to use FSL read on an interrupt basis rather than polling? I have a scenario where i only want to read data using get instruction if there is data on the bus. Are there any example projects ? BR RateArticle: 126940
L. Schreiber, The module flow was removed from this app note (no longer supported). PlanAhead is available to universities through the XUP (Xilinx University Program). Ask your professor to request a copy and a license. AustinArticle: 126941
I'm a final yr student undertaking a project which requires a microcontroller with an operating clk freq at 60MHz. My university has altera DE2 boards available, which to my understanding has oscillators @ 50MHz. A suggestion was to overclock the fpga, however I don't know where to start looking. Would someone be able to point me in the right directions to obtaining such information ?Article: 126942
truongt1024@gmail.com wrote: > I'm a final yr student undertaking a project which requires a > microcontroller with an operating clk freq at 60MHz. > > My university has altera DE2 boards available, which to my > understanding has oscillators @ 50MHz. > > A suggestion was to overclock the fpga, however I don't know where to > start looking. Would someone be able to point me in the right > directions to obtaining such information ? You need to look into the data sheet of the FPGA you are using. Inside the FPGA you can increase the clock frequency from the external oscillator. So your logic can use a much faster clock signal than the external applied 50MHz. The data sheet will give you details about how to do that. Cheers, GuenterArticle: 126943
On Dec 6, 8:11 am, truongt1...@gmail.com wrote: > I'm a final yr student undertaking a project which requires a > microcontroller with an operating clk freq at 60MHz. > > My university has altera DE2 boards available, which to my > understanding has oscillators @ 50MHz. > > A suggestion was to overclock the fpga, however I don't know where to > start looking. Would someone be able to point me in the right > directions to obtaining such information ? Best place to start would be www.altera.com That board has a Cyclone-II on it. That Cyclone-II has 4 PLL's in it. These PLL's can be used to make (just about) any frequency you need. And as always, Google is your friend. Do try the search feature some time!Article: 126944
On Dec 5, 8:49 pm, Yui <aikenp...@gmail.com> wrote: > I know the simple answer will be use NisoII... > But in my situation is ..I cannot use NisoII or any other soft/hard > core processor (actually is..I am not able to use any asm/c ..whatever > computer programing language). > > I would want to know anyone try to build a FSM to "talk" with the > Avalon bus before? > What should I do/understand first for build a FSM to work as Master in > Avalon bus? > > My project require to receive packet and put them into memory and then > I have another logic to read from the memory. > > The data flow is that > Ethernet --> PHY(chip) --> TSE MAC IP --> Avalon bus --> memory -- > > >DDR2 controller ->DDR2 memory. > > What I have now: > 1. PCI Express Development Kit, Stratix II GX Edition (http://www.altera.com/products/devkits/altera/kit-pciexpress_s2gx.html) > 2. DDR2 controller demo (non Avalon Bus), (it is work on the PCI > Express Development Kit) > 3. TSE MAC IP (I did not try it..because all the demo are using > NiosII) The Avalon bus is exceptionally well documented. It is so easy to build masters and slaves for that bus that even I can do it. But (IMHO) the only reason to use Avalon is to take advantage of NIOS. I would use Wishbone for the situation you describe. The Wishbone bus is also very well documented.Article: 126945
<truongt1024@gmail.com> wrote in message news:94d1e4d3-a316-4cd4-a115-ea62337830cb@s8g2000prg.googlegroups.com... > I'm a final yr student undertaking a project which requires a > microcontroller with an operating clk freq at 60MHz. > > My university has altera DE2 boards available, which to my > understanding has oscillators @ 50MHz. > > A suggestion was to overclock the fpga, however I don't know where to > start looking. Would someone be able to point me in the right > directions to obtaining such information ? Besides doing what others have suggested with the FPGA's internal PLLs (for Altera) or DCMs (for Xilinx), you could also replace the 50MHz oscillator with a 60MHz one. Assuming that you've already mastered soldering, however, you'll learn much more if you figure out how to use the FPGA's internal resources to solve the problem. When you start designing stuff for a commercial (or other) venture, these types of "soft" solutions are invaluable to know about since they can usually save hardware cost and can also be used to implement field-upgradeable bug fixes -- I mean feature enhancements. ;-) BobArticle: 126946
On Dec 6, 8:53 am, ghel...@lycos.com wrote: > The Avalon bus is exceptionally well documented. It is so easy to > build masters and slaves for that bus that even I can do it. > > But (IMHO) the only reason to use Avalon is to take advantage of > NIOS. I would use Wishbone for the situation you describe. > > The Wishbone bus is also very well documented. I disagree. Avalon is far better for high performance transfers, including first class support for split transaction and burst transfers. In it's native form, Wishbone can only transfer data every other cycle (due to the way handshaking , and the proposed support for streaming is a 2nd class citizen and I haven't seen it used anywhere. Avalon works so well that I use it even outside the realm of NIOS II and without the support of of the SOC builder (I essentially have to replicate this functionality by hand). Sustained Gigabit ethernet traffic will require a 32-bit bus running at 32+ MHz with Avalon. That should not be a problem. TommyArticle: 126947
I'm using a version of XMK provided by Avnet, for Memec Virtex-4 FX12 LC Evaluation Board. It includes a xilkernel demo, but I've found the sample code not working. I type nothing in the PC, but the XMK keeps reporting unrecognized command endlessly. After certain investigation, the problem lies in inbyte() function. The character that inbyte() retrieve is actually the data that outbyte(), print() or xil_printf() has just sent out. Here is the result seen from HyperTerminal: ========================================================== XMK: Start XMK: Initializing Hardware... XMK: System initialization... XMK: Enabling interrupts and starting system... SHELL: Starting clock... CLOCK: Successfully registered a handler for extra timer interrupts. CLOCK: Configuring extra timer to generate one interrupt per second.. CLOCK: Enabling the interval timer interrupt... [ should be 80 empty lines here ] shell>XMK: Start Unrecognized command. Type 'help' to see available commands. shell>XMK: Unrecognized command. Type 'help' to see available commands. shell> shell> shell> shell> shell> shell>commanco. Unrecognized command. Type 'help' to see available commands. shell>> Unrecognized command. Type 'help' to see available commands. shell>> Unrecognized command. Type 'help' to see available commands. shell>> Unrecognized command. Type 'help' to see available commands. shell>> Unrecognized command. Type 'help' to see available commands. shell>shell> Unrecognized command. Type 'help' to see available commands. shell>cococococommandscommands. Unrecognized command. Type 'help' to see available commands. shell>shell>cococococcommands. Unrecognized command. Type 'help' to see available commands. shell>shell>shell>coccommands. Unrecognized command. Type 'help' to see available commands. shell>shell>shell>shecommands. Unrecognized command. Type 'help' to see available commands. shell>shell>shell>shecommands. Unrecognized command. Type 'help' to see available commands. shell>shell>shell>shecommands. Unrecognized command. Type 'help' to see available commands. shell>shell>shell>shecommands. Unrecognized command. Type 'help' to see available commands. shell>shell>shell>shecommands. Unrecognized command. Type 'help' to see available commands. shell>shell>shell>shecommands. Unrecognized command. Type 'help' to see available commands. [ loop endlessly for unrecognized command ] ========================================================== Where the correct output should be: ========================================================== XMK: Start XMK: Initializing Hardware... XMK: System initialization... XMK: Enabling interrupts and starting system... SHELL: Starting clock... CLOCK: Successfully registered a handler for extra timer interrupts. CLOCK: Configuring extra timer to generate one interrupt per second.. CLOCK: Enabling the interval timer interrupt... [ should be 80 empty lines here ] shell> ========================================================== I've found that in xparameters.h, the input and output base address is the same: #define STDIN_BASEADDRESS 0x70010000 #define STDOUT_BASEADDRESS 0x70010000 In the xuratlite_l.h, the transmit and receive fifo offset is only differ by 4: #define XUL_RX_FIFO_OFFSET 0 /* receive FIFO, read only */ #define XUL_TX_FIFO_OFFSET 4 /* transmit FIFO, write only */ Is this the reason of this problem? Or are they any other field to investigate? I've also found that in XMD, there are two lines missing if I compare to the tutorial document screenshot: PC reset to 0xfffffffc, Clearing MSR Register PC reset to 0xfffffffc, Clearing MSR Register which is below the line "Start PC with program start addr 0xfffffffc" in the document. One more finding is that someone said in newsgroup that there is bug about MSR for XMK, but I've no way to access to the patch. http://www.fpga-faq.com/archives/109175.html#109185 Does this related to the above problem? Do anyone has any ideas about this problem? Thanks. A related problem: I've found that when I edit these header files, the update are not included when I rebuild the project, or update and download bitstream. How should I refresh the xilkernel .h and .c files?Article: 126948
On Dec 6, 9:10 am, mrmoos...@gmail.com wrote: > On Nov 24, 1:04 pm, "HT-Lab" <han...@ht-lab.com> wrote: > > > > > > > "fl" <rxjw...@gmail.com> wrote in message > > >news:ccb086d1-775c-44cf-8666-bc357a309d93@b15g2000hsa.googlegroups.com... > > > > Hi, > > > I want to learn the implementation ofCORDIC. I find the following > > > website has some code which I would like begin with it. > > > >http://www.ht-lab.com/freecores/cordic/cordic.html > > > > But I cannot simply simulate it in my Modelsim PE (student version) > > > because of the setup problem. Could you, the FPGA and VHDL experts can > > > tell me how to simulate it? Especially could you tell me how its > > > structure about the behaviour and synthesis files arranged? > > > > Thanks in advance. > > > Send me an email and I will create a standalone Modelsim version for you. I > > wrote this code some time ago using HDL Designer and Modelsim. > > > Regards, > > Hanswww.ht-lab.com > > We do appreciate, if it be possible to use a standalone Modelsim > version of project. > Would U plz upload it or give some clue. > Sincerely. > MrM- Hide quoted text - > > - Show quoted text - Try Altera or Xilinx, etc. for the web or student version where they bundle in a limited version of Modelsim. KJArticle: 126949
> > On Dec 5, 8:49 pm, Yui <aikenp...@gmail.com> wrote: > > I would want to know anyone try to build a FSM to "talk" with the > > Avalon bus before? Yes, many times. > > What should I do/understand first for build a FSM to work as Master in > > Avalon bus? The Avalon specification would be the a good start. > On Dec 6, 11:53 am, ghel...@lycos.com wrote: > But (IMHO) the only reason to use Avalon is to take advantage of > NIOS. I would use Wishbone for the situation you describe. > > The Wishbone bus is also very well documented.- Hide quoted text - > While Wishbond and Avalon are both well documented, I would disagree with you about only using Avalon to take advantage of Nios. Tommy Thorn's post is right on the money about the ways that Avalon can be superior to Wishbone and I'd also add that for simple transactions with no read latency, Wishbone and Avalon are pretty much functionally identical, only the signal names are different. You don't need Nios, SOPC Builder or even be targetting an Altera part to make Avalon compatible widgets....but based on the questions of the original post, I think there are very basic hurdles that Yui needs to clear first since it doesn't appear that he has perused the Avalon specification since transactions are almost painfully simple handshakes (as with Wishbone). Kevin Jennings
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