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You can order pretty much anywhere within the EU without any issues. I am in Germany and regularly order in the UK. Try http://www.trenz-electronic.de/products/fpga-boards.html or http://www.silica.com/products/manufacturers/xilinx.html Kolja Sulimma On 26 Jan., 15:29, "deepa...@gmail.com" <deepa...@gmail.com> wrote: > Hi , > > Can anybody give me some information on buying fpga kits in > denmark? ..iam interested in the altera cyclone 3 starter kit! .,guess > its possible to order from Altera directly , but i might have to deal > with the import procedure myself ...I tried farnell elektronics > denmark (http://dk.farnell.com/jsp/home/homepage.jsp) ..but afaik they > deal only with companies and not individuals > > any information will be helpful > > Thank You, > > DeepakArticle: 128451
In article <a4e1p393u0n0dnui6bn4s52pmpa73lkqfm@4ax.com>, Pillock <a@b.c> wrote: >On Thu, 17 Jan 2008 21:14:46 -0500, in sci.electronics.basics, krw ><krw@att.bizzzzz> gurgled: >>CMOS doesn't like X-Rays much. There is a failure mechanism that >>tends to harden CMOS SRAM bits in one direction. I'm not sure how >>bad it gets though. > >THE HORRORS! > >Someone need to tell Agilent & Teradyne ASAP. Millions of boards a >year are run through their x-ray fault detection systems. >Digital boards quite often with memory. There's a heck of a big difference between running a board through an xray machine a few times, and having that board run for a long time being exposed to xrays of uncertain energy while it's operating. -- Wim Lewis <wiml@hhhh.org>, Seattle, WA, USA. PGP keyID 27F772C1Article: 128452
"RK" <sun.radha@gmail.com> wrote in message news:b474ae86-a1ac-44e5-a4dc-4020a67b9283@f10g2000hsf.googlegroups.com... > I am getting the following error in modelsim when I try to simulate > some thing. > > # Loading C:\Xilinx92i\smartmodel\nt\installed_nt/lib/pcnt.lib/ > swiftpli_mti.dll > # ** Error: (vsim-3193) Load of "C:\Xilinx92i\smartmodel\nt > \installed_nt/lib/pcnt.lib/swiftpli_mti.dll" failed: DLL dependent > library not found. > # ** Error: (vsim-PLI-3002) Failed to load PLI object file "C: > \Xilinx92i\smartmodel\nt\installed_nt/lib/pcnt.lib/swiftpli_mti.dll". > # Region: / > > I have no idea why this is coming up....any help please! Did you remember to run Xilinx's "Simulation Library Compilation Wizard"? It's in the Accessories subfolder (along with Core Generator, Floorplanner, etc.) The Compilation Wizard unpacks the smartmodel\nt directories. Also, if you're running Windows Vista, too bad -- the Smartmodel package doesn't install (and it gives you a tiny warning message -- very easy to miss!) (Workaround: Install ISE and Modelsim/PE on a Windows/XP machine. Run the Compilation Wizard on that machine. After it finishes, copy the contents of \xilinx92i\smartmodel\* over to the target machine.) One problem I encountered is Modelsim-PE is very sneaky about the modelsim.ini file. When you initially create "New Project" in Modelsim's GUI, it copies the modelsim.ini file to the project-file. If the original modelsim.ini file changes in any way, you have to manually incorporate those changes into your project (in my case it was just easier to create another new project.)Article: 128453
I thought about buying the Xilinx Spartan3A/1800DSP starter kit ($295 USD.) When I ran Core Generator 9.2i.04 (with IP Update #2), created a new Spartan3A/DSP project, then looked at what wonderous DSP-blocks I could add, I discovered almost everything fun is greyed out. Basically, the IP-Cores haven't been updated to support the 3A-DSP family (only the regular Spartan 3, 3E, 3A/3AN.) Well, at least DSP48A is in there, whoop de doo!Article: 128454
>A worthwhile analysis would begin with knowing the current waveforms >that the fpga pulls on its various supplies. That would then be dumped >into the measured or estimated impedance of the bypassed power pours. >Does such current waveform info exist for your part, in your >application? If not, it's back to thumps. Has anybody tried writing nasty test code? My straw man would toggle a lot of FFs for X cycles, then do nothing for X cycles. Loop. Scan through various X to see what happens. Many years ago, there was a whole branch of hardware geeks that did nothing but write memory tests. I wonder if that sort of technology would be useful for FPGAs. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 128455
I've got major issues here. I've installed Xilinx 9.2i with the latest updates and service packs, and am trying to get Synplify 8.9 to actually work with it. The problem is that although I can compile my code fine, when it comes time to start the Place and Route state, nothing happens. I know my project files are OK because I ran the same project on another machine which had the same software except for an earlier version of Xilinx. I even created a test project from scratch to test this, and the same problem occured - Xilinx just won't take over after compilation in Synplicity (both Premier and Pro suffer the same problem). It should *just work*, it has so in the past. I have the par implementation ticked and XILINX & PATH env settings all enabled properly. I would have though if Synplicity couldn't activate that it would complain with an error message, but it's as if it's not even trying to load the xilinx tools to continue. Since the only difference between this machine and the one that works is a newer version of Xilinx, I'm guessing it's too new for Synplify 8.9. I have no idea what to do.Article: 128456
As Kolja said importing from anywhere in the EEC should be easy. As an individual any selling company will apply the local VAT rate which varys a little between the EEC countries. Watch out for carriage charges as some some companies do charge a bit over the odds sometimes. If you purchase outside of the EEC say from the US the courier/postal service may levy a charge for handling the VAT or other taxation collection. If use a curier like FEDEX etc. they usually they handle this very smoothly and delivery can usually be quick. As an example we do this every day in the opposite direction where we usually deliver from the UK next day, or next day + 1, into the US depending on whether an order meets our shipping cutoff time. John adair Enterpoint Ltd. - Home of Craignell. The DIL FPGA Module. On 26 Jan, 21:44, "comp.arch.fpga" <ksuli...@googlemail.com> wrote: > You can order pretty much anywhere within the EU without any issues. I > am in Germany and regularly order in the UK. > > Tryhttp://www.trenz-electronic.de/products/fpga-boards.html > orhttp://www.silica.com/products/manufacturers/xilinx.html > > Kolja Sulimma > > On 26 Jan., 15:29, "deepa...@gmail.com" <deepa...@gmail.com> wrote: > > > > > Hi , > > > Can anybody give me some information on buying fpga kits in > > denmark? ..iam interested in the altera cyclone 3 starter kit! .,guess > > its possible to order from Altera directly , but i might have to deal > > with the import procedure myself ...I tried farnell elektronics > > denmark (http://dk.farnell.com/jsp/home/homepage.jsp) ..but afaik they > > deal only with companies and not individuals > > > any information will be helpful > > > Thank You, > > > Deepak- Hide quoted text - > > - Show quoted text -Article: 128457
Hal Murray schrieb: >> A worthwhile analysis would begin with knowing the current waveforms >> that the fpga pulls on its various supplies. That would then be dumped >> into the measured or estimated impedance of the bypassed power pours. >> Does such current waveform info exist for your part, in your >> application? If not, it's back to thumps. > > Has anybody tried writing nasty test code? > > My straw man would toggle a lot of FFs for X cycles, then > do nothing for X cycles. Loop. Scan through various X > to see what happens. I did quite some time ago. http://www.geocities.com/jacquesmartini Try again some time later, ist just a cheap (free) account with 4MB/hour and I just blew it :-0 Regards FalkArticle: 128458
Hal Murray schrieb: >> A worthwhile analysis would begin with knowing the current waveforms >> that the fpga pulls on its various supplies. That would then be dumped >> into the measured or estimated impedance of the bypassed power pours. >> Does such current waveform info exist for your part, in your >> application? If not, it's back to thumps. > > Has anybody tried writing nasty test code? OK, its available again. http://www.geocities.com/jacquesmartini/digital/pldpower/pld_power_measurement.html Regards FalkArticle: 128459
>If you purchase outside of the EEC say from the US the courier/postal >service may levy a charge for handling the VAT or other taxation >collection. If use a curier like FEDEX etc. they usually they handle >this very smoothly Couriers like Fedex etc. often charge an excessive fee for cleearance- normal postal service are usually preferable in this respect but this may vary by country.Article: 128460
Hi *, since switching to ISE9.2, one of my favourite topics has come up again... Basically, what I have is an FPGA with a bank that has a VCCO of 3.3V. This bank has several LVTTL outputs and a few LVDS25-inputs. At the time when the board was designed, this was a valid configuration: LVDS-input buffers are powered from VCCAUX, which is always 2.5V, so it doesn't matter what your VCCO on that bank is. ISE8.2, which was used at the beginning of development, didn't even issue a warning here. Starting with ISE9.1, par would stop with a FATAL_ERROR, because I was using the DIFF_TERM-attribute on those LVDS-inputs, and it turns out that even though the input buffers are powered from VCCAUX, the termination is not, i.e. in the case where VCCO!=2.5V the termination value is not 100 Ohms, but something else, unspecified. In my case it didn't matter, everything works fine with that "wrong" termination as well, and it turns out that there is some magical environment variable you can set so par will just ignore this and finish its job. Now I tried the design in ISE9.2, and it again fails (despite setting the mentioned environment variable), this time issuing an error message stating that LVDS-inputs cannot be put in the same bank as LVTTL-outputs. This combination of IO standards is now forbidden completely. Question is: Why? Looking at the latest Virtex4 data sheet (ug070 2.3 from 8/10/2007, page 304, table 6-38), there is one footnote that was added 4 days after the previous doc release. It says: "Differential inputs and inputs using VREF are powered from VCCAUX. However, pin voltage must not exceed VCCO, due to the presence of clamp diodes to VCCO.". I don't quite see the relevance to my case here, but that's what changed last... cu, Sean -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 128461
"Hal Murray" <hal-usenet@ip-64-139-1-69.sjc.megapath.net> wrote in message news:SMidnXjLmYc4uQHanZ2dnUVZ_tLinZ2d@megapath.net... > >>A worthwhile analysis would begin with knowing the current waveforms >>that the fpga pulls on its various supplies. That would then be dumped >>into the measured or estimated impedance of the bypassed power pours. >>Does such current waveform info exist for your part, in your >>application? If not, it's back to thumps. > > Has anybody tried writing nasty test code? > > My straw man would toggle a lot of FFs for X cycles, then > do nothing for X cycles. Loop. Scan through various X Not sure why doing nothing for X cycles is of any use. It's fairly simple (and useful) to write code for something that simply toggles every output pin on every clock and put each of those outputs at the end of a long shift register so that internal flops in the device get used as well. Run it at different clock speeds, if it's suits your needs. Been there, done that....it's a good stress test. KJArticle: 128462
KJ schrieb: >> My straw man would toggle a lot of FFs for X cycles, then >> do nothing for X cycles. Loop. Scan through various X > > Not sure why doing nothing for X cycles is of any use. To measure the broadband step response of your power supply network. http://www.geocities.com/jacquesmartini/digital/pldpower/pld_power_measurement.html > as well. Run it at different clock speeds, if it's suits your needs. Been > there, done that....it's a good stress test. It ist NOT enough! Regards FalkArticle: 128463
>> Has anybody tried writing nasty test code? >> >> My straw man would toggle a lot of FFs for X cycles, then >> do nothing for X cycles. Loop. Scan through various X > >Not sure why doing nothing for X cycles is of any use. I was trying to draw current at a lower frequency. Adjusting X changes the frequency of the load. Toggling everything would take the most current, but it the on chip caps work well the rest of the system will see a nice simple DC load. Waiting half the time will only draw half as much current but at a lower frequency that the power supply might not like. -- These are my opinions, not necessarily my employer's. I hate spam.Article: 128464
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:60410aF1pe4mqU1@mid.individual.net... > KJ schrieb: > >>> My straw man would toggle a lot of FFs for X cycles, then >>> do nothing for X cycles. Loop. Scan through various X >> >> Not sure why doing nothing for X cycles is of any use. > > To measure the broadband step response of your power supply network. > > http://www.geocities.com/jacquesmartini/digital/pldpower/pld_power_measurement.html > >> as well. Broadband step response is not terribly useful, you want to know what the impedance is across the entire frequency band that the part can draw power from. Sweeping the clock frequency with a design that toggles everything and measuring supply voltage dips and looking for functional upsets is more strenuous. >> Run it at different clock speeds, if it's suits your needs. Been there, >> done that....it's a good stress test. > > It ist NOT enough! > It's much more than a step response. KJArticle: 128465
"Hal Murray" <hal-usenet@ip-64-139-1-69.sjc.megapath.net> wrote in message news:X-idnQg32c4zUwHanZ2dnUVZ_sbinZ2d@megapath.net... > >>> Has anybody tried writing nasty test code? >>> >>> My straw man would toggle a lot of FFs for X cycles, then >>> do nothing for X cycles. Loop. Scan through various X >> >>Not sure why doing nothing for X cycles is of any use. > > I was trying to draw current at a lower frequency. > Adjusting X changes the frequency of the load. > OK, but so does simply changing the clock frequency. Sweeping the clock frequency from DC to light will gather the information. > Toggling everything would take the most current, but it > the on chip caps work well the rest of the system will see > a nice simple DC load. I doubt that it would be a DC load. Those on chip caps get their charge from the caps on the PCB through the PCB impedance. Those caps in turn get their charge from other caps and PCB impedance and on back to the regulator. None of that will make the chip look like a DC load. In fact if it did look like a DC load then one wouldn't need to supply any capacitors on the board since the regulator can certainly supply the current demands of a DC load. > Waiting half the time will only > draw half as much current but at a lower frequency that > the power supply might not like. > No, the amount of current is only 'half' in some overall global measurement of power draw. The chip needs to be supplied with the instantaneous current that it demands to operate (otherwise it will fail functionally). The instantaneous power demand of the part when it does make it's demand after waiting is the same as if you hadn't waited at all. If it suddenly needs an extra 1A on 'this' clock cycle, it won't matter that the last time it needed the 1A was the previous clock cycle or if it was 'X' clock cycles ago...that is until you get up to the point where the part is on the verge of failing because the power distribution network of the entire system can not supply the dynamic power quickly enough (which is what you're testing to try to find). KJArticle: 128466
KJ schrieb: > Broadband step response is not terribly useful, you want to know what the > impedance is across the entire frequency band that the part can draw power > from. I think so. You can do a fourier transformation to convert the step resonse into the freqeuncy domain. > Sweeping the clock frequency with a design that toggles everything > and measuring supply voltage dips and looking for functional upsets is more > strenuous. Iam afraid you are mixing this up with a frequency sweep using a SINE wave signal, as you would do whn you measure a filter or something. But a clock with variable frequency is NOT a sine wave. So the behaviour is different. If you do continous toggling at different freqeuncies, your voltage regulator will not be challenged, since it has only to supply a constant current. Similar for low frequency caps. Only a burst signal will stress ALL components. Read the link and think about it. > It's much more than a step response. OK, my fault. I mean a step resonse to a burst signal. Regards FalkArticle: 128467
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:6042kcF1ovaijU1@mid.individual.net... > KJ schrieb: > >> Broadband step response is not terribly useful, you want to know what the >> impedance is across the entire frequency band that the part can draw >> power from. > > I think so. You can do a fourier transformation to convert the step > resonse into the freqeuncy domain. > What you're interested in is knowing what the effective source impedance of the power supply network is across the entire frequency band of interest (DC to light). Step response doesn't really do that very well. >> Sweeping the clock frequency with a design that toggles everything and >> measuring supply voltage dips and looking for functional upsets is more >> strenuous. > > Iam afraid you are mixing this up with a frequency sweep using a SINE wave > signal, as you would do whn you measure a filter or something. But a clock > with variable frequency is NOT a sine wave. Not at all. Those toggling flip flops are all squarish waves and each of them toggling presents a whole slew of harmonics to the entire power supply system. > So the behaviour is different. If you do continous toggling at different > freqeuncies, your voltage regulator will not be challenged, since it has > only to supply a constant current. Nope, not DC....but your PCB/caps do need to be designed adequately so that the regulator is only being called on to supply current over a relatively small frequency range since the output inductance that it presents will prevent it from supplying any high frequency current. Maybe you're missing that when I say to sweep the clock frequency I'm not meaning just somewhere around the operating point but all the way from DC up to as high as you can go with the part. > Similar for low frequency caps. Only a burst signal will stress ALL > components. Read the link and think about it. > Again, every toggling output is a squarish wave and the chip will be making demands for current over a broad frequency range, regardless. KjArticle: 128468
When I evaluated Active-HDL this past summer (7.2sp1), I liked the user-interface more than Modelsim. However, Aldec's Systemverilog support was quite far behind Modelsim 6.2g. Now, I was wondering how these two products compare, today. Looking at Aldec's online manual, it seems Active-HDL 7.3 has caught up with Modelsim PE. (PE still supports some constructs that Aldec doesn't, but Aldec has rudimentary support for classes.) Performance-wise which is faster? (Most likely, my decision is between Active-HDL "Plus Edition" and Modelsim-PE.) Any problems with the Smartmodel/LMTV interface? (This is standard for Modelsim/PE, but a separate upgrade for Active-HDL Plus-Edition.) And a final question. I know that Xilinx/Altera's development-suite officially support the Modelsim simulator. For example, the Xilinx EDK can autogenerate control-scripts and autolaunch a Modelsim session. Does Active-HDL have the same level of integration with Xilinx/Altera's development environment?Article: 128469
FoolsGold wrote:
> Since the only difference between this machine and the one that works is
> a newer version of Xilinx, I'm guessing it's too new for Synplify 8.9. I
> have no idea what to do.
I'd open a case with both vendors
and send them my code.
-- Mike Treseler
Article: 128470On Jan 27, 1:20 pm, "talkb" <no...@talkb.com> wrote: > When I evaluated Active-HDL this past summer (7.2sp1), I liked the > user-interface more than Modelsim. However, Aldec's Systemverilog support > was quite far behind Modelsim 6.2g. > > Now, I was wondering how these two products compare, today. > Looking at Aldec's online manual, it seems Active-HDL 7.3 has caught up > with Modelsim PE. (PE still supports some constructs that Aldec doesn't, > but Aldec has rudimentary support for classes.) > > Performance-wise which is faster? (Most likely, my decision is between > Active-HDL "Plus Edition" and Modelsim-PE.) > > Any problems with the Smartmodel/LMTV interface? (This is standard > for Modelsim/PE, but a separate upgrade for Active-HDL Plus-Edition.) > > And a final question. I know that Xilinx/Altera's development-suite > officially support the Modelsim simulator. For example, the Xilinx EDK > can autogenerate control-scripts and autolaunch a Modelsim session. > Does Active-HDL have the same level of integration with Xilinx/Altera's > development environment? Smartmodels are not standard with Modelsim-PE. You can get them, but it is an additional license at additional cost. Did someone tell you it was standard with PE? They are standard with SE. You can get a list of what each version of ModelSim supports here: http://www.model.com/products/products_comparison.asp Regards, John McCaskillArticle: 128471
talkb wrote:
> Performance-wise which is faster? (Most likely, my decision is between
> Active-HDL "Plus Edition" and Modelsim-PE.)
I would get eval versions of both vendors to see
how each worked on my machine with my code,
and which vendor was easier to deal with on licensing.
-- Mike Treseler
Article: 128472"John McCaskill" <jhmccaskill@gmail.com> wrote in message news:17a49aef-994b-435f-a423-2f7ab0f8c89b@i3g2000hsf.googlegroups.com... > Smartmodels are not standard with Modelsim-PE. You can get them, but > it is an additional license at additional cost. Did someone tell you > it was standard with PE? They are standard with SE. > > You can get a list of what each version of ModelSim supports here: > > http://www.model.com/products/products_comparison.asp That is wierd -- I could have sworn the product-sheet showed PE with Smartmodel as a standard feature. Many of Xilinx's IP-blocks (Rocket I/O GTP, Virtex4/5 TEMAC, PowerPC) require a Smartmodel capable simulator -- I've used PE 6.3c to simulate several TEMAC/PowerPC based Xilinx FPGA designs. I was pretty sure PE supported Smartmodels, since I had to edit the modelsim.ini file to read in the Xilinx-provided Smartmodel/LMTV binaries. Or perhaps Xilinx used a special-wrapper, such that their sim-models look and act like conventional Verilog-PLI?Article: 128473
On Jan 27, 4:56 pm, "talkb" <no...@talkb.com> wrote: > "John McCaskill" <jhmccask...@gmail.com> wrote in message > > news:17a49aef-994b-435f-a423-2f7ab0f8c89b@i3g2000hsf.googlegroups.com... > > > Smartmodels are not standard with Modelsim-PE. You can get them, but > > it is an additional license at additional cost. Did someone tell you > > it was standard with PE? They are standard with SE. > > > You can get a list of what each version of ModelSim supports here: > > >http://www.model.com/products/products_comparison.asp > > That is wierd -- I could have sworn the product-sheet showed PE with > Smartmodel > as a standard feature. > > Many of Xilinx's IP-blocks (Rocket I/O GTP, Virtex4/5 TEMAC, PowerPC) > require a Smartmodel capable simulator -- I've used PE 6.3c > to simulate several TEMAC/PowerPC based Xilinx FPGA designs. > > I was pretty sure PE supported Smartmodels, since I had to edit the > modelsim.ini file > to read in the Xilinx-provided Smartmodel/LMTV binaries. > Or perhaps Xilinx used a special-wrapper, such that their sim-models look > and act > like conventional Verilog-PLI? You can use Smartmodels with ModelSim PE, you just need to get a license for it. Look in the license file on the computer that you used to see if it had a license. I use ModelSim PE with extra license for Smartmodels, mixed language support, and code coverage. Even with getting the extra licenses PE was much cheaper than SE. Most of the difference is because of using a dongle instead of a floating license. SE comes standard with a floating license. EDK supports ModelSim, and Cadence, but not Aldec. Regards, John McCaskill www.FasterTechnology.comArticle: 128474
This is a multi-part message in MIME format. ------=_NextPart_000_000D_01C8610D.2C7567A0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable "John McCaskill" <jhmccaskill@gmail.com> wrote in message = news:aa864ccf-655f-445e-9a68-a25979acbdc2@v67g2000hse.googlegroups.com...= > You can use Smartmodels with ModelSim PE, you just need to get a > license for it. Look in the license file on the computer that you used > to see if it had a license. I use ModelSim PE with extra license for > Smartmodels, mixed language support, and code coverage. Even with > getting the extra licenses PE was much cheaper than SE. Most of the > difference is because of using a dongle instead of a floating license. > SE comes standard with a floating license. Modelsim/SE is a (ASIC) "sign-off grade" simulator -- it's more = expensive=20 for that reason alone, though cheaper than its competition (Synopsys = VCS, Cadence Incisive.) Once upon a time, Cadence made a desktop simulator product called "Verilog Desktop" -- it was priced to compete with Modelsim/PE, Aldec, = etc. But I'd guess Cadence didn't get any traction in the FPGA and desktop=20 simulation market, so they stopped after version 5.1 or so. > EDK supports ModelSim, and Cadence, but not Aldec. I did notice Xilinx's Library Compilation Wizard only gives two choices: Modelsim or NC-Sim. But Aldec's support page has downloadable = (precompiled) libraries for both ISE 9.2.04i and EDK 9.2i.02. I'm hoping this means Active-HDL is usable for EDK-simulation, even if Xilinx doesn't = officially sanction it. --------------------------------------- I downloaded and installed the Active-HDL 7.3 downloadable demo. Systemverilog support is almost nearly caught up with Modelsim/PE 6.3c. Of the many things I tried (which I KNOW work with PE 6.3c), most = worked. Unfortunately, there is 1 critical feature missing: package/endpackage Modelsim/PE has suppored packages for a while now (and actually, so does Altera Quartus II 7.2sp1.) On the plus-side, Active-HDL has some things that Modelsim doesn't: rudimentary support for class declaration, (intreface) clocking block I think Mentor groups these features into the Questasim license (for=20 Modelsim/SE), which means they won't be part of Modelsim/PE for the=20 forseeable future. ------=_NextPart_000_000D_01C8610D.2C7567A0 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML><HEAD> <META http-equiv=3DContent-Type content=3D"text/html; = charset=3Diso-8859-1"> <META content=3D"MSHTML 6.00.6000.16587" name=3DGENERATOR> <STYLE></STYLE> </HEAD> <BODY bgColor=3D#ffffff background=3D""> <DIV><FONT face=3DCourier size=3D2>"John McCaskill" = <jhmccaskill@gmail.com>=20 wrote in message=20 news:aa864ccf-655f-445e-9a68-a25979acbdc2@v67g2000hse.googlegroups.com...= <BR>>=20 You can use Smartmodels with ModelSim PE, you just need to get a<BR>> = license=20 for it. Look in the license file on the computer that you used<BR>> = to see if=20 it had a license. I use ModelSim PE with extra license for<BR>> = Smartmodels, mixed language support, and code coverage. Even = with<BR>>=20 getting the extra licenses PE was much cheaper than SE. Most of = the<BR>>=20 difference is because of using a dongle instead of a floating = license.<BR>>=20 SE comes standard with a floating license.<BR><BR>Modelsim/SE is a = (ASIC)=20 "sign-off grade" simulator -- it's more expensive <BR>for that reason = alone,=20 though cheaper than its competition (Synopsys VCS,<BR>Cadence=20 Incisive.)<BR><BR>Once upon a time, Cadence made a desktop simulator = product=20 called<BR>"Verilog Desktop" -- it was priced to compete with = Modelsim/PE, Aldec,=20 etc.<BR>But I'd guess Cadence didn't get any traction in the FPGA and = desktop=20 <BR>simulation market, so they stopped after version 5.1 or = so.<BR><BR>> EDK=20 supports ModelSim, and Cadence, but not Aldec.<BR><BR>I did notice = Xilinx's=20 Library Compilation Wizard only gives two choices:<BR>Modelsim or = NC-Sim. =20 But Aldec's support page has downloadable (precompiled)<BR>libraries for = both=20 ISE 9.2.04i and EDK 9.2i.02. I'm hoping this means</FONT></DIV> <DIV><FONT face=3DCourier size=3D2>Active-HDL is usable for = EDK-simulation, even if=20 Xilinx doesn't officially</FONT></DIV> <DIV><FONT face=3DCourier size=3D2>sanction it.</FONT></DIV> <DIV><FONT face=3DCourier size=3D2></FONT> </DIV> <DIV><FONT face=3DCourier=20 size=3D2>---------------------------------------</FONT></DIV> <DIV><FONT face=3DCourier size=3D2></FONT> </DIV> <DIV><FONT face=3DCourier size=3D2>I downloaded and installed the = Active-HDL 7.3=20 downloadable demo.<BR>Systemverilog support is almost nearly caught up = with=20 Modelsim/PE 6.3c.<BR>Of the many things I tried (which I KNOW work with = PE=20 6.3c), most worked.</FONT></DIV> <DIV><FONT face=3DCourier size=3D2>Unfortunately, there is 1 critical = feature=20 missing: </FONT><FONT face=3DCourier = size=3D2>package/endpackage<BR>Modelsim/PE has=20 suppored packages for a while now (and actually, so does</FONT></DIV> <DIV><FONT face=3DCourier size=3D2>Altera Quartus II = 7.2sp1.)</FONT></DIV> <DIV><FONT face=3DCourier size=3D2><BR>On the plus-side, Active-HDL has = some things=20 that Modelsim doesn't:<BR>rudimentary support for class = declaration,=20 (intreface) clocking block<BR><BR>I think Mentor groups these features = into the=20 Questasim license (for </FONT></DIV> <DIV><FONT face=3DCourier size=3D2>Modelsim/SE), which means they = won't be part=20 of Modelsim/PE for the </FONT></DIV> <DIV><FONT face=3DCourier size=3D2>forseeable=20 future.<BR><BR></DIV></FONT></BODY></HTML> ------=_NextPart_000_000D_01C8610D.2C7567A0--
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