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On Jan 30, 9:54 am, cpan...@yahoo.com wrote: > On Jan 30, 12:11 am, "BobW" <nimby_NEEDS...@roadrunner.com> wrote: > > > > > <cpan...@yahoo.com> wrote in message > > >news:02be1a91-ec9b-49a6-824b-b80b8daf1301@s13g2000prd.googlegroups.com... > > > >I have a Spartan3 Bank VCCO pins connected to 1.8V. Normally I use > > > this bank to generate 1.8V push-pull signals but I needto drive out > > > 3.3V signal on this bank. Can I drive out open drain output with > > > external pull-up resistor to 3.3V on a 1.8V I/O bank? > > > > Thanks. > > > > CP > > > There are diodes on each I/O that will prevent that I/O from going above > > VCCO or below GND by more than a "diode drop". > > > If the resistor is large enough you won't do any damage, but you won't get > > the high level voltage you're expecting. > > > Bob > > Hi, > > I was thiking that I use these outputs as static signals but even with > a week pullup (100KOhm), it seem that the high voltage will still not > reach to 3.3V unless, I use external voltage translator from 1.8 to > 3.3 > > Thanks. > > CP The output may not need to reach 3.3V depending on the load. 3.3V logic often has a Vih (min) of 2.0V like TTL. The additional diode drop on top of 1.8V can get you to about 2.3V, but you'll need a smaller pullup than 100K to get there. on the other hand, a single-gate logic device in SOT23 or similar package can do the job nicely without the stress on the protection diodes. Your choice (obviously). regards, GaborArticle: 128551
Gabor <gabor@alacron.com> writes: > I think you'll find a lot of posts by Xilinx users who aren't familiar > with comp.arch.fpga, and since the new forum site has taken away the > portal to c.a.f they are not likely to find it as quickly as they used > to. My biggest gripe with the Xilinx forums is the excessive > compartmentalizing and lack of a "latest posts" view. There are > many other supporters of "latest post" view in the forums, but > so far the site hasn't been updated to include it. In the meantime > my guess is that people unaware of c.a.f will post on the Xilinx > forums, and those who know of c.a.f will continue to post here for > a quicker response from a broader user base. I've been trawling the Altera forums of late - they're much more usable. And prettier (but hasn't that always been the difference between Altera and xilinx tools :-) Cheers, Martin (personal opinions only!)Article: 128552
I have defined two functions as below function complexMult (a_i,a_q,b_i,b_q: signed) return complex is variable a,b : complex; variable result : complex; begin assert a_i = a_q report "Error : complexMult - a_i and a_q are not of equal length." severity error; assert b_i = b_q report "Error : complexMult - a_i and a_q are not of equal length." severity error; a.i := a_i; a.q := a_q; a.max := a_i'length; b.i := b_i; b.q := b_q; b.max := b_i'length; result := complexMult(a,b); return result; end function complexMult; function complexMult (a,b: complex) return complex is variable result : complex; begin result.max := maxVal(a.max,b.max) + 1; result.i := ((a.i * b.i) - (a.q * b.q)); result.q := ((a.i * b.q) + (b.i * a.q)); return result; end function complexMult; I am not sure if i can use the same record type for result and inputs a and b. Note that a and b can be of different lengths. Output "result" is going to be max(a'length, b'length) + 1 .. I add a one for the overflow and underflow that can be generated from the addition and subtraction. In the simulation , for eg : if a'length = 10 and b'length =5 then I want result'length = 11. I am trying to do this by not declaring different record types for input and outputs. Can i do this? If so, should the testbench be described as follows a.max <= 10; a.i <= ".. 10 bits ..."; a.q <= " .. 10 nits..."; b.max <= 10; b.i <= ".. 5 bits ..."; b.q <= " .. 5 bits..."; Please give your feedbackArticle: 128553
On Jan 29, 10:14 pm, mk <kal*@dspia.*comdelete> wrote: > Hi, > I updated theGTKWavefor Win32 port I am maintaining. It's at 3.1.3. > This current version is built against GTK 2.12.6 so you'll need to get > the libs.tar.gz. The new GTK fixes a problem which happens with Vista. > > http://www.dspia.com/gtkwave.html Note that there might be problems with that then. For 3.1.4 (ready to be released within the next couple of days), there's a fix for some new behavior I saw turn up in GTK 2.12.14: 1) Do a reload 2) Drag and drop from the tree widget: the signal window is now dead. If that's the case for you, you'll need to grab the version from CVS. Whatever the case I'll do a release soon. -TonyArticle: 128554
Have you got access to a simulator? Why not try it with a few obvious cases? >I have defined two functions as below > >function complexMult (a_i,a_q,b_i,b_q: signed) return complex is > variable a,b : complex; > variable result : complex; >begin > assert a_i = a_q report "Error : complexMult - a_i and a_q are not >of equal length." > severity error; > > assert b_i = b_q report "Error : complexMult - a_i and a_q are not >of equal length." > severity error; > > a.i := a_i; > a.q := a_q; > a.max := a_i'length; > b.i := b_i; > b.q := b_q; > b.max := b_i'length; > result := complexMult(a,b); > return result; >end function complexMult; > >function complexMult (a,b: complex) return complex is > variable result : complex; >begin > result.max := maxVal(a.max,b.max) + 1; > result.i := ((a.i * b.i) - (a.q * b.q)); > result.q := ((a.i * b.q) + (b.i * a.q)); > return result; >end function complexMult; > >I am not sure if i can use the same record type for result and inputs >a and b. Note that a and b can be of different lengths. Output >"result" is going to be max(a'length, b'length) + 1 .. I add a one for >the overflow and underflow that can be generated from the addition and >subtraction. > >In the simulation , for eg : if a'length = 10 and b'length =5 then I >want result'length = 11. I am trying to do this by not declaring >different record types for input and outputs. Can i do this? If so, >should the testbench be described as follows > >a.max <= 10; >a.i <= ".. 10 bits ..."; >a.q <= " .. 10 nits..."; >b.max <= 10; >b.i <= ".. 5 bits ..."; >b.q <= " .. 5 bits..."; > >Please give your feedback > > >Article: 128555
fatima <fmansoori@gmail.com> wrote: > hi all When attempting to interface to a new bust, I recommend extra attention to ensure that all handshaking and arbitration rules are followed to avoid protocol errors that may lead to hazardous feedback effects. While theoretical concerns are important, ultimately a hands-on approach may be called for. G.Article: 128556
Hi, I have a quick question, and its been bothering me for at least 3 hours. So I made a project in EDK, and I simply want to run the memory test (powerpc). When I followed all the steps (generate bitstream, download bitstream,etc), the code seemed to be fine, because it showed "programmed successfully" in the console, and the led's on my ML310 board did light to red (meaning it's processing) for a while and went back to green. However, nothing shows up in the hyperterminal (im expecting to see the words like "Running 32-bit test--passed", "running 8-bit test--passed"), but I didnt. I checked the RS232 connection, and they worked just fine, because the welcome screen does show up everytime on hyperterminal when I turn the power on. I was wondering if its because of the version? Im using 9.1 EDK.....does everybody know why this is happening? Thank you so much.Article: 128557
fatima wrote: > Subject: define a new bust interface Is a "new bust interface" related to the "bra code reader" that was discussed in comp.home.automation and sci.electronics back in 1995?Article: 128558
I use External Peripheral Controller to access various peripherals from my MicroBlaze/PPC based systems. To allow access to slow serial off-chip peripherals I always set C_PRHx_RDY_WIDTH long enough to suppress bus timeout before peripheral is ready. I never had problems with opb_epc in EDK <8.2. My recent design is developed in EDK 9.2 and here goes the problem... The opb bus was deprecated and opb_epc was replaced by xps_epc connected to plb. I set all the xps_epc parameters exactly the same like I was used to do in opb_epc. The design works fine for fast peripherals but does not work at all with slow ones. For example, I set C_PRHx_RDY_WIDTH to 100us to be able to access Ethernet MAC using MIIM interface with access time ~32us. Behavior of opb_epc is quite straightforward - after asserting chip select it waits max. 100us for ready signal. The new xps_epc does not wait longer than 1.27us (observed by oscilloscope) so that I never get valid data from my slow peripheral. Does anyone observed such a behavior of xps_epc? Is there a solution? Might be this problem related to plb instead of xps_epc itself? Thanks for your suggestions, JanArticle: 128559
I'm trying to understand the intricacies of implementing a ROM in an FPGA. I've searched around and come up with some useful tidbits, but I was hoping someone here could clear up a few issues with doing it "right" for those looking to learn. I would greatly appreciate any comments on the "correctness" of the following (using VHDL): - There seem to be two common ways to do the implementation: one is to create an array and essentially index into it using a mux, the other seems to involve generating RAM with predefined values and then defining it as read-only. The latter seems to be preferred for large LUTs (why?). -- On that note, is there a preferred template for doing the latter? I know what a RAM template looks like, how does one go about forcing it to predefined values and setting it to read only? (or is it just a matter of directing the RAM input/enable ports nowhere) -- Also, I notice Altera has a ROM megafunction, am I restricted (at least in terms of ease of creation) to the altera megafunction or is it relatively easy to roll my own RAM based ROM? - Are there any particular considerations if I am looking for a dual ported ROM? (except for the fact that the megafunction doesn't seem to support dual ports) - What about initialization? Right now I have a Matlab file that spits out text that is formatted such that I can cut and paste. Is there an easier way with the VHDL file read functions, that still remains synthesizable? Any considerations in this regard for RAM based versus mux based? For the curious, I'm trying my hand at direct digital synthesis: this is a 1/2 wave LUT (the other half is just the negative of the first, done on the fly, I haven't tried to reduce this to 1/4 yet). The dual ports stem from the need to access the sine and cos portion (phase and phase-(1/4 wave length) index). I realize this topic roughly comes up in one form or another every now and then, but I am trying to put the knowledge in one place and figure out how to do it "right" for the sake of learning. Thanks, ChrisArticle: 128560
I am thinking of buying (or upgrading) my PC for an FPGA project. At the moment I am using a windows laptop for synthesis and P&R runs. I use a Linux PC for simulation runs. Ideally I would like to move everything onto a linux PC. I have not got to the stage of debugging the design. I would say I need a PC with lots of physical memory. A parallel port (probably via a PCI interface) parallel cable III (probably bought with a starter kit) Any other interface ports that I need? At a pinch I can probably use wine. I have no plans to use EDK. If there is anything that I have missed then please tell me. I'd hate to buy something and then find out "oh you need ..." . Thanks very much Andy.Article: 128561
On 30 Jan, 20:58, Andy Botterill <a...@plymouth2.demon.co.uk> wrote: > I am thinking of buying (or upgrading) my PC for an FPGA project. > > At the moment I am using a windows laptop for synthesis and P&R runs. I > use a Linux PC for simulation runs. > > Ideally I would like to move everything onto a linux PC. I have not got > to the stage of debugging the design. > > I would say I need a PC with lots of physical memory. > A parallel port (probably via a PCI interface) > parallel cable III (probably bought with a starter kit) > > Any other interface ports that I need? > > At a pinch I can probably use wine. > > I have no plans to use EDK. > > If there is anything that I have missed then please tell me. I'd hate to > buy something and then find out "oh you need ..." . The Synthesis/Place/Route process seem to be equivalent to traversing a *large* node tree repeatedly which will trash any cache. Thus you should look for something that have a really fast memory bus and a really large L2 cache >1MB primarly. Going from 32bit to 64bit seem to increase performance by 20% according to another poster. (is different ISE versions faster/slower?). Intel Core2 seems to be 1,69 times faster than AMD64 X2. I assume this is related to L2 cache and memory *bus* speed. http://www.polybus.com/linux_hardware/index.htm Under linux you can figure out how much memory you really need by checking how much swap that is used. You can get faster (3x?) programming via USB rather than PCI-parallell port. However the last alternative "just works". Check linux drivers! Xilinx Platform USB can be used via a free program that will reflash the cpld (?). The best resource for fpga-jtag-linux is to search forums and the web. Don't count at all on vendors. http://www.xilinx.com/support/programr/jtag_cable.pdf http://www.science-and-technology.nl/research/jolt/ http://sourceforge.net/ + xc3sprog http://www.rmdir.de/~michael/xilinx/ http://inisyn.org/src/xup/ http://sourceforge.net/projects/xilprg http://www.c3a.de/wiki/index.php/JTAG_Finder It's not problem to run ISE with linux-api module (linux.ko) under FreeBSD btw.Article: 128562
posedge52@yahoo.com wrote: ... > It's not problem to run ISE with linux-api module (linux.ko) under > FreeBSD btw. If you run on anything non-Redhat/Windows, be prepared to get the answer "Not a supported platform" all the time :-( for every problem you report/webcase you open, as unrelated to any distribution the problem can be. It takes persistance to get Xilinx first level support to realize the problem... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 128563
I have a custom board with a V4 LX60 and a XCF32P config prom. I can config the FPGA directly via JTAG, but I cannot program the prom. I hope someone can point out the stupid mistake I'm making. I am using ISE ver 8.1 and a parallel cable 4. The two devices (fpga and prom) are in a single JTAG chain, with the prom first in the chain. Impact finds the chain and identifies both parts.I can tell Impact to by-pass the prom and load the .bit file to the FPGA; this works fine. However, if I tell Impact to generate a .mcs file and try to download that to the prom (bypassing the fpga), it starts the process, gets to 1% on the progress bar, then stalls.The TCLK line briefly shows some activity, then sits low. Eventually Impact gives an error message that the operation timed out. The prom does get partially programmed, and the data is correct up to the point it just stops (remaining bytes are 0xFF). The correct portion varies, three trials yielded 5K, 15K and 53K bytes of correct data. The JTAG connector is 1.5 inch from the prom. Readback from prom yields consistent results, and transferring .bit file to FPGA works, so I believe the hardware is good. Does anyone have a suggestion as to what is broke? Thanks. SamArticle: 128564
On 31 Jan, 00:01, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de> wrote: > posedg...@yahoo.com wrote: > > > It's not problem to run ISE with linux-api module (linux.ko) under FreeBSD btw. > > If you run on anything non-Redhat/Windows, be prepared to get the answer > "Not a supported platform" all the time :-( > for every problem you report/webcase you open, as unrelated to any > distribution the problem can be. It takes persistance to get Xilinx > first level support to realize the problem... So far I have solved problems without help from Xilinx. And should it be needed one can always employ helpdesk engineering :)Article: 128565
sam catalpatechnology com schrieb: > Does anyone have a suggestion as to what is broke? Thanks. If not a software bug ist looks like a partially broken PROM. Regards FalkArticle: 128566
Chris Maryan wrote: > Also, I notice Altera has a ROM megafunction, am I restricted (at least > in terms of ease of creation) to the altera megafunction or is it > relatively easy to roll my own RAM based ROM? Most FPGAs have internal RAM blocks for the specific purpose of implementations of memory-based constructs such as roms, rams, fifos etc. Using these RAM blocks as intended obviously gives best resource allocation usage and performance, not to mention build times. You can roll your own, yes, however vendor-specific synthesis tools will often infer implementations based on these RAM blocks, so you end up with the same result. The altera megafunctions are simply gui tools that produce wrappers around the various entities for the device resources. For example, I took the VHDL output of a megafunction for a dual-port RAM and added generics to allow me to instantiate dual-port RAMs of any width/depth using my modified wrapper, negating the need to generate a plethora of megawizard objects. FWIW you can also instruct the megawizard explicitly to implement the memory in logic (LUT) or RAM blocks if you so desire. IIRC the default setting is AUTO, where it chooses for you. > - Are there any particular considerations if I am looking for a dual > ported ROM? (except for the fact that the megafunction doesn't seem to > support dual ports) - What about initialization? Right now I have a > Matlab file that spits out text that is formatted such that I can cut > and paste. There are certainly dual-port megafunctions for rom & ram, so I'm not sure why you can't find them? As for initialisation, by far the best and most flexible way I've found is to use intel .hex file formats. They have the advantage that they're easy to produce from other sources, and the same file will work for both synthesis and simulation (eg ModelSim). IMHO, don't touch .MIF files. > For the curious, I'm trying my hand at direct digital synthesis: this > is a 1/2 wave LUT (the other half is just the negative of the first, > done on the fly, I haven't tried to reduce this to 1/4 yet). The dual > ports stem from the need to access the sine and cos portion (phase and > phase-(1/4 wave length) index). On an Altera-based platform, I'd still use the megawizard (Memory Compiler->ROM: 2-PORT). If you're curious, look at the Verilog/VHDL output and you can see how it thinly wraps an altsyncram resource. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 128567
Hi all, I am sorry if this problem has been answered but I cannot find much help from the archive. I am using a Spartan3 starter board to interface with a Micron CMOS Image sensor (MT9T001), and is confused with the output data from the sensor. It outputs 10-bit pixel datum in each pixel clock, but I am wondering what is the use of the last 2 bits? From my understanding, each pixel datum is of 0~255 value (2-to-power-8). Thanks! NickArticle: 128568
Chris Maryan wrote:
> -- On that note, is there a preferred template for doing the latter? I
> know what a RAM template looks like, how does one go about forcing it
> to predefined values and setting it to read only? (or is it just a
> matter of directing the RAM input/enable ports nowhere)
See the ROM example here:
http://home.comcast.net/~mike_treseler/
-- Mike Treseler
Article: 128569Hello group, Recently I have started to learn NIOS. I will appreciate it if somebody knows any good online resource or book that I can use. Thanks, AmitArticle: 128570
On Jan 31, 8:08 am, Nick <tk...@cuhk.edu.hk> wrote: > Hi all, > > I am sorry if this problem has been answered but I cannot find much help > from the archive. > > I am using a Spartan3 starter board to interface with a Micron CMOS > Image sensor (MT9T001), and is confused with the output data from the > sensor. > > It outputs 10-bit pixel datum in each pixel clock, but I am wondering > what is the use of the last 2 bits? > > From my understanding, each pixel datum is of 0~255 value (2-to-power-8). > > Thanks! > > Nick Nick, Try to search for Camera Link Protocol on the web and you will find answers to your question. Such topics have already been discussed on this forum as well. Hope this helps /MHArticle: 128571
I suggest also considering transceiver speed, jitter and signal integrity. Stratix II GX FPGAs provide a production qualified transceiver speed of 6.375 Gbps which isn't addressed by V5 LXT. Dave Greenfield Altera MarketingArticle: 128572
MH, Thanks! I search that protocol as you suggested but Micron's CMOS image sensor seems not to be registered, and it is not following that protocol. Nick mh wrote: > On Jan 31, 8:08 am, Nick <tk...@cuhk.edu.hk> wrote: >> Hi all, >> >> I am sorry if this problem has been answered but I cannot find much help >> from the archive. >> >> I am using a Spartan3 starter board to interface with a Micron CMOS >> Image sensor (MT9T001), and is confused with the output data from the >> sensor. >> >> It outputs 10-bit pixel datum in each pixel clock, but I am wondering >> what is the use of the last 2 bits? >> >> From my understanding, each pixel datum is of 0~255 value (2-to-power-8). >> >> Thanks! >> >> Nick > > > Nick, > Try to search for Camera Link Protocol on the web and you will find > answers to your question. Such topics have already been discussed on > this forum as well. > > Hope this helps > > /MHArticle: 128573
On 30 Jan., 20:47, Chris Maryan <kmar...@gmail.com> wrote: > - There seem to be two common ways to do the implementation: one is to > create an array and essentially index into it using a mux, the other > seems to involve generating RAM with predefined values and then > defining it as read-only. The latter seems to be preferred for large > LUTs (why?). It's a matter of size. A LUT with 4 bits input and one bit output may be within your technology only one gate. A ROM with 16 bit input and 16 bit output may be very easy (for example each output is depending on only one input) and therefore be no more than a few gates, or very complex. Each output bit might be a function of each input bit (here are again more simple functions possible (like AND of all 16 bit inputs) or complex functions (eg. AND of 14 inputs if the last two are "00" else OR of 14 inputs if the last two inputs are "11" else something completely different). A ROM based on RAM has allways a defined size (which might be degrees smaller than a LUT). bye ThomasArticle: 128574
posedge52@yahoo.com wrote: > On 30 Jan, 20:58, Andy Botterill <a...@plymouth2.demon.co.uk> wrote: > > The Synthesis/Place/Route process seem to be equivalent to traversing > a *large* node tree repeatedly which will trash any cache. Thus you > should look for something that have a really fast memory bus and a > really large L2 cache >1MB primarly. Going from 32bit to 64bit seem to > increase performance by 20% according to another poster. (is different > ISE versions faster/slower?). > Intel Core2 seems to be 1,69 times faster than AMD64 X2. I assume this > is related to L2 cache and memory *bus* speed. > http://www.polybus.com/linux_hardware/index.htm New motherboard with more L2 cache great. > > Under linux you can figure out how much memory you really need by > checking how much swap that is used. My Linux system has twice the memory of my windows system. Since I'm buying a new motherboard I'll take the opportunity to get more memory. > > You can get faster (3x?) programming via USB rather than PCI-parallell > port. However the last alternative "just works". Check linux drivers! > Xilinx Platform USB can be used via a free program that will reflash > the cpld (?). An extra USB port. I know I need some more. Added to the shopping list :-) . > The best resource for fpga-jtag-linux is to search forums and the web. > Don't count at all on vendors. > http://www.xilinx.com/support/programr/jtag_cable.pdf > http://www.science-and-technology.nl/research/jolt/ > http://sourceforge.net/ + xc3sprog > http://www.rmdir.de/~michael/xilinx/ > http://inisyn.org/src/xup/ > http://sourceforge.net/projects/xilprg > http://www.c3a.de/wiki/index.php/JTAG_Finder > > It's not problem to run ISE with linux-api module (linux.ko) under > FreeBSD btw. Will that work under fedora? Full GUI usage under Fedora would be really good. The ability to do synthesis and simulation on the same system would be great. Thanks Andy
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