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Hi, I'm trying to configure a Xilinx Spartan 3 s400 through JTAG in a new prototype but I'm getting some weird results back while programming it. I hope somebody with more experience can help me out. The fpga is the 2nd device in a chain of 3 devices, of which the third a XC95144XL is which can be programmed succesfully. I assume therefore that there are acceptable noise levels on the bus and bus speed (currently at about ~1.2MHz - depends a bit on how fast the programmer can handle incoming data but not faster than that) is Ok. When fetching the status register before any programming, I get; mask; 0x01FFFFFFFE 34 bits; 0x0260000000 The fpga being the second device, it actually clocks out 0x30000000 (and the first device seems to add a 1?) After programming I get; 34 bits; 0x0262000000 So it actually clocks out 0x31000000 So apparently (if I follow xapp452) the DCM are locked and DCI is matched (even though I haven't flashed in anything yet - the PROM onboard doesn't contain valid data - and don't have any DCI pins configured as actual DCI) and after a programming attempt GHIGH_B is deasserted, and there are _no_ CRC errors reported here. It doesn't, however, start up. DONE pin stays low (isn't connected to anything) as well as GTS_CFG and GWE etc, basically, the startup is stalled for some reason. So I decided to pick up the multimeter and start measuring; DONE stays low PROG_B stays high INIT_B goes high, than goes low again after programming This seems to indicate a CRC error after all? I've tried setting the BitGen option for unused IOB pins to pull-up (I'm not using the DONE pin as IO) but that still made DONE go low. So right now I have no idea how to continue in figuring out what the problem is or how to get the fpga working. I haven't tried disabling the CRC check completely yet. Any tips, hints, suggestions are very welcome. Cheers, Mike http://projectvga.orgArticle: 128701
> If the values are fixed, it's just a 16x1 ROM (for the single bit case), > or 16x32 ROM (32-bit wide case). XST will synthesize something appropriate > from any reasonable VHDL construct; see the examples in the XST manual. > Here's one way of doing the 32-bit wide case with a concurrent assignment Thanks for the feedback Eric, but the problem is that the content is not fix. So I cant use a rom as u suggested, I need something that reads the actual content out of a register an applies then the current valuesArticle: 128702
Dear Eli, Thanks for the great Tutorials of the Xilinx FPGA Editor. I want also know if there is everywhere a Documentation or a Howto about the FPGA Editor. It is a little bit a "wrong world" in there users create documentation and more, but thanks to all for sharing her experience and knowledge. Best regards, Daniel http://home.arcor.de/dkoethe/ eli.billauer@gmail.com schrieb: > Hello all, > > For all those who know that the Xilinx FPGA Editor exists, and maybe > that it's good for something, but are reluctant to try it out (for > obvious reasons): I've made a short video guide, which takes the > viewer around, and also demonstrates some very useful things you can > do with it. Overall, it's some 20 minutes of video (in three parts). > > Link: http://billauer.co.il/xilinx-fpga-editor-video-tutorial-guide.html > > It's maybe not easy to follow at first glance, but since all > operations are shown explicitly on screen capture, using the "pause" > button, and trying it out yourself, should be pretty straightforward. > > The tutorial goes through everything from opening an NCD file for > editing, viewing the design down to its small details, making some > changes, and finally saving the altered design for creation of a > bitfile. It also shows how to create probes (or: how to touch any > signal within your FPGA design with your oscilloscope probe in a > minute). > > Hope it turns out useful out there. > > EliArticle: 128703
Not to bad. But a suggestion. In several points in the videos you use a generic reference. example : "click this button to commit changes." You probably want to state the button name/action, or if that is impossible make the button you are talking about impossible to miss. example...Use your video editor and circle the button or draw an arrow to it. The cursor is easily lost. Using the cursor for pointing can cause confusion. I shall have to try pulling nets out to my logic analyzer. Could save me the time it would take to learn chipscope. <eli.billauer@gmail.com> wrote in message news:27e66afe-5cab-41d3-bfc4-336012660952@u10g2000prn.googlegroups.com... > Hello all, > > For all those who know that the Xilinx FPGA Editor exists, and maybe > that it's good for something, but are reluctant to try it out (for > obvious reasons): I've made a short video guide, which takes the > viewer around, and also demonstrates some very useful things you can > do with it. Overall, it's some 20 minutes of video (in three parts). > > Link: http://billauer.co.il/xilinx-fpga-editor-video-tutorial-guide.html > > It's maybe not easy to follow at first glance, but since all > operations are shown explicitly on screen capture, using the "pause" > button, and trying it out yourself, should be pretty straightforward. > > The tutorial goes through everything from opening an NCD file for > editing, viewing the design down to its small details, making some > changes, and finally saving the altered design for creation of a > bitfile. It also shows how to create probes (or: how to touch any > signal within your FPGA design with your oscilloscope probe in a > minute). > > Hope it turns out useful out there. > > EliArticle: 128704
Michael Meeuwisse <mickeymeeuw@nospamplease_thesearchcompanywithcolorfulletters'emailservice.com> wrote: >I'm trying to configure a Xilinx Spartan 3 s400 through JTAG in a new >prototype but I'm getting some weird results back while programming it. >I hope somebody with more experience can help me out. >The fpga is the 2nd device in a chain of 3 devices, of which the third a >XC95144XL is which can be programmed succesfully. I assume therefore >that there are acceptable noise levels on the bus and bus speed >(currently at about ~1.2MHz - depends a bit on how fast the programmer >can handle incoming data but not faster than that) is Ok. * Check power for any dips or transients. * Connect directly with a parallell port jtag adapter. Like this: http://www.xilinx.com/support/programr/jtag_cable.pdf (And only try the USB approch once it confirmed to work) * Lower the clocking frequency, try 50 kHz. * Double check all pins related to configuration (DONE, M0,M1,M2, INIT_B, CCLK, etc) * You could connect pins to the fpga DIN etc.. back to your PC to verify your fpga actually get the data you expect.Article: 128705
Klaus Mayer <KMayer@hotmail.com> writes: > I have a simple question, whats the best way of designing a lookup > table which is 16 bit wide in VHDL and for sythesis. It receives 4 > input bits and depending of the values 1 bit will be selected for the > output. As I have a 32 bit architecture, this kind of lookup table > should have 32 instances in parallel. If the values are fixed, it's just a 16x1 ROM (for the single bit case), or 16x32 ROM (32-bit wide case). XST will synthesize something appropriate from any reasonable VHDL construct; see the examples in the XST manual. Here's one way of doing the 32-bit wide case with a concurrent assignment statement: signal select: std_logic_vector (3 downto 0); signal foo: std_logic_vector (31 downto 0); foo <= "01110111010101011000001110101011" when select = "0000" else "11001100001100111100110001010101" when select = "0001" else "00001111000011111111111100000000" when select = "0010" -- [...] else "00011100011100011100011100011100" when select = "1110" else "10011100001111100000011111110000"; -- when select = "1111" (I haven't actually compiled this, so I've probably made one or more dumb mistakes in it, but you get the general idea.)Article: 128706
Eric Smith wrote: > foo <= "01110111010101011000001110101011" when select = "0000" IMHO, hex is _so_ much easier to read/maintain... foo <= X"776683AB" when select = "0000" Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 128707
Eric Smith wrote:
> Klaus Mayer <KMayer@hotmail.com> writes:
>> I have a simple question, whats the best way of designing a lookup
>> table which is 16 bit wide in VHDL and for sythesis. It receives 4
>> input bits and depending of the values 1 bit will be selected for the
>> output. As I have a 32 bit architecture, this kind of lookup table
>> should have 32 instances in parallel.
>
> If the values are fixed, it's just a 16x1 ROM (for the single bit case),
> or 16x32 ROM (32-bit wide case). XST will synthesize something appropriate
> from any reasonable VHDL construct; see the examples in the XST manual.
> Here's one way of doing the 32-bit wide case with a concurrent assignment
> statement:
>
>
> signal select: std_logic_vector (3 downto 0);
> signal foo: std_logic_vector (31 downto 0);
>
> foo <= "01110111010101011000001110101011" when select = "0000"
> else "11001100001100111100110001010101" when select = "0001"
> else "00001111000011111111111100000000" when select = "0010"
> -- [...]
> else "00011100011100011100011100011100" when select = "1110"
> else "10011100001111100000011111110000"; -- when select = "1111"
>
>
> (I haven't actually compiled this, so I've probably made one or more
> dumb mistakes in it, but you get the general idea.)
>
Personally I prefer to use case statements for constructs like this to
avoid any accidental priority encoding by the synthesis tool.
signal sel: std_logic_vector (3 downto 0);
signal foo: std_logic_vector (31 downto 0);
process (sel)
case sel is
when "0000" foo <= "01110111010101011000001110101011" ;
when "0001" foo <= "11001100001100111100110001010101" ;
when "0010" foo <= "00001111000011111111111100000000" ;
when ....
when "1110" foo <= "00011100011100011100011100011100" ;
when "1111" foo <= "10011100001111100000011111110000" ;
end case;
end process;
All things being equal both should generate identical results.
Ed McGettigan
--
Xilinx Inc.
Article: 128708
Mark McDougall <markm@vl.com.au> writes:
> IMHO, hex is _so_ much easier to read/maintain...
Except when designing a 7-segment decoder ;-)
always @ (ibcd)
begin
case (ibcd) // abcdefg
0 : oseg = 7'b1111110;
1 : oseg = 7'b0110000;
2 : oseg = 7'b1101101;
3 : oseg = 7'b1111001;
4 : oseg = 7'b0110011;
5 : oseg = 7'b1011011;
6 : oseg = 7'b1011111;
7 : oseg = 7'b1110000;
8 : oseg = 7'b1111111;
9 : oseg = 7'b1111011;
default : oseg = 0;
endcase
Article: 128709
Ed McGettigan <ed.mcgettigan@xilinx.com> writes:
> Personally I prefer to use case statements for constructs like this to
> avoid any accidental priority encoding by the synthesis tool.
[...]
> process (sel)
> case sel is
> when "0000" foo <= "01110111010101011000001110101011" ;
> when "0001" foo <= "11001100001100111100110001010101" ;
> when "0010" foo <= "00001111000011111111111100000000" ;
> when ....
> when "1110" foo <= "00011100011100011100011100011100" ;
> when "1111" foo <= "10011100001111100000011111110000" ;
> end case;
> end process;
That's fine for synthesis, but since the type is std_logic_vector, many
simulators will complain that you've left a lot of alternatives unspecified.
I suppose adding
when others => foo <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX" ;
would solve that.
Article: 128710Klaus Mayer <KMayer@yahoo.com> writes: > Thanks for the feedback Eric, but the problem is that the content is > not fix. So I cant use a rom as u suggested, I need something that > reads the > actual content out of a register an applies then the current values So it's either a RAM, or a register with a mux. Here's a single-bit wide version of the register with mux. use IEEE.numeric_std; signal reg: std_logic_vector (15 downto 0); signal sel: std_logic_vector (3 downto 0); signal foo: std_logic; foo <= reg (unsigned (sel)); -- multiplexer [untested, probably has some typo or thinko] You're on your own as far as how to get data into reg. Depending on how you do that, this might or might not fit into a single LUT. EricArticle: 128711
Some designs have at least one "left-over" BlockRAM, where this design would fit very nicely. You would be using less than 4% of the BlockRAM, but that's still better than not using it at all... The dual-ported nature of the BlockRAM nicely decouples the writing from the reading. Peter Alfke, Xilinx Applications On Feb 4, 10:32=A0am, Klaus Mayer <KMa...@hotmail.com> wrote: > Hi > > I have a simple question, whats the best way of designing a lookup table > which is 16 bit wide in VHDL and for sythesis. It receives 4 input bits > and depending of the values 1 bit will be selected for the output. As I > have a 32 bit architecture, this kind of lookup table > should have 32 instances in parallel. So I wonder what is the best > option to implement this? I also need to configure these lookup tables > before using them. > > Is the following approach feasable? I have one register that is 16 bits > wide and which holds the value of my lookup table. Now I use 32 Muxes > and each receives the 16 bits that are stored in the lookup register. > Each mux has its own 4-input selection signal, which consists of > the corresponing bits of the registers, and outputs the the > corresponding bit. So I would need quite a lot of muxes, it is maybe > better to have 32 16-bit lookup tables in parallel and read there > directly the value out? > > Thanks for helpful tips!Article: 128712
Same here.. It is working fine for me too. You might want to remove the instalation and re-install the software.*CRINGE* "Arlet Ottens" <usenet+5@c-scape.nl> wrote in message news:47a5a30e$0$85789$e4fe514c@news.xs4all.nl... > pallavi wrote: >> Hello, >> I want to set up design environment for my new Spartan-3E FPGA starter >> kit. >> I have downloaded ISE WebPack 9.2 and the service pack 9.2i SP4. >> To my dismay, when I want to point to my target device at the start or >> later(Set Properties for project), the Family drop-down, doesnot show >> of all the things, Spartan-3E. >> > > I don't know what's wrong with your setup, but I'm using ISE WebPack > 9.2.04i, and it shows the Spartan-3E devices.Article: 128713
> I actually tried this command: > $ xmd -tcl genace.tcl -jprog -hw implementation/download.bit -board > ml310 -target mdm -elf timer_test/executable.elf -ace system.ace > > My software code is supposed to write something to hyperterminal > through RS232 port and I have in fact populated the local BRAMs with > the data and instructions of my software code and download.bit should > contain that information (I tried commands with and without -elf > timer_test/executable.elf). Did you try removing the "-target mdm" as well? If your program is in bram it shouldn't be necessary. > Firstly I don't know why it is so, secondly I know no more convenient > way to make sure that my design is actually loaded and working (the > only way I found convenient is to write something to the output)! You could try a very simple design in ISE that just flashes a led or something and make an ace file from that. That should at least tell you whether it is a problem with the systemAce or the microblaze. Also, re-reading your original post - you probably don't need the OPB SysAce controller unless you intend to write to the compact flash - it could be causing some conflict with the sysace chip if it's not set up properly. Cheers, DaveArticle: 128714
Hallo to everyone, I should develop a system which outputs a pwm signal into a filter to obtain a sine at 500 Hz which will command a class D amplifier. I was considering to use dds compiler to generate digital sine, then putting the output in a pwm generator, like the one seen in fpga4fun website. If I can't use a high frequency oscillator for fpga, because of the limit of class D amplifier, may I use an oscillator of 500kHz about? There are some troubles, in example with DCM? Many Thanks, MarcoArticle: 128715
Hi, > I'm trying to configure a Xilinx Spartan 3 s400 through JTAG in a new > prototype but I'm getting some weird results back while programming it. > I hope somebody with more experience can help me out. Try to switch the modepins to JTAG only. Do you use a PC3 clone? There seems to be some problems in certain impact versions with PC3 and S3 if the chip is not in JTAG only mode. best regards Thorsten Trenz -- www.trenz-electronic.deArticle: 128716
Hello, I have a problem with apparently no issue. I use a V5 and I have a problem with the data path delay of a net. This net is used everywhere in my design and particulary in fixed blocs. The fanout is reduced to the maximum and I put a maxdelay constraint on it. The syntesis options are configured for speed. Anybody have an idea to reduce this delay ? Tk.Article: 128717
Hi Goli, The synthesis tools currently run as a single threaded process, and therefore dual and quad core CPUs have a limited effect on performance. I run the tools on my dual core desktop and the main benefit of dual core for me is that I can perform other tasks while the tools are crunching away on one of the CPUs, on my previous single core machine it was pretty much unusable. Apart from having at least one fast CPU you will also benefit greatly from having a large amount of high bandwidth memory (<=2GB). Make sure it is dual channel and some high frequency DDR variant. I'm not sure what impact fast hard drives make, since (as far as i know) as long as you don't run out of memory that's where the number crunching is performed. I think this subject has been covered at least once on this forum. check out: http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/b0572dfbb3c9600c/2a0ca5da1013a7c0?hl=en&lnk=gst&q=pc+performance#2a0ca5da1013a7c0 HTH Rob On Feb 4, 10:23 am, Goli <tog...@gmail.com> wrote: > Hi, > > Our company is looking to buy some Linux servers for design > implementations of Virtex5. So I was wondering if there is any optimum > configuration that I can use to decrease my run time of the designs. > > -- > GoliArticle: 128718
Hello, does anyone have an answer to the following two issues on using leonardo: 1. How can I see the exact functionality of the the cells Leonardo produces in its RTL Schematic, after reading my input HDL files? e.g. After synthesizing my code I get an RTL schematic with some cells (that look like multiplexers) and that only give me the info that they are instances of an "select_3_3" entity from the library "OPERATORS", but I can't really tell what they do or find this library. 2. When I use the VHDL "block" statement, the synthesizer appears to completely neglect (in its RTL schematic) the blocks I asked for. It creates the same schematic it did before I entered the block- statements. Is there a way to make the synthesizer take into account block-statements? Thank you in advance guys! GeorgeArticle: 128719
>The synthesis tools currently run as a single threaded process, and >therefore dual and quad core CPUs have a limited effect on >performance. I run the tools on my dual core desktop and the main >benefit of dual core for me is that I can perform other tasks while >the tools are crunching away on one of the CPUs, on my previous single >core machine it was pretty much unusable. >Apart from having at least one fast CPU you will also benefit greatly >from having a large amount of high bandwidth memory (<=2GB). Make sure >it is dual channel and some high frequency DDR variant. >I'm not sure what impact fast hard drives make, since (as far as i >know) as long as you don't run out of memory that's where the number >crunching is performed. The factors seems to look like this: * Don't bother with more than one core. * L2 cache is really good (L1 doesn't hurt). * Fast memory bus (FSB speed). * Fast dram chips (DDR2 >600 MHz etc). * 64 bit over 32bit. * CPU frequency. So you should get fast memory primarly, and secondarly look at cpu frequency.Article: 128720
Hi all, I am currently building a Digital Down Converter on Xilinx System Generator 9.1 platform which unfortunately overshot resources provided by mt target Virtex 4 chip by 400%. Is there any optimization way to shrink it down.?Article: 128721
maverick wrote: > Hi, > i need to know is it possible to readback and verify the loaded > configuration in the FPGA after the GSR is deasserted and the FPGA is > up and running with the loaded configuration? I am suspecting that due > to power requirement of my application, the FPGA loses its > configuration when the current demand increases ( HDD is connected to > the FPGA board, when the FPGA talks to the HDD through SATA > controller, the current goes up from .8 Amp to 1.7 Amps)and the FPGA > stops working in the expected manner. > > Any ideas......... > > Farhan > > My guess would be low frequency noise on your core or I/O supply, which can be quite hard to see on a 'scope. Try some very large low ESR capacitors on the suspect rails to see if that improves matters. As someone else said, the easiest way to verify is using a cable and verifying the bitstream. Dunstan ByteSnap Design Ltd, Web: www.bytesnap.co.ukArticle: 128722
On Feb 5, 3:02 am, "Marco T." <marcotos...@gmail.com> wrote: > Hallo to everyone, > I should develop a system which outputs a pwm signal into a filter to > obtain a sine at 500 Hz which will command a class D amplifier. > > I was considering to use dds compiler to generate digital sine, then > putting the output in a pwm generator, like the one seen in fpga4fun > website. > > If I can't use a high frequency oscillator for fpga, because of the > limit of class D amplifier, may I use an oscillator of 500kHz about? > > There are some troubles, in example with DCM? > > Many Thanks, > Marco Generating a "digital sine wave" requires a clock frequency higher than the output waveform. The clock oscillator for the FPGA can be at many MHz, allowing the sine wave to have many samples per waveform period. This is how you get a smooth wave without resorting to a very tight low-pass filter on the output. You can also create the PWM waveform inside the FPGA, which would remove your analog filtering requirements on the sine wave, but would require an even higher clock frequency to achieve a reasonable duty cycle resolution. The frequency limit of the class D amplifier is only on the output frequency of the PWM, not the oversampling clock used to generate the waveform. Regards, GaborArticle: 128723
Marco T. wrote: > Hallo to everyone, > I should develop a system which outputs a pwm signal into a filter to > obtain a sine at 500 Hz which will command a class D amplifier. > > I was considering to use dds compiler to generate digital sine, then > putting the output in a pwm generator, like the one seen in fpga4fun > website. > > If I can't use a high frequency oscillator for fpga, because of the > limit of class D amplifier, may I use an oscillator of 500kHz about? > > There are some troubles, in example with DCM? > > Many Thanks, > Marco > Hi Marco, You are right that DCMs have minimum clock freq restrictions (eg 24MHz in V5), but not sure why you want to use a DCM. You are not trying to phase lock to the input clock source or multiply it up so you could just use the low skew clock resources in your FPGA to pipe the clock around. You could use standard counter (eg a LFSR) to divide down your clock. Regards Dunstan Power ByteSnap Design Ltd, Web: www.bytesnap.co.ukArticle: 128724
On Feb 5, 8:17 am, hilo_p...@hotmail.com wrote: > Hi all, > > I am currently building a Digital Down Converter on Xilinx System > Generator 9.1 platform which unfortunately overshot resources provided > by mt target Virtex 4 chip by 400%. Is there any optimization way to > shrink it down.? It's unlikely that any back-end "pushbutton" optimizations will reduce your final size by a factor of 4. If it is possible to reduce your size, you'll need to do the tweaking in the System Generator. Make sure you aren't over- specifying the speed requirements. Sometimes you can gain a lot of area using time-multiplexing to share resources. Not knowing more details of your design it's hard to say exactly how to accomplish this. HTH, Gabor
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