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On 23 Gen, 10:14, Arlet Ottens <usene...@c-scape.nl> wrote: > Marco T. wrote: > > I should generate a pwm sinusoidal signal of a frequency lower than > > 500 Hz. > > > I have seen DDS Compiler into Coregen, but it seems useful to drive a > > DAC. > > > My aim instead is to output a pwm signal. > > > Any suggestion? > > Hook up the output data from the DDS to a separate PWM module. DDS has an output width >=1, a pwm module can have an input width >= 1 ? I was considering pwm as a counter and a comparator, there are other kind of implementation? Thanks MarcoArticle: 128376
"Marco T." <marcotoschi@gmail.com> wrote in message news:470c593b-9e38-4fed-854b-ae831fb0326d@f47g2000hsd.googlegroups.com... > > I was considering pwm as a counter and a comparator, there are other > kind of implementation? > Hi Marco, Google pwm dac fpga HTH., Syms.Article: 128377
Marco T. wrote: > On 23 Gen, 10:14, Arlet Ottens <usene...@c-scape.nl> wrote: >> Marco T. wrote: >>> I should generate a pwm sinusoidal signal of a frequency lower than >>> 500 Hz. >>> I have seen DDS Compiler into Coregen, but it seems useful to drive a >>> DAC. >>> My aim instead is to output a pwm signal. >>> Any suggestion? >> Hook up the output data from the DDS to a separate PWM module. > > > DDS has an output width >=1, a pwm module can have an input width >= > 1 ? > > I was considering pwm as a counter and a comparator, there are other > kind of implementation? DDS has output width N, so you make an N bit counter and N bit comparator. As the counter increments, you compare counter with DDS output. If DDS > counter, PWM output is 1, otherwise 0. Alternatively, you could use something like this: http://www.fpga4fun.com/PWM_DAC.htmlArticle: 128378
Hi, thanks for answer.
> Hi Peter,
>
> you must have missed something. I am using ISE/EDK9.2 on Linux. The Uart
> Lite is doing fine. Try to import the EDK project from Win (ISE 9.1) into
> your Linux (ISE 9.2) and see what happens.
>
> -Markus
That is defently possible, because I'm a EDK newbe. So this is my
discription of what I'm doing:
- first i'm using a BSB wizard to create a project with this options:
- board: S3E Starter Kit
- MB@50MHz, 8KB mem, H/W Debug component
- IO interfaces: onlu UART Lite
- with Configure Memory Test Application option
- everythig else is default
- next is "Generate Netlist"
- "Generate Bitstream"
- "Generate Libraries and BSPs"
- "Update Bitstream"
- and last is "Download Bitstream"
Article: 128379
Ok, I would try to explain as better as I can.
This is my block design:
Input Block ====> FIFO input ==> Any Algorithm => FIFO
output => Output Block
As you could see, the FPGA (a Virtex IIPro) has two inputs/outputs
ports. I use one of the for the input, and another one for the output.
The ports intarfaces are implemented as Input Block and Output block,
and this works fine. Each of them is conected with a FIFO.
So the system receives a certain number of packets, then it process
them and finally it retransmits them. That is:
Receive 1 2 3 4 5 6 7 8 9 from a DSP connected by a 32 bit bus.
Process (for example *2): 2 4 6 8 10 12 14 16 18
Returns 2 4 6 8 10 12 14 16 18 to the DSP.
Every block works fine with the exception of the FIFO output block.
I have tried the next designs for this block:
- First of all I probed with the same design as Input FIFO, but the
DSP didn't receive back any packet. I suppose I was not able to
resolve delay problems in clock synchronization (this is what I call
"design fails", that is, DSP didn't receive back any processed
packet).
- For this reason I decide to probe a LIFO design in which I use
the complete size of the LIFO (64 positions of 32 bits). Then I only
have to read from position 0 (that is the reason why I need to use Mod
operator).
This is the code for this block.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
entity simpleFIFO is
generic (
bits : integer := 32; -- # of bits per word
words : integer := 64); -- # words in memory
port (
reset : in std_logic;
clk : in std_logic;
wr_en : in std_logic;
rd_en : in std_logic;
data_in : in std_logic_vector(bits-1 downto 0);
data_out : out std_logic_vector(bits-1 downto 0);
fifo_full: out std_logic;
fifo_empty: out std_logic;
debug : out integer range 0 to words-1);
end simpleFIFO;
architecture a of simpleFIFO is
type vector_array is array (0 to words-1) of std_logic_vector(bits-1
downto 0);
signal memory : vector_array;
begin
process(clk, reset, wr_en, rd_en)
variable addr : integer range 0 to words-1:=0;
variable fifo_empty_v : std_logic;
variable fifo_full_v : std_logic;
begin
if reset = '1' then
fifo_empty_v := '0';
fifo_full_v := '0';
addr := 0;
else
if(clk'event and clk = '1') then
if addr = words+1 then
fifo_full_v := '1';
else
fifo_full_v := '0';
end if;
if(wr_en = '1' and fifo_full_v = '0') then
memory(addr) <= data_in;
addr := addr + 1;
end if;
if(rd_en = '1') then
addr := (addr - 1);
THIS WORKS FINE BUT I RECEIVE PACKETS IN ORDER INVERSE SO I JUST ERASE
addr:=addr-1 AND PUT addr:=(addr+1)mod(words)
end if;
if (addr-1) = 0 then
fifo_empty_v := '1';
else
fifo_empty_v := '0';
end if;
end if;
end if;
debug <= addr;
fifo_empty <= fifo_empty_v;
fifo_full <= fifo_full_v;
data_out <= memory(addr);
end process;
end a;
Regards
From pcw@www.karpy.com Wed Jan 23 08:48:36 2008
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From: Peter Wallace <pcw@www.karpy.com>
Subject: Re: Pwm Sine Generation
Date: Wed, 23 Jan 2008 08:48:36 -0800
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On Wed, 23 Jan 2008 16:51:33 +0100, Arlet Ottens wrote:
> Marco T. wrote:
>> On 23 Gen, 10:14, Arlet Ottens <usene...@c-scape.nl> wrote:
>>> Marco T. wrote:
>>>> I should generate a pwm sinusoidal signal of a frequency lower than
>>>> 500 Hz.
>>>> I have seen DDS Compiler into Coregen, but it seems useful to drive a
>>>> DAC.
>>>> My aim instead is to output a pwm signal.
>>>> Any suggestion?
>>> Hook up the output data from the DDS to a separate PWM module.
>>
>>
>> DDS has an output width >=1, a pwm module can have an input width >=
>> 1 ?
>>
>> I was considering pwm as a counter and a comparator, there are other
>> kind of implementation?
>
> DDS has output width N, so you make an N bit counter and N bit comparator.
>
> As the counter increments, you compare counter with DDS output. If DDS >
> counter, PWM output is 1, otherwise 0.
>
> Alternatively, you could use something like this:
>
> http://www.fpga4fun.com/PWM_DAC.html
Note that the example above generates PDM, _not_ PWM!
If you are intending to filter the FPGA outout signal to generate an
analog signal, PDM is more appropriate. If you are using the FPGA to
control power electronics, say for a motor drive, PWM is what you want.
Peter Wallace
Article: 128380On Wed, 23 Jan 2008 00:28:27 -0800 (PST), kislo <kislo02@student.sdu.dk> wrote: >well, im looking for a more theoretic answer for determing the >decoupling capacitors ... Why? JohnArticle: 128381
On Wed, 23 Jan 2008 07:18:19 -0800 (PST), "Marco T." <marcotoschi@gmail.com> wrote: >On 23 Gen, 10:14, Arlet Ottens <usene...@c-scape.nl> wrote: >> Marco T. wrote: >> > I should generate a pwm sinusoidal signal of a frequency lower than >> > 500 Hz. >> >> > I have seen DDS Compiler into Coregen, but it seems useful to drive a >> > DAC. >> >> > My aim instead is to output a pwm signal. >> >> > Any suggestion? >> >> Hook up the output data from the DDS to a separate PWM module. > > >DDS has an output width >=1, a pwm module can have an input width >= >1 ? > >I was considering pwm as a counter and a comparator, there are other >kind of implementation? > >Thanks >Marco Delta-sigma can be better than PWM, but at 500 Hz, either will be fine. JohnArticle: 128382
kislo wrote: > well, im looking for a more theoretic answer for determing the > decoupling capacitors ... if i switch 2A with a risetime of 0.5ns how > can i determine the current vs frequency or the impedance vs frequency > for the harmonics of 50Mhz switching frequency ... the impedance > requirement cant be constant over the complete frequency spectrum The Fourier transform of the (current) waveform will give you the current vs. frequency spectrum. The actual problem comes with the capacitor itself which, including its leads, will turn inductive as the frequency increases. -- glenArticle: 128383
On Jan 15, 10:20=A0am, FPGA <FPGA.unkn...@gmail.com> wrote: > On Jan 15, 3:58=A0am, "HT-Lab" <han...@ht-lab.com> wrote: > > > > > > > "FPGA" <FPGA.unkn...@gmail.com> wrote in message > > >news:113ff161-5e90-43f8-9c06-7da9ca92db65@s12g2000prg.googlegroups.com...= > > > > Hello all, > > > > I am trying to use some of the proposed functions by IEEE which are > > > still awaiting approval. > > >http://www.vhdl.org/vhdl-200x/vhdl-200x-ft/packages/float_pkg_c.vhdl > > > .. > > > > I am using ModelsimPE Student Edition 6.3c > > > I am not sure about the Student Edition but in the commercial PE version= (I > > use 6.3d) these packages are already supplied as standard. Have a look i= n > > your <your_mti_installation_dir>\vhdl_src\floatfixlib\ directory. > > > In my PE version they are compiled into floatfixlib: > > > Library floatfixlib; > > use floatfixlib.float_pkg.all; > > > signal A32,B32:float(8 downto -23); > > signal Y32 : float(8 downto -23); > > > A32 <=3D "01000000110100000000000000000000" ; -- 6.5 > > > B32 <=3D to_float(3.23, B32); -- size using B32 > > Y32 <=3D A32 + B32 ; > > > These are great libraries and very easy to use. The only problem is that= the > > waveform doesn't have an option to display them properly. > > > Hanswww.ht-lab.com > > > > Thanks- Hide quoted text - > > > - Show quoted text - > > I appreciate your help. I will try to use the floatfixlib library you > mentioned and see how it goes.- Hide quoted text - > > - Show quoted text - I am getting the following error when i try to make ieee_proposed library. Modelsim > vcom -work ieee_proposed float_pkg_c.vhd # Model Technology ModelSim PE Student Edition vcom 6.3c Compiler 2007.09 Sep 11 2007 # ** Error: (vcom-7) Failed to open design unit file "C:Modeltech_pe_edu_6.3cieee_proposed" in read mode. # No such file or directory. (errno =3D ENOENT) # C:/Modeltech_pe_edu_6.3c/win32pe_edu/vcom failed. I was successful is adding the math_utility_pkg.vhdl. I am however getting the same error while adding fixed_pkhg_c.vhd and float_pkg_c.vhd.Article: 128384
On Wed, 23 Jan 2008 14:48:30 -0800 (PST), FPGA <FPGA.unknown@gmail.com> wrote: >I am getting the following error when i try to make ieee_proposed >library. >Modelsim > vcom -work ieee_proposed float_pkg_c.vhd ># Model Technology ModelSim PE Student Edition vcom 6.3c Compiler >2007.09 Sep 11 2007 ># ** Error: (vcom-7) Failed to open design unit file >"C:Modeltech_pe_edu_6.3cieee_proposed" in read mode. ># No such file or directory. (errno = ENOENT) ># C:/Modeltech_pe_edu_6.3c/win32pe_edu/vcom failed. It seems likely that you've used the [vmap] command to map logical library name "ieee_proposed" to physical library directory "C:\Modeltech_pe_edu_6.3c\ieee_proposed" and the backslashes have been stripped by Tcl. Change the mapping to have forward slashes in the pathname, and all should be well. Also, to play safe, take a look in the currently-applicable "modelsim.ini" file and see if there are backslashes in the library-mapping pathnames there - if so, replace them with forward-slash. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 128385
On Jan 23, 5:54=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote: > On Wed, 23 Jan 2008 14:48:30 -0800 (PST), FPGA > > <FPGA.unkn...@gmail.com> wrote: > >I am getting the following error when i try to make ieee_proposed > >library. > >Modelsim > vcom -work ieee_proposed float_pkg_c.vhd > ># Model Technology ModelSim PE Student Edition vcom 6.3c Compiler > >2007.09 Sep 11 2007 > ># ** Error: (vcom-7) Failed to open design unit file > >"C:Modeltech_pe_edu_6.3cieee_proposed" in read mode. > ># No such file or directory. (errno =3D ENOENT) > ># C:/Modeltech_pe_edu_6.3c/win32pe_edu/vcom failed. > > It seems likely that you've used the [vmap] command > to map logical library name > =A0 "ieee_proposed" > to physical library directory > =A0 "C:\Modeltech_pe_edu_6.3c\ieee_proposed" > and the backslashes have been stripped by Tcl. > Change the mapping to have forward slashes in the > pathname, and all should be well. =A0Also, to play > safe, take a look in the currently-applicable > "modelsim.ini" file and see if there are backslashes > in the library-mapping pathnames there - if so, > replace them with forward-slash. > -- > Jonathan Bromley, Consultant > > DOULOS - Developing Design Know-how > VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services > > Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK > jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com > > The contents of this message may contain personal views which > are not the views of Doulos Ltd., unless specifically stated. I am still getting the same problem. Is there an alternate way of doing this? Can you please tell me the steps i need to follow to add the ieee_proposed library to Modelsim. ThanksArticle: 128386
On 23 Gen, 16:23, "Symon" <symon_bre...@hotmail.com> wrote: > "Marco T." <marcotos...@gmail.com> wrote in message > > news:470c593b-9e38-4fed-854b-ae831fb0326d@f47g2000hsd.googlegroups.com... > > > I was considering pwm as a counter and a comparator, there are other > > kind of implementation? > > Hi Marco, > Google > pwm dac fpga > HTH., Syms. I couldn't use a dac because I must avoid integrated circuit that permits too much complex feedback test. With an fpga like spartan3a I can perform jtag test and matrix configuration test with icap, but the most important I can make an output diagnosis of every step, in example output of dds, output of pwm, etc., so at the output of fpga I will put an LC filter to obtain a sine. In my application I should generate a signal modulated. I don't drive a motor, so I think PDM should be right for me. Many Thanks, MarcoArticle: 128387
Hi all, I want to choose an FPGA for a High speed appliction so which one to go for either for Xilinx or Altera. But i am vey much familiar with xilinx devices. And in the design the gate array will be ineracting with a host PC and two SRAM and with an HDD Inside the FPGA two FIFO are to be implemented. Later on the ASIC of this has to be obtained. so, kindly help me out in this regard Thanks in advance KiranArticle: 128388
On Wed, 23 Jan 2008 15:04:35 -0800 (PST),
FPGA <FPGA.unknown@gmail.com> wrote:
>Can you please tell me the steps i need to follow to add the
>ieee_proposed library to Modelsim.
Not precisely, because it depends on the location of things
in your setup. I would do something like this...
vlib c:/existing/directory/ieee_proposed_lib
vmap ieee_proposed c:/existing/directory/ieee_proposed_lib
vcom -work ieee_proposed c:/source/directory/float_pkg_c.vhd
Note also that any pathname containing spaces MUST be
enclosed in quotes "" or braces {} so that Tcl does not
interpret the spaces as word separators.
As usual, once you've done the "vlib" and "vmap" commands
you don't need to do them again; the library mapping will
be written into the local modelsim.ini file and will then
be used automatically whenever you run ModelSim in that
directory.
Ghastly thought: You're not actually running Modelsim in
its installation directory, are you? That's disastrous
because it has a read-only modelsim.ini file. Make sure
you've changed Modelsim's working directory to some place
where you have full read/write access.
HTH
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 128389Our Craignell webpage now has the schematics for the Issue2 40 pin version on it for all that have asked. Webpage is here http://www.enterpoint.co.uk/component_replacements/craignell.html. We now have a limited stock of the programming adaptors for the Craignell modules and the 500K gate Craignells are now in stock apart from the CR40-500EC which sold out very rapidly. We should have some more CR40-500EC in stock in a few weeks time. John Adair Enterpoint Ltd.Article: 128390
On 23 Jan., 17:57, John Larkin <jjlar...@highNOTlandTHIStechnologyPART.com> wrote: > On Wed, 23 Jan 2008 00:28:27 -0800 (PST), kislo > > <kisl...@student.sdu.dk> wrote: > >well, im looking for a more theoretic answer for determing the > >decoupling capacitors ... > > Why? > > John hehe well, since i have to document my work, it would be nice to have a proper analysis of the decoupling problem and not just use rules of thumps all the way .. alot of decoupling problems are easy solved with rules of thumps, but i think it would be nice to have a deeper understandin of the problem, which perhaps will lead to better results for my fpga board (and grades :o) .. but i see now that a deeper analysis of decoupling a fpga, from a theoritic approach, is very complex and will take to much of my time, which is already very limited for this project .. but thank you all for the answers ;)Article: 128391
kiransr.ckm@gmail.com wrote: > Hi all, > I want to choose an FPGA for a High speed appliction so which one to > go for either for Xilinx or Altera. > But i am vey much familiar with xilinx devices. > And in the design the gate array will be ineracting with a host PC and > two SRAM and with an HDD > Inside the FPGA two FIFO are to be implemented. > Later on the ASIC of this has to be obtained. > so, kindly help me out in this regard You don't specify what "High Speed" means to you, and even if you did there's no definite answer to your question, but let me say this: I recommend sticking with the architecture you're familiar with. Feature-wise there's not really much of a difference between both manufacturer's high-end parts. Even though Xilinx people will tell you their devices are better and Altera people will tell you their's are better, every marginal advantage you might have will be used up by having to learn a new architecture. So if you have know how on one technology, stick with it, unless you desperately need one of the special features of the other. HTH, Sean -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 128392
On Thu, 24 Jan 2008 08:09:15 -0800 (PST), kislo <kislo02@student.sdu.dk> wrote: >On 23 Jan., 17:57, John Larkin ><jjlar...@highNOTlandTHIStechnologyPART.com> wrote: >> On Wed, 23 Jan 2008 00:28:27 -0800 (PST), kislo >> >> <kisl...@student.sdu.dk> wrote: >> >well, im looking for a more theoretic answer for determing the >> >decoupling capacitors ... >> >> Why? >> >> John > >hehe well, since i have to document my work, it would be nice to have >a proper analysis of the decoupling problem and not just use rules of >thumps all the way .. alot of decoupling problems are easy solved with >rules of thumps, but i think it would be nice to have a deeper >understandin of the problem, which perhaps will lead to better results >for my fpga board (and grades :o) .. but i see now that a deeper >analysis of decoupling a fpga, from a theoritic approach, is very >complex and will take to much of my time, which is already very >limited for this project .. but thank you all for the answers ;) A worthwhile analysis would begin with knowing the current waveforms that the fpga pulls on its various supplies. That would then be dumped into the measured or estimated impedance of the bypassed power pours. Does such current waveform info exist for your part, in your application? If not, it's back to thumps. I wonder if anyone here has encountered a situation where an fpga failed because of inadequate bypassing. I've done dozens of Actel, Lattice, and Xilinx apps, including mixed-signal stuff and picosecond-jitter things, and I've never had a problem, even as I keep ratcheting down on bypassing. So I don't understand why so much is made over this issue. JohnArticle: 128393
> Try to import the EDK project from Win (ISE 9.1) into > your Linux (ISE 9.2) and see what happens. I did it and it's working, so where is the catch? There is 2 major defferences between 9.1 and 9.2: - new ver. of MB (7) - UART is using PLB instead of OPB so, maybe PLB is not properly implemented.Article: 128394
I'm investigating if the microblaze is an option for a project where physical space is extremely limited. Perhaps somebody can answer the following: 1.Is it possible to use the microblaze in a spartan3E 500? If yes, how much will it eat from this device? 2.if yes, is it possible to use the microblaze without any other memory chips (except one serial bootrom) and still running a standalone program which is not super large and does not need lots of memory? Thanks tacoArticle: 128395
I know Xilinx does not officially support anything other than RedHat Enterprise Linux, yet so many people have installed it on other versions such as Ubuntu, Gentoo, etc. I am trying to install it on openSuse 10.3 and am having a very difficult time. The instructions I have say to run ./setup in the root of the CD. It runs but very quickly and no error messages are given either. Cd into <EDKDVD>/bin/ lin and try to run ./setup there and it runs quickly and nothing happens either. Try running ./_setup and get errors about missing libraries, so I manually add the path to LD_LIBRARY_PATH. Then try again and I get errors about the XILINX environment variable not being set. I have no clue what to set this too and have tried many different places. Right now I just have it pointing to /opt/Xilinx/. Then finally the installer runs. Enter my registration ID and it says it is invalid. I think some variable or file is misplaced. Does anyone have any advice on what I should do? I am a student and have contacted my professor about this issue and detailed it with him but am not sure if he has opened a case with Xilinx support or if he will.Article: 128396
On Jan 24, 4:17=A0am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Wed, 23 Jan 2008 15:04:35 -0800 (PST),
>
> FPGA <FPGA.unkn...@gmail.com> wrote:
> >Can you please tell me the steps i need to follow to add the
> >ieee_proposed library to Modelsim.
>
> Not precisely, because it depends on the location of things
> in your setup. =A0I would do something like this...
>
> =A0 vlib c:/existing/directory/ieee_proposed_lib
> =A0 vmap ieee_proposed c:/existing/directory/ieee_proposed_lib
> =A0 vcom -work ieee_proposed c:/source/directory/float_pkg_c.vhd
>
> Note also that any pathname containing spaces MUST be
> enclosed in quotes "" or braces {} so that Tcl does not
> interpret the spaces as word separators.
>
> As usual, once you've done the "vlib" and "vmap" commands
> you don't need to do them again; the library mapping will
> be written into the local modelsim.ini file and will then
> be used automatically whenever you run ModelSim in that
> directory.
>
> Ghastly thought: You're not actually running Modelsim in
> its installation directory, are you? =A0That's disastrous
> because it has a read-only modelsim.ini file. =A0Make sure
> you've changed Modelsim's working directory to some place
> where you have full read/write access.
>
> HTH
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.
You are right. I was running Modelsim in the installation directory.
Thank you very much for pointing that.
Article: 128397Hello members, I would like to know if VHDL already has functions defined to generate Random Numbers. If not, which would be the best algorithm for generating random numbers for implementation on an FPGA. Thank youArticle: 128398
taco wrote: > I'm investigating if the microblaze is an option for a project where > physical space is extremely limited. Perhaps somebody can answer the > following: > 1.Is it possible to use the microblaze in a spartan3E 500? If yes, how much > will it eat from this device? > 2.if yes, is it possible to use the microblaze without any other memory > chips (except one serial bootrom) and still running a standalone program > which is not super large and does not need lots of memory? If you need a real small CPU, take a look at ftp://137.193.64.130/pub/mproz/mproz3_e.pdf Only a few dozen flip-flops and a few hundred gates.Article: 128399
Good luck with the random numbers, but if you want pseudo-random: http://en.wikipedia.org/wiki/LFSR. Xilinx also has an excellent document on LFSRs with polynomials up to about 1000 bits or so.
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