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Jon Elson <elson@wustl.edu> wrote: >sky465nm@trline4.org wrote: >> Jon Elson <elson@pico-systems.com> wrote: >> >>>I got a batch of "Xilinx" Spartan XCS30 FPGAs from a Chinese >>>seller, and am having problems with random failures at first >>>power up. Sometimes it is a stuck I/O pin, sometimes a failure >>>to configure. I first thought maybe we had an ESD problem, but >>>I'm now thinking these may be counterfeit. They have white ink >>>printed labels on the front, whereas other Xilinx chips have >>>laser-etched labels. Also, these Spartan chips don't have the >>>Spartan logo just below the Xilinx logo, like my other Xilinx >>>chips. Anyone have any comments on this? >> >> >> Photo.. ? >> >OK, where should I put the photos? Try this service: http://www.freeimagehosting.net/ (Max 3MB/picture)Article: 130451
Hi Kolja, >>> Also 15% speedup is the same as purchasing the CPU three months >>> later. > [... b]ut all these are minor cleanups when you consider the class of > algorithms involved. Sorry to use a cliche, but you have to walk before you can run! Our first parallel release (in 2006) improved runtimes by 5% or so, and we've since pushed that up to 20% and have many more improvements on the way. The big problem, of course, is that we're held back by Amdahl's law - if you perfectly parallelize 25% of your algorithm (eg get a 4x speedup on four processors), this will only make the overall algorithm about 20% faster. However, if you parallelize the second 25%, you get a 60% speedup, and the third 25% will get you to 130% (ie, a 2.3x speedup). We're clearly still in that first-25%-ish range, but we don't intend to stay there. As Paul mentioned, we've dramatically improved our serial runtimes as well, which gets a greater improvement than our parallel results to date. But it's unwise to rely solely on our ability to repeat this feat again and again. In addition, while it was recently true that processors were doubling in speed every 18 months or so, chip vendors now are choosing lower clock speeds and increasing the number of cores available instead. For example, when I compare the SPEC CINT2006 results for the second half of 2006 with the second half of 2007 (the most recent numbers I could find on spec.org), the best single- threaded score increased by only 9% and the average score by only 14%. Since our devices are now growing much faster than this, waiting for a new processor to reduce your runtimes isn't a good long-term solution anymore. In short, these are early days for parallel EDA and we're not at 4x speedups yet, but we're busy laying the groundwork for the many-core future to make sure we don't get left behind. Cheers, Adrian Ludwin AlteraArticle: 130452
"ni" <nbg2006@gmail.com> wrote in message news:1a0e6c96-03f8-4456-bd3d-7a5f1f60fde4@b1g2000hsg.googlegroups.com... >I wanted to perform a byte shifting of a 24bit vector . the resultant > vector is a 48 bit vector . the following is the functinality needed > > signal BV : std_logic_vector(23 downto 0); > signal BYTE_SEL : std_logic_Vector(1 downto 0); > signal BVOUT : std_logic_Vector(47 downto 0); > > method 1 > BVOUT <= x"000000" & BV when BYTE_SEL = "00" else > x"0000" & BV & x"00" when BYTE_SEL ="01" else > x"00" & BV & x"0000" when BYTE_SEL ="10" else > BV & x"000000"; > This will likely get implemented something like a 3 bit 'and for each bit (i.e. bit 0 out = bit 0 in when byte_sel=00) , so basically 1 logic cell per bit...not too bad. > > I would like to know if the above method 1 of the behavioural > statement is a good way of programming when I am implementing on the > FPGa Yes it is. > or should I implement it using a ROM where I store a multiplier > constant and use the byte_sel as an address to select it and then > multiply with the pipelined BV to generate the output. Now you're obscuring your real design intent in the hopes of improving either logic resource or performance (not sure which). Unless your targetted part has 32 bit hardware multipliers, the resulting implementation may consist of two smaller multipliers plus some logic to combine the outputs into the final result or some logic on the front end into the multiplier, a single multiplier and then some additional logic on the output side. Possibly a better approach would be to break it down into two independent 16 bit multipliers where one of the multipliers would end up multiplying by 0, the other by either 1 or 256. In any case, I'm guessing that any solution along those lines would probably have a hard time being better than the single level of logic per bit required for method 1. > Or is there any other better way to implement it other than the above > two methods. > Possibly. But the best way to explore implementation ideas is with synthesis software which allows you to implement the idea and get pretty immediate feedback via their RTL and technology map viewers as well as logic resource and timing performance so you can get a feel for which methods are 'better' than others for how you intend to use it. One important thing you've done is tried to see the problem from different perspectives. Method 1 is a view that is basically a 4>1 multiplexer view whereas method 2 views the problem from an arithmetic view. It got a bit convoluted by thinking of using a ROM lookup table when the multipliers are a fairly trivial function of the input byte_sel. If you have ISE, Quartus, Synplify, etc. try out your ideas and you'll get quicker turn around then the newsgroup approach. Kevin JenningsArticle: 130453
no reply? water9580@yahoo.com wrote: > The Linux lspci -xxx command can show my PCIE device header > space(0x00~0xFF). However,simultaneity,the Correctable Error and > Unsupported Request error from PCIE Capabilities device status > register are set. > > I run the PCI Express Configuration Testing program from PCISIG to > test configure space.The system is halt after click run all test.Reset > PC and report NMI error. > > why? > > My configuration: PCIEx1, 16bit customize GTP wrapper same as Endpoint > x1 IP.Article: 130454
water9580@yahoo.com wrote: > no reply? > > water9580@yahoo.com wrote: >> The Linux lspci -xxx command can show my PCIE device header >> space(0x00~0xFF). However,simultaneity,the Correctable Error and >> Unsupported Request error from PCIE Capabilities device status >> register are set. >> >> I run the PCI Express Configuration Testing program from PCISIG to >> test configure space.The system is halt after click run all test.Reset >> PC and report NMI error. >> >> why? >> >> My configuration: PCIEx1, 16bit customize GTP wrapper same as Endpoint >> x1 IP. Do you see anything unusual from your PCI Express protocol analyzer?Article: 130455
hai..all i am trying to make a particular snr (in dB ) awga (additive white guassian noise.) in vhdl. pls guide me to code it.. i generated the random number using F/F and exor gate, but not getting how to generate guassian noise. pls help meArticle: 130456
> > i) We want to make SOC designs used for image processing, path > > planning, motion control for our robots which need both processor and > > dedicated hardware. Since this type of design has not been used so far > > here, we are actually trying to introduce it and hence finding it > > difficult to select the best way. > > Once started it will continue with newer students every year. I am afraid that you may have to design a custom board for this application, I myself thought that I could try a Xilinx Virtex-4 (FX) device for such a research activity but had to design a custom board employing TI-tms320c64x processor with Xilinx Virtex-4 device to meet computational demands of parallel image processing applications. May be you find some off the shelf board with such horse power of computational capability. > > ii) We want to complete a project with a working robot that could > > track some colored object or some specific shaped object. Finding such > > object in a room. Even the basic 2-D template matching algorithms are computationally demanding, and the algorithms for ATR (automatic target recognition) are far more complex. > Looking at the Spartan-3A board it seems it could be better. I'm still > not clear about if we can use some softcore processor in this board's > FPGA. What about extra cost for the license (if required) to use, say, > microblaze. > Putting it in simpler way, we want to have an embedded platform where > we could use FPGA for designing hardwares like pwm generators, > quadrature phase decoders, display controllers, parallel algorithms > for image processing, and then we could use the processor present in > it to do planning, some AI and high level tasks. I recommend you to do more research and get a clear idea of algorithms that you want to implement. Try to calculate the number of multiplications, additions, square roots etc that may be needed per second. Only then you will have a good number of required computations and you can identify a target device. May be some FPGA from Virtex-4/5 meet your demands. Best of luck !!! /MHArticle: 130457
On 21 Mrz., 19:02, kkoorndyk <kris.koorn...@gmail.com> wrote:
> create_clock -name {clk_48M_p} -period 20.000 -waveform {0.000 10.000}
[..]
> set_max_delay 20.000 -from [all_inputs] -to [all_outputs]
I think these are synthesis constraints. Did you use them for layout,
too?
> Is there a good, clean way of partitioning the constraints for the two
> clock domains short of listing all of the different signals in each
> domain? Anybody have any other ideas?
I wouldn't use timing constraints for clock domain crossing, but
ensure a proper handling in the code.
Even if your clocks are alligned on input, you might have a big skew
caused by using different routing sources for the clock (Especially
when mixing hclk, clk and qclk in SX-A).
bye Thomas
Article: 130458I can not imagine that the server overload is such a real problem that Xilinx hasnt been able to solve it during the many years of repeated webserver problems. Getting the company website and downloads working reliable isnt magic. Its way less complicated the making FPGA's Sure probably there are just too many download requests of 10.1 but, but still it should be possible to get the servers managed ======== Error We cannot fullfill your request due to technical difficulties. Please try again later. Please do NOT click the back button. Please try again later, and email webmaster@xilinx.com if you receive this error repeatedly. ========Article: 130459
On 25 Mrz., 07:44, Antti <Antti.Luk...@googlemail.com> wrote: > I can not imagine that the server overload is such a real problem that > Xilinx hasnt been able to solve it during the many years of repeated > webserver problems. > > Getting the company website and downloads working reliable isnt magic. > Its way less complicated the making FPGA's > > Sure probably there are just too many download requests of 10.1 but, > but still it should be possible to get the servers managed > > ======== > Error > > We cannot fullfill your request due to technical difficulties. Please > try again later. > > Please do NOT click the back button. Please try again later, and email > webmas...@xilinx.com if you receive this error repeatedly. > > ======== !!!!!!!!!!!!!!!!!111 ISE 10.1 DOES NOT SUPPORT Virtex-5FXT ????? at least by the online information and "whats new in 10.1" for embedded design points to dead link really looks like Xilinx webmaster is on permanent maternity leave or something... AnttiArticle: 130460
Hi comp.arch.fpga, Wojciech,
I have figured out how to get jtagd working in Remote mode *with*
correct detection of part names ("071280DD" --> "EPM7128S").
Here's what you need to do:
0. If there's an already-running instance of jtagd, kill it:
killall jtagd
1. mkdir /etc/jtagd
2. Create /etc/jtagd/jtagd.conf using the following template. Use the
~/.jtagd.conf file, generated by jtagconfig, for inspiration,
particularly for the Device sections.
# /etc/jtagd/jtagd.conf
Password = "changeme";
Device0 {
Port = "/dev/parport0";
Type = "ByteBlasterII";
}
3. Provide the part name database to jtagd. For some reason, it looks
for it as /etc/jtagd/jtagd.pgm_parts when --user-start is *not*
specified. You can either make a symbolic link or copy it:
/etc/jtagd# ln -s $QUARTUS_HOME/linux/pgm_parts.txt jtagd.pgm_parts
4. Start jtagd manually, using only the --config switch:
$QUARTUS_HOME/bin/jtagd --config /etc/jtagd/jtagd.conf
At this point, jtagd will be listening on *:1309 and will accept
remote connections provided the password is correct. The parts will
also show up using their names instead of JTAG IDs only. I have
programmed a EPM7128S from Quartus II 5.0 Windows using this and it
worked well.
If you run into any trouble, add in the --foreground --debug switches.
Enjoy.
Catalin
Article: 130461On 25 Mrz., 07:54, Antti <Antti.Luk...@googlemail.com> wrote: > On 25 Mrz., 07:44, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > I can not imagine that the server overload is such a real problem that > > Xilinx hasnt been able to solve it during the many years of repeated > > webserver problems. > > > Getting the company website and downloads working reliable isnt magic. > > Its way less complicated the making FPGA's > > > Sure probably there are just too many download requests of 10.1 but, > > but still it should be possible to get the servers managed > > > ======== > > Error > > > We cannot fullfill your request due to technical difficulties. Please > > try again later. > > > Please do NOT click the back button. Please try again later, and email > > webmas...@xilinx.com if you receive this error repeatedly. > > > ======== > > !!!!!!!!!!!!!!!!!111 > > ISE 10.1 DOES NOT SUPPORT Virtex-5FXT ????? > > at least by the online information > > and "whats new in 10.1" for embedded design points to dead link > > really looks like Xilinx webmaster is on permanent maternity leave or > something... > > Antti well there are GOOD NEWS TOO, first time in history? has Xilinx managed to release ALL MAJOR version at the same time, that is EDK 10.1 CS 10.1 are all available!! and as new feature added to EDK: *Usability improvements as well as Simplified Installation and Registration process unfortunatly that new feature (added in 10.1) COMPLETLY prevents the download of any of the 10.1 tools!! only the standalone programming tools can be downloaded. so we can download xilinx programming tools only - as simple one file download of 916 MEGA BYTE only :) Antti has sent email to xilinx webmaster and is waiting responseArticle: 130462
On 25 Mrz., 08:54, Antti <Antti.Luk...@googlemail.com> wrote: > On 25 Mrz., 07:54, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > On 25 Mrz., 07:44, Antti <Antti.Luk...@googlemail.com> wrote: > > > > I can not imagine that the server overload is such a real problem that > > > Xilinx hasnt been able to solve it during the many years of repeated > > > webserver problems. > > > > Getting the company website and downloads working reliable isnt magic. > > > Its way less complicated the making FPGA's > > > > Sure probably there are just too many download requests of 10.1 but, > > > but still it should be possible to get the servers managed > > > > ======== > > > Error > > > > We cannot fullfill your request due to technical difficulties. Please > > > try again later. > > > > Please do NOT click the back button. Please try again later, and email > > > webmas...@xilinx.com if you receive this error repeatedly. > > > > ======== > > > !!!!!!!!!!!!!!!!!111 > > > ISE 10.1 DOES NOT SUPPORT Virtex-5FXT ????? > > > at least by the online information > > > and "whats new in 10.1" for embedded design points to dead link > > > really looks like Xilinx webmaster is on permanent maternity leave or > > something... > > > Antti > > well there are GOOD NEWS TOO, first time in history? has Xilinx > managed to > release ALL MAJOR version at the same time, that is EDK 10.1 CS 10.1 > are all available!! > > and as new feature added to EDK: > > *Usability improvements as well as Simplified Installation and > Registration process > > unfortunatly that new feature (added in 10.1) COMPLETLY prevents the > download of any of the 10.1 tools!! > > only the standalone programming tools can be downloaded. > > so we can download xilinx programming tools only - as simple one file > download of 916 MEGA BYTE only :) > > Antti > has sent email to xilinx webmaster and is waiting response ROTFL, now the Xilinx response has changed, trying to download WebPACK we get: ====== cut here, response from xilinx server === null null =================== !!! Antti, at least some good laugh this morning :)Article: 130463
David R Brooks wrote: > [snip] > But if you have long (ie 32 bit) words, that is 32 clocks for every > operation, just to optimise the (relatively few) accesses to the full > space of the SD card. Would it not be better to have, say 16 bit words, > and divide the SD into 64k pages. Most modern 32 Bit CPUs have the option to run variable length opcodes and they can use 16 bit opcodes for most common operations, and include some 32 bit ones for rarer instances. They do this for similar reasons : because widely parallel memory is NOT cheap, and Memory access can dominate CPU speeds. Parallel FLASH access speeds have somewhat saturated, and so wide-access schemes are used, but that excludes external bus uses. With Serial memory, 24 bits is another OpCode size candidate. (even 8 bits could be considered, as valid), and would certainly be natural candidate for RET and RETI for example. - why fetch 32 clocks just to find you have to go somewhere else anyway..., a SHORT RET could go someway to compensate for the slow re-address of serial memory. A handfull of conditional short-skip opcodes could be mapped onto 8 bits, to further speed those serial-optimise cases. The Mico8 has a core-opcode field of 5 bits (of the 18 bits), and then sometimes extends that 5 bits, with sub-codes. The v3.0 Mico8 uses a 6 bit core opcode on BRANCH and CALL, for 12 bits of Address, covers +/-2048 in the 18b opcode. 16/24 bit opcode versions of that, would map to +/-0.5KB, and +/- 128KB. -jgArticle: 130464
referringto@googlemail.com wrote: > On Mar 23, 10:36 pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> > wrote: > >>referrin...@googlemail.com wrote: >> >>>On Mar 19, 7:28 am, Antti <Antti.Luk...@googlemail.com> wrote: >>> >>>>I have been think and part time working towards a goal to make useable >>>>and useful serialized processor. The idea is that it should be >> >>(snip) >> >> >>>I wonder what the optimization target is? Size? >>>I am pretty sure that at some point the overhead of handling >> >> > a serial datapath exceeds the benefits. eg I would assume> that a 2 or 4 bit datapath does actually use fewer >> >> > resources than a 1 bit datapath. >> >>I suppose so for FPGA or other modern systems. > > > I would even go as far as saying that a 1 bit datapath does > not even represent the clock speed optimum. The clock speed > optimum is probably around 4-8 bits. Correct. The speed actually only needs to be faster than the memory :) The 4 bit-wide, SPI access Winbond part Antti referenced, would make a 4 bit datapath natural for most opcodes. Special cases like MUL and DIV may choose to go to 1 bit for a size/speed trade off. -jgArticle: 130465
I would suggest to use what I do: Use a circular addr counter on both sides, make a signal that will indicate that its 1/4 full and reclock that single signal to the other side (edge detecting to single clock), to indicate its safe to read 1/4 of the ramblock. To give a message back to the input clock domain, create a similar signal on the read side telling that 1/4 is used, telling input tocontinue to write 1/4 more data. You could be using 1/2 size partitions too, but quads (or even smaller portions) gives you some headroom to fill more memory while reading. If you partition the ram into too small partitions, the reclocking of a filled part will not work (you do not want to loose any of these signals). You can calculate the minimum partition by comparing the clocking ration of your domains, ensuring that every 1/n'th fill will be guaranteed to reclock.Article: 130466
Antti <Antti.Lukats@googlemail.com> wrote: > ROTFL, now the Xilinx response has changed, trying to download WebPACK > we get: > ====== cut here, response from xilinx server === > null > null > =================== > !!! > Antti, at least some good laugh this morning :) Antii, calm down.... Roling out a multi-hundred or even Gigabyte distribution is some heavy load for any server farm. And there is also some poroblem with the European-US transatlatic cable (http://www.heise.de/newsticker/Beschaedigtes-Unterseekabel-bremst-Internetverbindungen-in-die-USA--/meldung/105433) which cuts 30 GBit/s transfer capacity. Cheers -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 130467
On 25 Mrz., 10:54, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de> wrote: > Antti <Antti.Luk...@googlemail.com> wrote: > > ROTFL, now the Xilinx response has changed, trying to download WebPACK > > we get: > > ====== cut here, response from xilinx server === > > null > > null > > =================== > > !!! > > Antti, at least some good laugh this morning :) > > Antii, > > calm down.... > > Roling out a multi-hundred or even Gigabyte distribution is some heavy load > for any server farm. And there is also some poroblem with the European-US > transatlatic cable > (http://www.heise.de/newsticker/Beschaedigtes-Unterseekabel-bremst-Int...) > which cuts 30 GBit/s transfer capacity. > > Cheers > > -- > Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- well its not that... I just downloaded the "standalone programmer" 916MByte OK, so Xilinx servers have no issues with the bandwidth the problem is that the registration does not work. for that there is no bandwidth needed. just a webmaster who does what he is getting paid for. thats all that is needed. AnttiArticle: 130468
On 25 Mrz., 11:04, Antti <Antti.Luk...@googlemail.com> wrote: > On 25 Mrz., 10:54, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de> > wrote: > > > > > Antti <Antti.Luk...@googlemail.com> wrote: > > > ROTFL, now the Xilinx response has changed, trying to download WebPACK > > > we get: > > > ====== cut here, response from xilinx server === > > > null > > > null > > > =================== > > > !!! > > > Antti, at least some good laugh this morning :) > > > Antii, > > > calm down.... > > > Roling out a multi-hundred or even Gigabyte distribution is some heavy load > > for any server farm. And there is also some poroblem with the European-US > > transatlatic cable > > (http://www.heise.de/newsticker/Beschaedigtes-Unterseekabel-bremst-Int...) > > which cuts 30 GBit/s transfer capacity. > > > Cheers > > > -- > > Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de > > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- > > well its not that... > > I just downloaded the "standalone programmer" 916MByte OK, so Xilinx > servers have no issues with the bandwidth > the problem is that the registration does not work. for that there is > no bandwidth needed. > > just a webmaster who does what he is getting paid for. thats all that > is needed. > > Antti ah its all working now!! it only 6.7 GB download :) AnttiArticle: 130469
Frank Buss wrote: > referringto@googlemail.com wrote: > > > Maybe this is of interest, it recently found a new home: > > > > http://www.opencores.org/projects.cgi/web/mcpu/overview > > Nice small instruction set, but maybe too limitd, because even implementing > a shift operation (e.g. for implementing multiplication) would need > multiple instructions. And 64 bytes of data/code memory doesn't look very > useful. A shift left is nothing but an add. Just updated the documentation for the SPARTAN3E port of MPROZ with external RAM/ROM (in German): ftp://137.193.64.130/pub/mproz/mproz2a.pdf The version with internal RAM (in English): ftp://137.193.64.130/pub/mproz/mproz3_e.pdfArticle: 130470
Antti Release notes say only early access support currently for V5 FX. Full support coming in a service pack. John Adair Enterpoint Ltd. On 25 Mar, 06:54, Antti <Antti.Luk...@googlemail.com> wrote: > On 25 Mrz., 07:44, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > > > I can not imagine that the server overload is such a real problem that > > Xilinx hasnt been able to solve it during the many years of repeated > > webserver problems. > > > Getting the company website and downloads working reliable isnt magic. > > Its way less complicated the making FPGA's > > > Sure probably there are just too many download requests of 10.1 but, > > but still it should be possible to get the servers managed > > > ======== > > Error > > > We cannot fullfill your request due to technical difficulties. Please > > try again later. > > > Please do NOT click the back button. Please try again later, and email > > webmas...@xilinx.com if you receive this error repeatedly. > > > ======== > > !!!!!!!!!!!!!!!!!111 > > ISE 10.1 DOES NOT SUPPORT Virtex-5FXT ????? > > at least by the online information > > and "whats new in 10.1" for embedded design points to dead link > > really looks like Xilinx webmaster is on permanent maternity leave or > something... > > Antti- Hide quoted text - > > - Show quoted text -Article: 130471
On 25 Mrz., 11:29, John Adair <g...@enterpoint.co.uk> wrote: > Antti > > Release notes say only early access support currently for V5 FX. Full > support coming in a service pack. > > John Adair > Enterpoint Ltd. > hmm.. I missed that part, or maybe that wasnt online when i looked. the ISE 10.1 release info had NO V5-FXT listed at all. sure it would be only early access for now as the 5FXT still hasnt been announced officially AnttiArticle: 130472
Antti wrote: > On 25 Mrz., 11:04, Antti <Antti.Luk...@googlemail.com> wrote: >> On 25 Mrz., 10:54, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de> >> wrote: >> >> >> >>> Antti <Antti.Luk...@googlemail.com> wrote: >>>> ROTFL, now the Xilinx response has changed, trying to download >>>> WebPACK we get: >>>> ====== cut here, response from xilinx server === >>>> null >>>> null >>>> =================== >>>> !!! >>>> Antti, at least some good laugh this morning :) >> >>> Antii, >> >>> calm down.... >> >>> Roling out a multi-hundred or even Gigabyte distribution is some >>> heavy load for any server farm. And there is also some poroblem >>> with the European-US transatlatic cable >>> (http://www.heise.de/newsticker/Beschaedigtes-Unterseekabel-bremst-Int...) >>> which cuts 30 GBit/s transfer capacity. >> >>> Cheers >> >>> -- >>> Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de >> >>> Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt >>> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- >> >> well its not that... >> >> I just downloaded the "standalone programmer" 916MByte OK, so Xilinx >> servers have no issues with the bandwidth >> the problem is that the registration does not work. for that there is >> no bandwidth needed. >> >> just a webmaster who does what he is getting paid for. thats all that >> is needed. >> >> Antti > > ah its all working now!! > > it only 6.7 GB download :) > > Antti Why don't they use bit torrent? It would save them a packet (hoho) in bandwidth costs... Syms.Article: 130473
Hi all, I am using Chipscope 9.2i in ubuntu 7.10. Everything works fine except for Chipscope analyzer GUI not showing up. But the weird thing is insert.sh and gengui.sh are working, I mean the GUI pops up, but analyzer's GUI never show up. When I use Tightvnc to remote desktop to the local machine, the Chipscope analyzer GUI shows up. I recon it's problem of my X. And I did run export DISPLAY=:0, but it doesn't help. Why insert.sh and gengui.sh's GUI works, but analyzer's? Please help, thanks in advance.Article: 130474
>> it only 6.7 GB download :) >> >> Antti >Why don't they use bit torrent? It would save them a packet (hoho) in >bandwidth costs... That and slave servers around the world. Like other large internet projects handle this kind of issue. Ie why have 100 ppl download over a slow pipe when you can download it fast from a local server. A response from xilinx on this matter would be nice.
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