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What are the failure cases that you experience? I did something like this a few years ago w/ a V2Pro-X @ 3.x Gbps and had to do a lot of playing around with the settings in the megawizard in order to turn off all of the layers of encoding and get everything working properly as a "vanilla" SERDES. One thing that I would look at is whether or not you need to do manual bit-slipping in order to actually frame the data properly. Otherwise, you might not have the 8-bit / 16-bit words aligned properly. I would also recommend a scrambling algorithm, in order to balance 1's and 0's. I believe the spec for those parts is up to ~71 consecutive 1's or 0's before losing CDR. Jeff On Mar 26, 3:27 am, shakith.ferna...@gmail.com wrote: > Hi, > > We have developed a High Speed on FPGA using the MGT/RocketIO to > generate high speed signals. Also we receive the high speed signals > using the MGT. Due to the nature of the application, we require a pure > signal without encoding (We have switched off the 8B/10B encoding in > the MGT). The problem is that it effects the clock recovery accuracy > in the received signal as there might not be good DC balance in the > signal. Which in turn effects the data received. And MGT is a black > box to us. > > Two options- > 1. Another encoding mechanism such that we have pure signal and good > clock recovery. > 2. Or is there a parameter in MGT to improve the clock recovery. > > We are looking for some solution around this problem. > > Our setup: > FPGA - Xilinx Virtex II Pro > Board - Xilinx XUP Virtex(tm)-II Pro Development System > Software - ISE 9.1i > > Best Regards > ShakithArticle: 130526
"Peter Alfke" <peter@xilinx.com> wrote in message news:856c6055-0b45-4a6a-99f1-0c5a3c49fbf8@e23g2000prf.googlegroups.com... > Many years ago, when we packed our little kids into the station wagon > for the 45 min trip to the beach, they would become impatient after a > few miles and whine: "Aren't we there yet?". > The whining here reminds me of those trips. > PS: We always made it to the beach, the whining seems to be what > parents are supposed to endure... > Peter Alfke It's more like when you take your kids to the icecream shop only to find out that it's closed in the middle of the day! It must have been a server-side issue because the registration pages never came up. All is well now however. The web install worked like a champ. -- Steve Knapp Prevailing Technology, Inc.Article: 130527
I am wondering if it is possible to select IPLB (Instruction PowerPC Bus) to work with 32 bits instead of 64 bits?. The reason is that my DDR Sdram fails when it works with double words (64 bits) and it could be simpler to configure IPLB to work with 32 than configure the DDR Sdram to work with double words. my best regardsArticle: 130528
"Antti" <Antti.Lukats@googlemail.com> wrote in message news:74c03eac-ca76-4491-a46b-e3d2d98ac16d@e23g2000prf.googlegroups.com... [snip] > PS you have switched to dangerous company? ;) > or maybe i dont know the exact meaning of "prevailing.." It's always interesting to see how names "translate" internationally. Hopefully, it's not quite like the "bite the wax tadpole" problem Coca Cola had when originally selling in China. http://www.snopes.com/cokelore/tadpole.asp The term "prevailing technology" generally means the technology that eventually wins out or prevails over all others (the hopeful state for all technology ventures). The company logo is supposed to be a visual pun. Prevailing Technology ... (wait for it) ... "Prevailing _over_ Technology". Okay, maybe not so funny. You had to be there. -- Steve Knapp www.prevailing-technology.comArticle: 130529
> I was wondering if there is a good VHDL document generation utility (free or > not) out there? I stumbled across an article describing HDLDoc by DualSoft, > which seemed promising, but it seems that that company ceased to exist... I > am looking for something that would be more than just a comments > extractor... I use vhdldoc: http://schwick.home.cern.ch/schwick/vhdldoc/Welcome.html YMMV -P@Article: 130530
On 25 mar, 15:36, oscar.ode...@gmail.com wrote: > Hi, > I tried to use the EDK 9.2 MicroBlaze tutorial in Virtex-4 but at the > end of the Base System Builder Wizard I found some problems. > I opened the project with Xilinx ISE, imported the new peripheral > (named custom_ip), followed all points and created a new directory > called custom_ip_v1_00_a in the pcores directory. When the guide says: > "Select the system.xmp source file and double click on the View HDL > Instantiation Template. Once the process has completed the editor > window will contain the instantiation template called system.vhl" the > process doesn't synthetizes. > why? > > thank you Have you use "Export to project navigator " to use Xilinx ISE?? I don't know if version 9.2 support this utility?. Could you explain me step by step what you do to know what is the problem?Article: 130531
Hi all, I was wondering if there is a good VHDL document generation utility (free or not) out there? I stumbled across an article describing HDLDoc by DualSoft, which seemed promising, but it seems that that company ceased to exist... I am looking for something that would be more than just a comments extractor... Thanks, /MikhailArticle: 130532
MM wrote: > I was wondering if there is a good VHDL document generation utility (free or > not) out there? I stumbled across an article describing HDLDoc by DualSoft, > which seemed promising, but it seems that that company ceased to exist... I > am looking for something that would be more than just a comments > extractor... for free, have a look at this: example http://schwick.web.cern.ch/schwick/muctpi/mirod/mirod.html download http://schwick.home.cern.ch/schwick/vhdldoc/Welcome.html I haven't used it, but I like the idea of postprocessing rather than preprocessing the code. Keep in mind that the customer for this kind of documentation is the user or customer of the hdl design, not the author. Some developers are fussy about their front-end tools and might lack motivation to adopt the more restrictive documentation systems like mentor hdl designer. A developer would probably prefer a working testbench to a binder full of documents in any case. -- Mike TreselerArticle: 130533
Un bel giorno MM digiṭ: > I was wondering if there is a good VHDL document generation utility (free or > not) out there? I stumbled across an article describing HDLDoc by DualSoft, > which seemed promising, but it seems that that company ceased to exist... I > am looking for something that would be more than just a comments > extractor... The almighty Doxygen now supports also VHDL: http://www.stack.nl/~dimitri/doxygen/ http://www.stack.nl/~dimitri/doxygen/docblocks.html#vhdlblocks -- emboliaschizoide.splinder.comArticle: 130534
SaTaN0rX@googlemail.com wrote: >> Don't use two clock domains, just drive the cordic with a half- >> frequency Clock Enable. That keeps everything synchronous, and on the >> same clock. > Thank You. > > I'm currently trying to implement the design using a parallel cordic > (which is able to reach 200MHz), > but is of course a huge ressource waste. (this cordic will process 1 > vector every 3000 clock cycles) > > I'll try aour suggestion once I'm done with the current run, but a > question remains: > > will ISE be smart enough to notice that the cordic runs at half of the > clock speed ? > I have the feeling that ISE will still create timing violations in the > cordic. Do I need to use timing groups? Dear Satan, RTFM. Specifically the constraints guide. NET "clk_en_100M" TNM=FFS "clock_enable"; TIMESPEC TS1000 = FROM : clock_enable : TO : clock_enable : 100ns ; And please, oh dark lord, send my regards to all your little wizards. I'm looking forward to meeting you all in a few years time. I hope you're looking after my friends who've already made it to you. Also, I'm practising with my violin. Cheers, Syms.Article: 130535
Georg Acher wrote: > Jon Elson <elson@pico-systems.com> writes: > >>I got a batch of "Xilinx" Spartan XCS30 FPGAs from a Chinese >>seller, and am having problems with random failures at first >>power up. Sometimes it is a stuck I/O pin, sometimes a failure >>to configure. I first thought maybe we had an ESD problem, but >>I'm now thinking these may be counterfeit. They have white ink >>printed labels on the front, whereas other Xilinx chips have >>laser-etched labels. Also, these Spartan chips don't have the >>Spartan logo just below the Xilinx logo, like my other Xilinx >>chips. Anyone have any comments on this? > > > I have XCS10XL in TQFP100 from around 1999/2000 and they also have printed > labels. They were obtained from the official German distri at that time > (Metronik/Unique). So I guess that white ink labels are no sign of unoffical > chips... > Yup, I have some test fixtures here with Spartans in them from VERY close to the same date code as the lot in question. They also have a white printed label. The most obvious difference is the one in the fixture has Spartan(tm) in big letters right under the Xilinx(tm), while the questioned one is missing that Spartan line. Every onter Spartan chip I can dig up has the Spartan marking on it, too, in whatever marking technology was used. Another difference is the questionable one has a "weaker" label printing, under a microscope it looks "speckled" while the good chip looks to have very dense ink. The speckles look a lot like looking at laser printer toner under a microscope. Of course, I'm just jumping to lots of conclusions here, with no real basis to stand on. When I pulled the removed chips out of the desoldering tool, they bent noticeably. I thought these package materials were supposed to be thermosetting, and shouldn't get soft when heated to desoldering temperatures. Maybe my desoldering tool was getting a lot hotter than I thought, but I just ran it up until I could lift the chips. JonArticle: 130536
On Mar 26, 10:23=A0am, "MM" <mb...@yahoo.com> wrote: > Hi all, > > I was wondering if there is a good VHDL document generation utility (free = or > not) out there? I stumbled across an article describing HDLDoc by DualSoft= , > which seemed promising, but it seems that that company ceased to exist... = I > am looking for something that would be more than just a comments > extractor... > > Thanks, > /Mikhail I've used the following document extraction tools: NaturalDocs Robodoc Both do not natively support VHDL, but can be configured to extract decent documentation. See http://en.wikipedia.org/wiki/Comparison_of_documentation_generatorsArticle: 130537
Hello, I am planning to visit Amsterdam and Brussells in July '08 for a week. What places you would recommend to see for these two cities? Thanks AshokArticle: 130538
water9580@yahoo.com wrote: > On Mar 25, 1:17 pm, John_H <newsgr...@johnhandwork.com> wrote: >> water9...@yahoo.com wrote: >>> no reply? >>> water9...@yahoo.com wrote: >>>> The Linux lspci -xxx command can show my PCIE device header >>>> space(0x00~0xFF). However,simultaneity,the Correctable Error and >>>> Unsupported Request error from PCIE Capabilities device status >>>> register are set. >>>> I run the PCI Express Configuration Testing program from PCISIG to >>>> test configure space.The system is halt after click run all test.Reset >>>> PC and report NMI error. >>>> why? >>>> My configuration: PCIEx1, 16bit customize GTP wrapper same as Endpoint >>>> x1 IP. >> Do you see anything unusual from your PCI Express protocol analyzer? > > No,i didn't use any protocol analyzer. Only PCISIG Configuration > Testing program If this is your first PCI Express design, you need to think about getting some tools. PCI-SIG recommends a scope with at least 6GHz of bandwidth. There are a couple of different companies that have PCIE analyzer solutions. You need to buy, rent, or borrow one. I've run compliance testing in the Gold suite at PCI-SIG workshops. It takes me just a couple of minutes to identify the folks that designed and built a device without having the right tools. There's a real surprised look on their face when they see the waveforms. Sometimes we spend the entire scheduled testing period just debugging their design, electrically. If your device is failing the Config Test program, you may need to write some low-level code to generate some simple cycles. You'll want to start with a single Cfg Read, Type 0 of Register 0, and look at the results. Follow that up with more reads and writes, stepping through the enumeration process. If you don't want to do that, the same companies that make analyzers make exercisers that can generate the necessary cycles and show you the result of the completions. Good luck... RBArticle: 130539
On Mar 26, 3:19 pm, "Ashok Chotai" <as...@xilinx.com> wrote: > Hello, > I am planning to visit Amsterdam and Brussells in July '08 for a week. > What places you would recommend to see for these two cities? > Thanks > Ashok In Amsterdam, I would recommend visiting the Anne Frank House, where she hid during World War II. That is where she taught herself VHDL and programmed her first FPGA. Alan NishiokaArticle: 130540
Ashok Chotai wrote: > Hello, > I am planning to visit Amsterdam and Brussells in July '08 for a week. > What places you would recommend to see for these two cities? > Thanks > Ashok > > It depends how much fun you want to have.Article: 130541
Hi, I have developed a Decoder in verilog and successfully simulated it on an FPGA. I am using Actel's ProASIC3E proto kit. Simulink has an instrument control toolbox which allows one to read and write to the fpga. I plan to have the encoder, modulation and demodulation blocks in simulink and want to send the demodulated data to the fpga through serial and recieve the output. How can I do this? My design is synchronous takes 2 bits which get decoded into 1bit. Also, what's the output voltage/current on the pc serial port? If the connect on the pins directly into one of fpga's input pins on the board.. would I fry it? (I don't have a serial port on the fpga proto board). Is this even possible? Thanks for the help, SarahArticle: 130542
On Mar 26, 7:46=A0pm, sarah_s <sarah.stre...@gmail.com> wrote: > Hi, > > I have developed a Decoder in verilog and successfully simulated it on > an FPGA. I am using Actel's ProASIC3E proto kit. Simulink has an > instrument control toolbox which allows one to read and write to the > fpga. I plan to have the encoder, modulation and demodulation blocks > in simulink and want to send the demodulated data to the fpga through > serial and recieve the output. How can I do this? My design is > synchronous takes 2 bits which get decoded into 1bit. Also, what's the > output voltage/current on the pc serial port? If the connect on the > pins directly into one of fpga's input pins on the board.. would I fry > it? (I don't have a serial port on the fpga proto board). Is this even > possible? > > Thanks for the help, > Sarah Sorry simulink also read/write to the serial port.Article: 130543
Hi, I have developed a Decoder in verilog and successfully simulated it on an FPGA. I am using Actel's ProASIC3E proto kit. Simulink has an instrument control toolbox which allows one to read and write to the pc serial port. I plan to have the encoder, modulation and demodulation blocks in simulink and want to send the demodulated data to the decoder on fpga through serial and recieve the output. How can I do this? My design is synchronous. It takes 2 bits at every clock cycle which get decoded into 1bit. Also, what's the output voltage/current on the pc serial port? If the connect on the pins directly into one of fpga's input pins on the board.. would I fry it? (I don't have a serial port on the fpga proto board). Is this even possible? Thanks for the help, SarahArticle: 130544
Paul Urbanus wrote: > > As with all designs, understanding the capabilities of the devices > being used along with the performance needs of the final design will > lead one to a series of decisions which will insure that all > requirements are met. > Urb Urb, Your typo is telling. Xilinx won't insure you, no matter you ensure your design will work! ;-) Best, Syms.Article: 130545
Hi Mike, On Mar 18, 10:58 pm, morphiend <morphi...@gmail.com> wrote: > On Mar 18, 6:35 am, John Williams <jwilli...@itee.uq.edu.au> wrote: > > > I'm attempting to get the xps_ll_temac talking to an SGMII PHY > > (Vitesse 8211), with little success. > > > The board doesn't have a dedicated 125MHz differential clock, so I'm > > deriving the 125MHz clock internally with a DCM, driving the > > ll_temac's MGTCLK_P signal with it, and setting the C_INCLUDE_IO param > > to zero to direct EDK that this clock drives the MGT clock directly > > (no IBUFDS). I understand this is not ideal but I didn't lay out the > > board! > > Did you consider the jitter requirements when using the DCM to > generate the clock for the MGT? I've got it working now. I obtained an ML505 SGMII reference design from Xilinx, and reworked it to derive the MGT clock from an internal DCM rather than the external differential clock - worked fine! Gave me confidence that my clocking scheme would work, which it does. For the record, my problem was needing some pullup and pulldown constraints on some FPGA pins sampled by the PHY immediately post- reset. The PHY oscillator was being disabled, - no clock -> no fun! One observation from this experience - with the proliferation of BGA packaging there are a lot of signals that simply cannot be observed if they route directly between two BGA packages with no discretes touching the trace. Instead of directly observing the clock I had to route it into the FPGA, through a big counter and drive a LED with the MSB to detect activity. Cheers, JohnArticle: 130546
On Mar 18, 10:28 pm, Antti <Antti.Luk...@googlemail.com> wrote: > I have been think and part time working towards a goal to make useable > and useful serialized processor. The idea is that it should be > > 1) VERY small when implemented in any modern FPGA (less 25% of > smallest device, 1 BRAM) > 2) be supported by high level compiler (C ?) What's the smallest instruction set supported by an existing and available C compiler? Is there a C compiler available for any of the tiniest stack machines, or even for an OISC (one instruction set computer)?Article: 130547
"Alan Nishioka" <alan@nishioka.com> wrote in message news:d13512dc-94b3-4533-9cfa-115bf5461b9a@i29g2000prf.googlegroups.com... > On Mar 26, 3:19 pm, "Ashok Chotai" <as...@xilinx.com> wrote: >> Hello, >> I am planning to visit Amsterdam and Brussells in July '08 for a week. >> What places you would recommend to see for these two cities? >> Thanks >> Ashok > > In Amsterdam, I would recommend visiting the Anne Frank House, where > she hid during World War II. That is where she taught herself VHDL > and programmed her first FPGA. > > Alan Nishioka Wow. I had no idea. I don't remember seeing any HDL in her diary (she must have kept it all in her head). With her hardware skills, the Nazis could have developed the V3 and possibly even won the war. How ironic. BobArticle: 130548
On Mar 27, 6:23 am, Rube Bumpkin <Some...@somewhere.world> wrote: > water9...@yahoo.com wrote: > > On Mar 25, 1:17 pm, John_H <newsgr...@johnhandwork.com> wrote: > >> water9...@yahoo.com wrote: > >>> no reply? > >>> water9...@yahoo.com wrote: > >>>> The Linux lspci -xxx command can show my PCIE device header > >>>> space(0x00~0xFF). However,simultaneity,the Correctable Error and > >>>> Unsupported Request error from PCIE Capabilities device status > >>>> register are set. > >>>> I run the PCI Express Configuration Testing program from PCISIG to > >>>> test configure space.The system is halt after click run all test.Reset > >>>> PC and report NMI error. > >>>> why? > >>>> My configuration: PCIEx1, 16bit customize GTP wrapper same as Endpoint > >>>> x1 IP. > >> Do you see anything unusual from your PCI Express protocol analyzer? > > > No,i didn't use any protocol analyzer. Only PCISIG Configuration > > Testing program > > If this is your first PCI Express design, you need to think about > getting some tools. PCI-SIG recommends a scope with at least 6GHz of > bandwidth. There are a couple of different companies that have PCIE > analyzer solutions. You need to buy, rent, or borrow one. > > I've run compliance testing in the Gold suite at PCI-SIG workshops. It > takes me just a couple of minutes to identify the folks that designed > and built a device without having the right tools. There's a real > surprised look on their face when they see the waveforms. Sometimes we > spend the entire scheduled testing period just debugging their design, > electrically. > > If your device is failing the Config Test program, you may need to write > some low-level code to generate some simple cycles. You'll want to start > with a single Cfg Read, Type 0 of Register 0, and look at the results. > Follow that up with more reads and writes, stepping through the > enumeration process. If you don't want to do that, the same companies > that make analyzers make exercisers that can generate the necessary > cycles and show you the result of the completions. > > Good luck... > > RB but,i use a simple tool of windows ,eg:Pcitree. it can read out my PCIE device header content. why ompliance testing prgrame not?Article: 130549
"MM" <mbmsv@yahoo.com> wrote in message news:650h6dF2clht9U1@mid.individual.net... > "Alan Nishioka" <alan@nishioka.com> wrote in message > news:d13512dc-94b3-4533-9cfa-115bf5461b9a@i29g2000prf.googlegroups.com... >> >> In Amsterdam, I would recommend visiting the Anne Frank House, where >> she hid during World War II. That is where she taught herself VHDL >> and programmed her first FPGA. > > not funny :( > > /Mikhail Mikhail, Please explain why you don't find that funny. Please. Bob
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