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On Mar 5, 11:39=A0am, Olaf <is...@inter.net> wrote: > Hi, > > I test the EDK 9.2 MicroBlaze Tutorial > (http://www.xilinx.com/support/techsup/tutorials/92_MB_Tutorial.pdf) for > my Spartan3e Starter Board Rev.D using XPS 9.2.02i. After the bitsream > is uploaded, the TestApp_memory is started and got on rs232: > > -- Entering main() -- > Starting MemoryTest for DDR_SDRAM: > =A0 =A0Running 32-bit test...FAILED! > =A0 =A0Running 16-bit test...FAILED! > =A0 =A0Running 8-bit test...FAILED! > -- Exiting main() -- > > I know, there was a problem using the MIG for this board. Is this my > problem? and is it solved now? > > Thanks, > Olaf You better try some verified designs first: http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm Try: XAPP983 Executing and Debugging Software from Flash Memory If it also fails the memory test then return the board. cheers, GuruArticle: 129826
austin <austin@xilinx.com> writes: > Well, we are unable to get anyone interested to try it, as they tried > the obviously less secure 3DES, and didn't get anywhere. I think claiming 3DES to be "obviously less secure" is a bit much. DES has withstood far more attacks than AES. After all that, there are no known attacks that are significantly better than brute force, so 3DES is quite secure. AES *might* be as secure or more, but since it hasn't had nearly as much time to be poked and prodded by cryptographers, I wouldn't count on it. Of course, some clever cryptographer might come up with a new attack against either one. The biggest advantage of AES over 3DES is that AES is approved by the US government now, and DES no longer is. (I think 3DES still is for at least some applications.) For my own data, I prefer 3DES.Article: 129827
austin <austin@xilinx.com> writes: > I knew someone would say this, > > Yes, there are those that think because the NSA approves a crypto > standard, they either have a back door, or some other way around it. > > You give them far too much credit. > > They are not that smart. > > If there is a weakness, or a back door, then they have created a way for > all systems they certify to be broken. > > They are also not that stupid. They *are* that smart. When the influenced the design of DES way back when, they *both* strengthened and weakened it. They weakened it by reducing the key length to 56 bits. It is generally believed that they did this because they could afford to build hardware that would brute-force search a 56-bit key space. The strengthened it by making design changes, the nature of which was not obvious at the time. Many years later, cryptographers (re)discovered linear and differential cryptanalysis methods, and found that the NSA's changes to the design of DES made it essentially immune to those lines of attack. The NSA had developed those attacks, but had not published them, for obvious reasons. In other words, the NSA wanted the strength of DES to be only 56 bits, but also not to have weaknesses reducing the effective key size signficantly below 56 bits. When the NSA is involved in the development of any cryptosystem made available for public use, it would be foolish to assume that they haven't made sure that it is neither too insecure nor too secure. EricArticle: 129828
On Mar 6, 5:19 am, austin <aus...@xilinx.com> wrote: > Allan, > > No Altera product with poly efuse is able to meet FIPS 41, none are > approved by the NSA. > > In my book, that means we see no competition (all customers that require > FIPS 41, or NSA approval come to Xilinx). > > Now, if you do not require FIPS 41, or you are not interested in NSA > compliance, then the Altera solutions are perfectly good, and useful. > In no way do I imply they are poor solutions, however, they are not in > compliance with the highest level standards, and they are not approved > for generic use in US government contracts. > > That means, they are not a solution for banking (which requires FIPS > 41), and other commercial markets as well. > > What is left? From the "Virtex" point of view, nothing at all of import. > > Perhaps in the Cyclone/Spartan world, there are some good sockets they > win (and we do too) for anti-cloning of consumer goods. > > I am sure they will have FIPS 41 compliant products at some point. I am > also sure they will eventually get NSA approval (if they can meet their > requirements, as the US government is not allowed to play favorites, and > must treat all fairly). Until then, we enjoy the sockets we are getting, > > Austin The reason the Xilinx parts get approval for single chip Type 1 COMSEC applications has to do primarily with software tools changes insuring adequate red/black separation.using the column based architecture found in Virtex-4 LX, SX and FX. http://www.mil-embedded.com/PDFs/NSA.Mar07.pdf FIPS 41 is entitled "Computer Security Guidelines for Implementing the Privacy Act of 1974" and was withdrawn in 1998.; I think you mean FIPS140-2 (-3 pending) "Security Requirements for Cryptographic Modules", wherein you can use the placement tools and column architecture for functional separation (compartmentalization). The FIPS 140 criteria derive from the NSAs CCEP program. One could wonder if the market is sufficiently large or attractive enough for Altera to make the effort.Article: 129829
On Mar 6, 10:54 am, austin <aus...@xilinx.com> wrote: > Antti, > > Good points. Even the best component security doesn't equate to a high > level of system security. > > You are also correct to point out the Actel antifuse (basically a via > that can be 'popped') where is 'impossible' to map all of them, and > hence how the part is programmed. This is only because no one has > automated this attack: if automated, it could be done (shave off 10 > angstroms, take a picture, repeat, then rebuild the connections). > > Don't forget some attackers have infinite labor, and infinite patience. > My favorite example is when the students took over the American Embassy > in Iran, and then put back together all of the shredded secret documents > ... a massive task, but just a big puzzle after all (and one that could > be, and was, solved). > > Austin There were interesting stories about Intel and a scanning electron beam prober during the Clipper Chip days (uses anti-fuse). Something about seeing the charge around a via and telling whether or not the fuse was conducting or high impedance. Presumably this would be easier to automate. There was a lot of speculation about tamper proof chip cases. Also something about the technology getting classified.Article: 129830
Hi, I have written already about this topic. At finally I have configured a DDR SDRAM core for PowerPC so I could read and write from/ to DDR. It supports words, half words and bytes. I have probed it with Xilinx TestMemory and Mwr/Mrd in xmdstub. Everything works fine and I could use this memory for my programs. The problem is that my programs have growed a lot and now I have to download the executable.elf to the DDR via xmdstub. When I do it, the program doesn't work. I have disassemble the executable.elf and run the program step by step. The problem is that certain number of assemble code doesn't work as I need. I have probed to download only the code belongs to my program, so "boot.o", "cpu_init.o",... , resides at bram. But when PC pointer arrives to my program at DDR, then it fails again. I know that this situation is very strange, but I could not use xilinx ddr cores because my custom board has another type of configuration. Any advice? Thanks a lot for your help.Article: 129831
On Mar 6, 7:40 am, Pablo <pbantu...@gmail.com> wrote: > Hi, I have written already about this topic. At finally I have > configured a DDR SDRAM core for PowerPC so I could read and write from/ > to DDR. It supports words, half words and bytes. I have probed it with > Xilinx TestMemory and Mwr/Mrd in xmdstub. Everything works fine and I > could use this memory for my programs. > > The problem is that my programs have growed a lot and now I have to > download the executable.elf to the DDR via xmdstub. When I do it, the > program doesn't work. I have disassemble the executable.elf and run > the program step by step. The problem is that certain number of > assemble code doesn't work as I need. > > I have probed to download only the code belongs to my program, so > "boot.o", "cpu_init.o",... , resides at bram. But when PC pointer > arrives to my program at DDR, then it fails again. > > I know that this situation is very strange, but I could not use xilinx > ddr cores because my custom board has another type of configuration. > > Any advice? > > Thanks a lot for your help. Make sure you have the IPLB of the PPC connected to the PLB that your memory controller resides on. Being able to access the data side is completely seperate from the instruction side, from the processor's point of view.Article: 129832
On Mar 6, 7:40 am, Pablo <pbantu...@gmail.com> wrote: > Hi, I have written already about this topic. At finally I have > configured a DDR SDRAM core for PowerPC so I could read and write from/ > to DDR. It supports words, half words and bytes. I have probed it with > Xilinx TestMemory and Mwr/Mrd in xmdstub. Everything works fine and I > could use this memory for my programs. > > The problem is that my programs have growed a lot and now I have to > download the executable.elf to the DDR via xmdstub. When I do it, the > program doesn't work. I have disassemble the executable.elf and run > the program step by step. The problem is that certain number of > assemble code doesn't work as I need. > > I have probed to download only the code belongs to my program, so > "boot.o", "cpu_init.o",... , resides at bram. But when PC pointer > arrives to my program at DDR, then it fails again. > > I know that this situation is very strange, but I could not use xilinx > ddr cores because my custom board has another type of configuration. > > Any advice? > > Thanks a lot for your help. I would start by trying to find out what types of memory cycles might happen during program execution that were not tested by TestMemory etc. Some possibilities: TestMemory does not overlap banks while program execution does. TestMemory is not dependent on burst order/length while program execution is. Any possibility of fitting ChipScope into your design and looking at the DDR activity when it fails (assuming you can figure out what to trigger on)? That's all I can think of at the moment. Regards, GaborArticle: 129833
Does anybody have any experience with programming an 802.16d decoder with the Xilinx Viterbi decoder, as far as how to parameterize the core? I've been beating my head against this and can't quite figure out how to get the core set up correctly. I know cores are the devil, but they do save some time. Thanks for the help.Article: 129834
maverick wrote: > //----------------------------------------------------------------------------// > > Anyone out there to help me out here. > > Farhan I'll give you one quick shot: Check the options for your Xilinx tool. In the GUI, there's actually a checkbox for "ignore timing constraints." Look for it.Article: 129835
I saw this, but it doesn't tell how to understand the code. There's
all sorst of strange constructs like:
OUTPUT =3D NORF(OUTPUT.d, SYSCLK, RESET, GND)
Which I assume is a DFF with a preset and clear, but I can't be sure
unless I have documentation.
There are other constructs like:
X =3D RORF()
X =3D COCF()
X =3D RONF()
X =3D CONF()
There are also logic equations
X.d =3D !Y & Z
# Q
Which I assume is X.d =3D ((not Y) and Z) or Q algebraically.
On Mar 5, 6:21=A0pm, "Dejan" <_remove_dejan@_remove_dilogic.hr> wrote:
> "jtw" <wrightjt @hotmail.invalid> wrote in message
>
> news:8bpzj.14675$0o7.7677@newssvr13.news.prodigy.net...
> > You might want to also crosspost to comp.arch.fpga.
>
> If you only want to use ADF files in Quartus, here is description of the w=
hole conversion
> procedure (that involves MaxPlus-II too)
>
> http://www.altera.com/support/kdb/solutions/rd02012007_34.html
>
> For total re-write, I've got no idea :-(
>
> regards
>
> Dejan- Hide quoted text -
>
> - Show quoted text -
Article: 1298363 X 56 bits < 256 bits. Note that we have AES256, and the "other" competitor only had AES128. AES128 was not approved (for the crypto modernization program). I am sure that tells you something. AustinArticle: 129837
Thanks for your advice. Both give me the opportunity to continue to seek a solutionArticle: 129838
On Mar 6, 7:54=A0am, CTSportPilot <girm...@gmail.com> wrote: > I saw this, but it doesn't tell how to understand the code. =A0There's > all sorst of strange constructs like: > > OUTPUT =3D NORF(OUTPUT.d, SYSCLK, RESET, GND) > > Which I assume is a DFF with a preset and clear, but I can't be sure > unless I have documentation. > > There are other constructs like: > X =3D RORF() > X =3D COCF() > X =3D RONF() > X =3D CONF() > > There are also logic equations > > X.d =3D !Y & Z > =A0 =A0 =A0 =A0# Q > > Which I assume is X.d =3D ((not Y) and Z) or Q algebraically. > > On Mar 5, 6:21=A0pm, "Dejan" <_remove_dejan@_remove_dilogic.hr> wrote: > > > > > "jtw" <wrightjt @hotmail.invalid> wrote in message > > >news:8bpzj.14675$0o7.7677@newssvr13.news.prodigy.net... > > > You might want to also crosspost to comp.arch.fpga. > > > If you only want to use ADF files in Quartus, here is description of the= whole conversion > > procedure (that involves MaxPlus-II too) > > >http://www.altera.com/support/kdb/solutions/rd02012007_34.html > > > For total re-write, I've got no idea :-( > > > regards > > > Dejan- Hide quoted text - > > > - Show quoted text -- Hide quoted text - > > - Show quoted text - The macrocells in the Altera CPLDs are registers with or without feedback and even with or without a direct output. I believe these primitives are for the output select from the logic and the register. While the NORF() with the list is similar to ordered lists in other languages, you'd need a list of primitives to understand precisely what each entry is. In the case of the NORF, by inspection the first entry is the output connected to the D input of a declared register such as a DFFE (D flip-flop with enable). The ports on declared items are referred to by NAME.port and here, again, the primitive definitions tell you precise syntax. I think the language allows both forms - declared elements as well as the ordered-list function form - such that the NORF could have been declared in a primitive list and the connections referred to as NAME.o, NAME.clk, NAME.rst and NAME.clr. I cut my teeth on AHDL in 1988 and haven't used it in well over a decade. If you have other specifics, air them. If I can't recall, I have another engineer here that declares AHDL as one of his competencies. - John_H (from comp.arch.fpga)Article: 129839
kiransr.ckm@gmail.com wrote:
> I have a design developed long before now i want the same desin to
> work for the double frequency at what it was working before. So for
> this what i have to do.
Redesign it with more latency.
If start to done takes 4 clock ticks in the old design
redo it to use 8 clock ticks (same nS for double frequency).
Sometimes I use a step counter and a case statement.
-- Mike Treseler
Article: 129840On Thu, 06 Mar 2008 07:56:18 -0800, austin <austin@xilinx.com> wrote: >3 X 56 bits < 256 bits. > >Note that we have AES256, and the "other" competitor only had AES128. > >AES128 was not approved (for the crypto modernization program). > >I am sure that tells you something. You would not try to brute force a 128 bit AES system. Making the brute force attack 2^128 times harder by doubling the key size, doesn't change all that much since you wouldn't be using that approach anyway. (Yes, I do know that only the 256 bit key version is approved for top secret work in the USA. All our products support the 256 bit key size for that reason.) BTW, I think bitstream encryption is an excellect idea for protecting the intellectual property that the bitstream represents. I'm just not sure I'd rely on it as an essential part of a security system, where the threat model includes attacks by well funded military organisations. Austin, is there an appnote showing how bitstream encryption can be used to make an HSM? I'd be intersted in knowing how it's done. Disclaimer: none of our products rely on bitstream encryption (from any FPGA vendor) to protect our customers' secrets. Regards, AllanArticle: 129841
On Mar 6, 10:54=A0am, CTSportPilot <girm...@gmail.com> wrote: > I saw this, but it doesn't tell how to understand the code. =A0There's > all sorst of strange constructs like: > > OUTPUT =3D NORF(OUTPUT.d, SYSCLK, RESET, GND) > > Which I assume is a DFF with a preset and clear, but I can't be sure > unless I have documentation. > > There are other constructs like: > X =3D RORF() > X =3D COCF() > X =3D RONF() > X =3D CONF() > > There are also logic equations > > X.d =3D !Y & Z > =A0 =A0 =A0 =A0# Q > > Which I assume is X.d =3D ((not Y) and Z) or Q algebraically. > > On Mar 5, 6:21=A0pm, "Dejan" <_remove_dejan@_remove_dilogic.hr> wrote: > > > > > "jtw" <wrightjt @hotmail.invalid> wrote in message > > >news:8bpzj.14675$0o7.7677@newssvr13.news.prodigy.net... > > > You might want to also crosspost to comp.arch.fpga. > > > If you only want to use ADF files in Quartus, here is description of the= whole conversion > > procedure (that involves MaxPlus-II too) > > >http://www.altera.com/support/kdb/solutions/rd02012007_34.html > > > For total re-write, I've got no idea :-( > > > regards > > > Dejan- Hide quoted text - > > > - Show quoted text -- Hide quoted text - > > - Show quoted text - Googling for "Altera+NORF" http://www.google.com/search?hl=3Den&q=3DAltera+NORF The first link came up the following PDF file from Texas A&M which might give you some more clues. http://courses.cs.tamu.edu/rgutier/ceg453_s00/altera_handout.pdf Page 14 says that NORF=3DNo output registered feedback, CONF=3DCombinatorial output, no feedback. Page 17 lists RONF, nothing on COCF, but based on what it has I would expect it to be a combinatorial output with combinatorial feedback. The next few Google link are to "The Church Heraldry of Norfolk: A Description of All Coats of Arms" "JSTOR: Violence and the Exercise of Feudal Guardianship" "Sir Robert Lovett of Liscombe" So I think the pickings are rather slim on this niche. Happy sleuthing. Kevin JenningsArticle: 129842
That's exactly what I was looking for, thanks! This at least gets me most of the way there. I tried googling "norf", but didn't try the combination with Altera. Thanks! On Mar 6, 12:17=A0pm, KJ <kkjenni...@sbcglobal.net> wrote: > > Googling for "Altera+NORF"http://www.google.com/search?hl=3Den&q=3DAltera+= NORF > > The first link came up the following PDF file from Texas A&M which > might give you some more clues. > > http://courses.cs.tamu.edu/rgutier/ceg453_s00/altera_handout.pdf > > Page 14 says that NORF=3DNo output registered feedback, > CONF=3DCombinatorial output, no feedback. =A0Page 17 lists RONF, nothing > on COCF, but based on what it has I would expect it to be a > combinatorial output with combinatorial feedback. > > The next few Google link are to > "The Church Heraldry of Norfolk: A Description of All Coats of Arms" > "JSTOR: Violence and the Exercise of Feudal Guardianship" > "Sir Robert Lovett of Liscombe" > > So I think the pickings are rather slim on this niche. =A0Happy > sleuthing. > > Kevin Jennings- Hide quoted text - > > - Show quoted text -Article: 129843
CTSportPilot wrote: > I saw this, but it doesn't tell how to understand the code. There's > all sorst of strange constructs like: > > OUTPUT = NORF(OUTPUT.d, SYSCLK, RESET, GND) > > Which I assume is a DFF with a preset and clear, but I can't be sure > unless I have documentation. > > There are other constructs like: > X = RORF() > X = COCF() > X = RONF() > X = CONF() > > There are also logic equations > > X.d = !Y & Z > # Q > > Which I assume is X.d = ((not Y) and Z) or Q algebraically. What is the device, and do you have any fitter map/report files, or only the source code ?. The link given earlier uses MAX+II as a stepping stone, to convert ADF to tdo to TDF Boolean Eqn porting should be relatively easy, often that support is still in the tool flows. Device specific configs would need some work. -jgArticle: 129844
Alan, HSM? AustinArticle: 129845
Allan, I presume HSM = Host Security Module? If so, that is an application, and we do not supply any examples, nor any IP. AustinArticle: 129846
On Thu, 06 Mar 2008 10:44:13 -0800, austin <austin@xilinx.com> wrote: >Alan, > >HSM? > >Austin google suggests High School Musical. Hmmm. Perhaps this would be better: http://en.wikipedia.org/wiki/Hardware_Security_Module It's only when you start designing products like that, that the distinction between 128 and 256 bit AES becomes important. (IMO) Regards, AllanArticle: 129847
Yes, these methods are very slow. I'm trying your method, but I'm not sure how to get it working from within EDK. I set OPTION CORE_STATE =3D DEVELOPMENT in the mpd and when I rerun "Generate Netlist" I get the output "make: Nothing to be done for `netlist'." platgen is not being run. Is there a way to get it working from within EDK? Thanks On Feb 29, 10:58=A0am, benr...@gmail.com wrote: > On Feb 28, 3:52=A0pm, Skogul <etork...@gmail.com> wrote: > > > These approaches seem to work. Thanks. > > Yes, it works but the whole project will be re synthesized which is > time consuming. > Instead, you can change a parameter of your IP in mhs - and that IP > only will be re synthesized and merged with the rest of the project. > Another option is to use OPTION CORE_STATE =3D DEVELOPMENT in the IP's > mpd and the core will be synthesized every time you runplatgen. > More detail in C:\EDK\doc\usenglish\psf_rm.pdf page 38Article: 129848
Hi, I'm pleased to announce that we have a test release available for MicroBlaze MMU support in the PetaLinux 2.6.20 kernel. You can access it via the http://developer.petalogix.com front page, just follow the links to the release notes and download. Tested hardware platforms so far are Xilinx S3E1600 and ML505 boards, with reference designs for both include in the usual place (hardware/reference-designs/...) If you are looking to target to a new board, after running petalinux-new-platform make sure you copy the core kernel config settings from one of these existing platforms, to your new platform (e.g. vendors/Xilinx/Spartan3E1600-MMU/config.linux-2.6.x -> vendors/XXX/YYY/config-linux-2.6.x) The defaults assigned by the petalinux-new-platform script will be quite far from what is required for the MMU. I'll see about making petalinux-new-platform a bit smarter about this for a future release. Also please note this is a test release - once we do some more cleanup and shakeout a few bugs we will merge it into the mainline PetaLinux distribution. There are a few toolchain issues etc that are as yet unresolved, however it is quite possible to build complete, working systems with this test release. If there is a GCC guru lurking please drop me an email at john.williams@petalogix.com Please send all bugs, patches, experience reports (good and bad!) to this list in the first instance. Finally thanks to Atmark Techno Inc for their financial contribution to porting the MMU support patches to the 2.6.20 kernel tree. For Suzaku users, support on that platform is in the works. http://www.atmark-techno.com/en/ Regards, JohnArticle: 129849
Antti <Antti.Lukats@googlemail.com> wrote: >On 5 Mrz., 17:30, sky46...@trline5.org wrote: >> Would this eeprom work as a configuration boot eeprom for Xilinx XC3S500E ..? >> http://ww1.microchip.com/downloads/en/DeviceDoc/22065A.pdf >generic answer: RTFM >25xxx chips are what is normally described "standard SPI", and have >0x03 READ command, so i would say its ok. But to be sure please verify >that it is OK, dont take my word (or anyone elses) When designing for Spartan-3E I stumbled on a post regarding Sp3E+SPI+SDcard and it got my thinking due that the the XCFxxS chips is harder to source than any "standard spi" eeprom. The price seems to be lower, and the wiring mess less. The only catch is the lack of Jtag port then. However I was abit unsure as to what the Spartan-3E required for an spi eeprom. At the distributor there are several "3-wire serial eeprom" chips. So the confusion was to make the correct match.
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