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Hi everybody, I'm trying to use ICAP for reconfiguring XC2VP30 on ML310 board. At this moment I'm just trying to read back the configuration. However no matter what frame I try reading I get all 0s as the content of the frame. As far as I've understood persist bit should not be set and also configuration mode should not be on JTAG (M2M1M0 should not be 101). I have made sure that these are not problems. I'm using DeviceReadFrame from the hwicap driver to read a frame, meaning that after initialization of ICAP, I try reading a frame which is stored in the storage buffer. After that I print the content of the storage buffer but the content is all 0s. Do you have any idea what the problem could be? As well I have a doubt about something: Why do we have to go through the process of Read, Modify and then Write for reconfiguration? Can't we just write a frame instead of bearing the overhead of reading and modifyin it? Also do I have to explicitly define the BRAM attached to the ICAP device or is it assigned explicitly? I truly appreciate your response beforehand, AmirArticle: 129701
On Mar 3, 8:27=A0am, Kolja Sulimma <ksuli...@googlemail.com> wrote: > Hi, > > maybe you folks can help me with a design decision: > > I need to distribute a clock to up to ten identical boards. > The boards are all plugged into a backplane in a single row. > > In addition to the backplane the boards will be connected by > a twinax flatband cable on samtec connectors. For the clock > distribution I can choose between a bus structure cable or a > series of point to point connections between neighbouring boards. > > The leftmost of the identical boards shall provide a clock for all > the other boards. I am now concerned that a bus structure with > that many stubs will have problems maintaining a good signal quality. > > I could instead use point to point connections with fanout clock > buffers on each board to forward the clock to the next board. As far > as the signal quality goes this will obviously work very well, > BUT the boards need a fixed phase relationship. While the absolute > phase is of no importance, the phase must not drift over time or > temperature by more than 50ps or so. Ten buffers in a row would > probably have a larger drift, wouldn't they? > > Any ideas, how I can make a pure passive distribution work in a setup > like that? > > Also: How can I turn on the termination on the last board dynamically? > > Kolja Sulimma I would generate the clock on the center board, then fan out in both directions and terminate on both ends, which of course means that the driver sees half the characteristic impedance... Peter AlfkeArticle: 129702
"Antti" <Antti.Lukats@googlemail.com> wrote in message news:ee42d07c-3062-489e-93b1-d9afa01fbbac@y77g2000hsy.googlegroups.com... > On 3 Mrz., 17:15, Kolja Sulimma <ksuli...@googlemail.com> wrote: >> On 3 Mrz., 11:20, Antti <Antti.Luk...@googlemail.com> wrote: >> >> > but as the V5FX has been delaying so long, I have almost lost interest >> > to follow up how much longer it is delaying in reality... >> >> > The Spartan-4 is much more interesting, >> >> Well, we are desperately waiting for the V5 MGTs. >> Actually we need a solution for 10gbps soon as XAUI is going to be >> replaced >> by SFP+ really soon. We can't place external 10G serdes on 12 ports. >> >> Kolja Sulimma > > well EVERY new xilinx family since V2ProX is DOWNGRADING the speed of > MGTs > V4 less than V2 > V5 less than V4 > > so you may need wait V6 :( > > Antti > V6? Don't hold your breath. A reliable source tells me that the 10Gbps serdes will be fully functional in V12 Pro (they're skipping V13 for obvious reasons). BobArticle: 129703
On Mar 3, 8:27=A0am, Kolja Sulimma <ksuli...@googlemail.com> wrote: > Hi, > > maybe you folks can help me with a design decision: > > I need to distribute a clock to up to ten identical boards. > The boards are all plugged into a backplane in a single row. > > In addition to the backplane the boards will be connected by > a twinax flatband cable on samtec connectors. For the clock > distribution I can choose between a bus structure cable or a > series of point to point connections between neighbouring boards. > > The leftmost of the identical boards shall provide a clock for all > the other boards. I am now concerned that a bus structure with > that many stubs will have problems maintaining a good signal quality. > > I could instead use point to point connections with fanout clock > buffers on each board to forward the clock to the next board. As far > as the signal quality goes this will obviously work very well, > BUT the boards need a fixed phase relationship. While the absolute > phase is of no importance, the phase must not drift over time or > temperature by more than 50ps or so. Ten buffers in a row would > probably have a larger drift, wouldn't they? > > Any ideas, how I can make a pure passive distribution work in a setup > like that? > > Also: How can I turn on the termination on the last board dynamically? > > Kolja Sulimma Kolja, Have you considered using a clock buffer on the backplane? By using point-to-point connections, your design is significantly cleaner but you no longer have a passive-only backplane solution. - John_HArticle: 129704
Hi,
I just try the patch http://www.xilinx.com/support/answers/30051.htm
and the bug steal occurs if I have a "rand" or "srand" function in my
code.
When i stop the CPU under XMD it returns me the same adress:
0x820036a4
if i do "mb-objdump -x -D -S -t executable.elf > dump.out" to output a
dump file of my *.elf to see what there is at this address:
=2Esection .text
=2Ealign 2
=2Eent _hw_exception_handler
_hw_exception_handler:
bri 0;
820036a4: b8000000 bri 0 // 820036a4
so apparently the code is crashed because of an exeption like the
problem in "Answer Record #29784 (http://www.xilinx.com/support/
answers/
29784.htm". Although i work on the last version of tools with the SP2
and the last patch....
I have tried my code on a PowerPC architecture with the same IP on the
same Hardware and I don't have the bug.
R=E9my
Article: 129705Kolja Sulimma wrote: > Hi, > > maybe you folks can help me with a design decision: > > I need to distribute a clock to up to ten identical boards. > The boards are all plugged into a backplane in a single row. > > > The leftmost of the identical boards shall provide a clock for all > the other boards. I am now concerned that a bus structure with > that many stubs will have problems maintaining a good signal quality. > Hi Kolja, Thinking as I type... 1) What frequency is the clock? The higher the frequency, the more likely you are to have problems with reflections from an edge during the next edge. 2) What is the rise time of the clock? The faster the rise time, the bigger the reflections, in general. 3) What logic standard is the clock? 4) What does the clock drive on the destination cards? FPGAs have relatively large pin capacitance which can cause big reflections at fast edge rates. Your 50ps requirement rules out any tricks with DCMs, they have that much phase noise and more already. I like your daisy chain plan. As you are worried about 50ps, this must be the safest way to go. You could use something like the SY58011u 1:2 CML buffer from Micrel, depending on your operating temperature range. The datasheet has a graph of propagation delay versus temperature. From 10C to 80C the delay changes by 10ps more or less linearly. If you can keep the temperature range low, this might be ok. Use one output to drive the board, the other to drive the next board. They also make 1:4 parts, so the first board could drive the next 3, the 4th drives 5,6,7 and so on. So you'd have fewer buffers. Oh, yeah. Simulate it! HTH., Syms.Article: 129706
Kolja, I hate to say it, but why do you wish to architect a system that has this requirement? Why not solve the problem in a way that does not require this 50ps phase alignment? The added FIFO buffering may be well worth the pain of precise clock phase control/signal integrity. My two pennies, AustinArticle: 129707
here it is: 1) devices densities like in Spartan-3 (50..5000) 2) devices packages like Spartan-3E (including QN132 !) or better (microBGA 6x6 mm?) 3) all good features of S3A/AN !! 4) design security with OTP encryption key (like Lattice ECP2) 5) other features as already planned by Xilinx Antti has made his Christmas wish this year... or did I just describe Lattice XP3 or Cyclone IV? eh, I just wish Spartan-4 will have all the good things from Spartan-3 subfamilies+extra goodies.Article: 129708
At the beginning of February, DJ Delorie proudly posted a bin2seven project. Since my entire reason to purchase a Spartan 3e development board was to experiment, I decided to take DJ Delorie's project and experiment on how coding style and language effected XST/ISE final result. I stuck with DJ Delorie's original target of xc9572. The results were interesting, I will posted them on a website to be viewed later. But I did hit one giant stumbling block. "Use Multi-level Logic Optimization"!!!! This option is on by default when you start a new project. The hurdle I hit is when this option is on, I fail to find a solution that maps to the target device. Instead of minimizing the design it actually causes the design size to be increased. The variant that first hit this issue uses 52/72 macrocells 181/360 Pterms, 8/72 registers 34/34 pins and 72/144 function blocks when this option is off. Which is less resources than all of the other variants of the original DJ Delorie design with the same options. Has anyone else seen "Use Multi-level Logic Optimization" cause a logic explosion, rather than minimization? I am using ISE 9.2i, and XST for the synthesis. I have it set to minimize "Density". This is a tiny design. My concern is in the future when I am working on something more substantial, if I will always need to make sure this switch is disabled to ensure fitting in my target device.Article: 129709
rickman <gnuarm@gmail.com> wrote: >On Mar 2, 7:19 pm, wmwmur...@gmail.com wrote: >> On Mar 2, 3:15 pm, sky46...@trline5.org wrote: >> >> > wmwmur...@gmail.com wrote: >> > >FPGA/CPLD group on LinkedIn >> > > http://www.linkedin.com/e/gis/56713/3CC3BF77FD22 >> > >Group for People Involved In the Design and Verification of FPGA's and >> > >CPLD's to Exchange Idea's and Techniques. You should have FPGA/CPLD >> > >Design/Verification on your Profile to Join. (The focus is more on >> > >FPGA/CPLD in the product as opposed to FPGA's solely as a path to an >> > >ASIC) >> >> > I prefer NNTP over webbforums that is pumped full of the latest webb-fad from >> > the webmaster. Thread structure often missing. >> >> The one big advantage is that joining the group allows one to search >> the members CV's and look for a few people to ask for a one-on-one >> answer to something that they are familiar with. It also allows one >> to build contacts in an area of interest, that one might not otherwise >> meet. Hope this helps with why I started the group. There are other >> reasons to join beyond this as well -- will save for later -- both >> NNTP, and LinkedIn can be useful tools Usenet seem to attract people with more solid knowledge. Also getting trapped in the get-the-latest-webb-browser race seems like a time waste.Article: 129710
Aragorn <me.aragorn@gmail.com> writes: > I am using a LFSR for random number > generation, but I also need a random state of the LFSR to begin with, > don't I? How do I get that? Generally speaking, you need some source of entropy external to the FPGA. For instance, if you put a counter in the FPGA that is clocked at a fairly high frequency, and use it to measure the time between switch presses by a human operator, the low bits of the counter can be used as a source of entropy. Another approach I've seen used is to measure how long it takes an analog PLL to lock. With any timing-based method, you can't get too many bits of entropy per event, or they won't be sufficiently random.Article: 129711
In the Fitting properties, there's also "Logic optimization" which defaults to speed; you can set it to Density instead.Article: 129712
I have written a process to generate random numbers using UNIFORM. I was trying to check the results using "rand" in matlab. How do i initialise the seed values of both these functions to the same value. I see that the random numbers generated by UNIFORM are different compared to rand when the seed values are left uninitialised. What do I need to change so that I get same output from both programs. ThanksArticle: 129713
Antti <Antti.Lukats@googlemail.com> writes: > 2) devices packages like Spartan-3E (including QN132 !) or better > (microBGA 6x6 mm?) I keep wondering if there's a market for a few "unbalanced" devices, like something with a ton of gates but in a tqfp-64 package. Or BGA packages that only use the two outer rows for signals, for simpler board routing. Likewise, I'd like to see the occasional MCU with a ton of ram and a little flash, rather than the other way as it usually is. Every once in a while I need a smart buffer chip :-(Article: 129714
I didn't mention earlier, ALL steps were done with optimization set for "Density". If the optimization was set for "Speed", I would expect resource utilization to increase. It is the fact that ALL optimizations are set for "DENSITY" and the resource utilization is increasing that has me concerned. "DJ Delorie" <dj@delorie.com> wrote in message news:xnve43a4xz.fsf@delorie.com... > > In the Fitting properties, there's also "Logic optimization" which > defaults to speed; you can set it to Density instead.Article: 129715
"Antti" <Antti.Lukats@googlemail.com> schrieb im Newsbeitrag news:467475ec-6d16-4789-acec-07d3c1a4977e@s19g2000prg.googlegroups.com... > here it is: > > 1) devices densities like in Spartan-3 (50..5000) > 2) devices packages like Spartan-3E (including QN132 !) or better > (microBGA 6x6 mm?) > 3) all good features of S3A/AN !! > 4) design security with OTP encryption key (like Lattice ECP2) > 5) other features as already planned by Xilinx > > Antti > has made his Christmas wish this year... or did I just describe > Lattice XP3 or Cyclone IV? > eh, I just wish Spartan-4 will have all the good things from Spartan-3 > subfamilies+extra goodies. > > > Hi Antti, I've the same wishes, some additional i/O & memory cores would be nice: 6) USB2 host/slave interface with integrated PHY 7) Ethernet MAC + PHY 8) DDR2/3 core 9) some analog stuff (ADC, temp sensor, system supervisor) S4 would be a serious competitor to 32bit microcontrollers, if some of their standard peripherals are included in low price FPGA's. MIKEArticle: 129716
On 3 Mrz., 22:16, DJ Delorie <d...@delorie.com> wrote: > Antti <Antti.Luk...@googlemail.com> writes: > > 2) devices packages like Spartan-3E (including QN132 !) or better > > (microBGA 6x6 mm?) > > I keep wondering if there's a market for a few "unbalanced" devices, > like something with a ton of gates but in a tqfp-64 package. Or BGA > packages that only use the two outer rows for signals, for simpler > board routing. > > Likewise, I'd like to see the occasional MCU with a ton of ram and a > little flash, rather than the other way as it usually is. Every once > in a while I need a smart buffer chip :-( oh yes, TQFP48 0.5mm pitch FPGA running from single voltage! defenetly, but hey thats wish for new Lattice device ;) BTW, Actel QFN132 3 row QFN 0.5mm pitch CAN be used on 2 layer PCB or even single layer. AnttiArticle: 129717
Kolja, You could distribute some slow clock and generate your fast clocks on each board independently with high quality PLLs but that's not a pure passive solution you've asked for... /MikhailArticle: 129718
"M.Randelzhofer" <techseller@gmx.de> wrote: >"Antti" <Antti.Lukats@googlemail.com> schrieb im Newsbeitrag >news:467475ec-6d16-4789-acec-07d3c1a4977e@s19g2000prg.googlegroups.com... >> here it is: >> >> 1) devices densities like in Spartan-3 (50..5000) >> 2) devices packages like Spartan-3E (including QN132 !) or better >> (microBGA 6x6 mm?) >> 3) all good features of S3A/AN !! >> 4) design security with OTP encryption key (like Lattice ECP2) >> 5) other features as already planned by Xilinx >> >> Antti >> has made his Christmas wish this year... or did I just describe >> Lattice XP3 or Cyclone IV? >> eh, I just wish Spartan-4 will have all the good things from Spartan-3 >> subfamilies+extra goodies. >> >> >> > >Hi Antti, > >I've the same wishes, some additional i/O & memory cores would be nice: > >6) USB2 host/slave interface with integrated PHY > >7) Ethernet MAC + PHY > >8) DDR2/3 core > >9) some analog stuff (ADC, temp sensor, system supervisor) > >S4 would be a serious competitor to 32bit microcontrollers, if some of their >standard peripherals are included in low price FPGA's. You forget a standard ARM core, some internal flash (say 32KB to 256KB), some memory (8KB to 64KB) and some standard pheripherals like UART, SPI, I2C. Such a device would be a real killer. I would design it in straight away if it existed today for a Spartan price. -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)Article: 129719
DJ Delorie <dj@delorie.com> wrote: >Antti <Antti.Lukats@googlemail.com> writes: >> 2) devices packages like Spartan-3E (including QN132 !) or better >> (microBGA 6x6 mm?) >I keep wondering if there's a market for a few "unbalanced" devices, >like something with a ton of gates but in a tqfp-64 package. Or BGA >packages that only use the two outer rows for signals, for simpler >board routing. I also like the large logic core, small package idea. And a builtin optional linear regulator for those pesky 2.5V and 1.2V would be really nice. Add some builtin eeprom for the bitstream (like Spartan-3 AN).Article: 129720
Antti wrote: > here it is: > > 1) devices densities like in Spartan-3 (50..5000) > 2) devices packages like Spartan-3E (including QN132 !) or better > (microBGA 6x6 mm?) > 3) all good features of S3A/AN !! > 4) design security with OTP encryption key (like Lattice ECP2) > 5) other features as already planned by Xilinx Supposedly Spartan4 will have RocketIOs/GTPs. Or at least there will be a flavour that will have them, so maybe PCIe and SGMII for Gigabit Ethernet? To me this sounds an awful lot like "We need something like the Lattice ECP2/M!", just like the Spartan3-AN sounds a lot like "We need something like the Lattice XP/XP2!". Lattice must've struck a nerve with those two families, they found their niche of devices Xilinx doesn't really cover (yet)... BTW, ECP3 is on its way, but supposedly will be not much more than a die shrink of the ECP2. cu, Sean -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 129721
Make a ring counter which nearly oscillates at 1/1024th (say) frequency as your off-chip clock. Divide the external clock by 1024, then compare and count the phase difference in clock cycles. Hey presto a random number ! (well nearly) which is different every time you switch on. "Aragorn" <me.aragorn@gmail.com> wrote in message news:37a00fd4-62e6-402e-a12f-6b9f94597607@s12g2000prg.googlegroups.com... > Hi > I am new to this group. I am an undergraduate student working on an > implementation of RSA on an FPGA. I am using a LFSR for random number > generation, but I also need a random state of the LFSR to begin with, > don't I? How do I get that? What does one do in such a case? I don't > want to restart the whole random no. generation business with a new > method!! > > I want the user to get a different key each time he uses the key > generation system. > > ThanksArticle: 129722
David Binnie wrote: > Make a ring counter which nearly oscillates at 1/1024th (say) frequency as > your off-chip clock. > > Divide the external clock by 1024, then compare and count the phase > difference in clock cycles. > > Hey presto a random number ! (well nearly) which is different every time > you switch on. > > "Aragorn" <me.aragorn@gmail.com> wrote in message > news:37a00fd4-62e6-402e-a12f-6b9f94597607@s12g2000prg.googlegroups.com... > >>Hi >> I am new to this group. I am an undergraduate student working on an >>implementation of RSA on an FPGA. I am using a LFSR for random number >>generation, but I also need a random state of the LFSR to begin with, >>don't I? How do I get that? What does one do in such a case? I don't >>want to restart the whole random no. generation business with a new >>method!! >> >>I want the user to get a different key each time he uses the key >>generation system. >> >>Thanks > > > You have to be careful using a ring oscillator on-chip, as chip parasitics will cause it to sync up to other clocks on the chip, and you will lose randomness. That said, as long as you use the ring oscillator right at start-up before it has an opportunity to lock to the system clock, you will probably be OK. Alternatively, if you have two independent external clocks, you can use a divided version of one to capture the state of a toggle flip-flop clocked by the other (or a divided version of the other) to determine if there are an even or odd number of clocks between successive edges. Assuming the two clocks are truely asynchronous to one another, you will get a good quality one bit random for each event. Use successive events to assemble a parallel seed value (note for an LFSR you can just clock the bits in as they occur, so there is no need to deserialize it. Additionally, the LFSR only produces one new pseudo-random bit for each clock, so if you need more than a 1 bit random, you need to operate the LFSR for the number of clock cycles equal to number of bits you need. Obviously, the LFSR has to have a long enough sequence so that only a small fraction of the cycle is completed within your longest observation window in order for the bits to appear random. If your clocks really are de-correlated, then you don't need the LFSR at all, you can just use the odd/even timing measurement of the successive edges between the two clocks and get a good random.Article: 129723
DJ Delorie wrote: > I keep wondering if there's a market for a few "unbalanced" devices, > like something with a ton of gates but in a tqfp-64 package. Or BGA > packages that only use the two outer rows for signals, for simpler > board routing. I have seen more often need for a huge package and very little logic. Nowadays I have seen that at networking side many designs are becoming I/O limited and the pinouts are more and more complex to do because of all restrictions what can be in what FPGA bank etc. Hopefully serial interfaces will help in this problem (high speed serial interfaces to memories etc.). But this on the other hand needs also low cost FPGAs with decent amount of tranceivers. --KimArticle: 129724
Hi friends
Can u please help me in reconfiguring virtex 2 pro board... Pls
give an example and steps to reconfigure virtex 2 pro.. I am using
Xilinx 8.2 i version software.. If u have some codes please send it
and help me in working out reconfiguration in Virtex 2 pro ...
More over how to use the xilinx 8.2i software for
reconfiguration..
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