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rickman wrote:
> All I need to know is how the Lattice ispLever tool is told the order
> to compile the files.
http://www.latticesemi.com/products/designsoftware/isplever/ispleverstarter/index.cfm
Looks like you have the choice of Synplify or Precision.
Probably an ordered file list for these.
Check the docs.
-- Mike Treseler
Article: 129351On 21 Feb., 20:00, austin <aus...@xilinx.com> wrote: > Antti, > > The 3A configuration bits have potential to "glitch" when reconfigured, > so one has to carefully select what to reconfigure, and then make sure > it works as desired. > > So, yes, you can physically do it, but it may not perform as desired. > > This is different in Virtex devices, where it is fully supported (or a > full as we can be right now). > > Austin kill the glitch-bitch! ok, things there are things potentially doabl (but not recommended) and things really doable and working , AnttiArticle: 129352
Antti, Yes. For example, if you stopped the system clock, reconfigured, and started the clock again, that would probably work just fine. It was decided (long ago) that some features were more important to some customers, and since Spartan parts are concerned with: cost, cost, cost (in order of importance), things like reconfigurability are reserved for the Virtex line (where we are not so greatly constrained). AustinArticle: 129353
Sky465nm@trline5.org wrote: >>LFSRs are fine for a psuedo-random sequence. If it needs to be truely >>random however (such as with crypto), an LFSR is not suitable because >>the output is predictable given the history. If you do use an LFSR, >>take only one bit per clock of the LFSR, as the bits are highly >>correlated in the shift register. > > > Maybe one could exploit gated clocks, signal races, metastability etc.. to > get randomness without resorting to hardware? (like transistor white noise). > > I think Jenny tried using ring oscillators to get a seed, but found that given enough time the ring oscillators sync'ed up thanks to parasitics. I was hoping she'd post here and maybe provide a link to her thesis.Article: 129354
Hi I just came across some interview questions for digital design, and would like to discuss my solutions with you! #Design a circuit to divide input frequency by 2 I could do this with a Toggle Flip flop where the inverted output is connected to the input, then i also divide the clock frequency by two # Design a divide-by-3/divide-by-5 sequential circuit with 50% duty cycle. I was thinking of having here a statemachine that outputs for 3 cycles 0, and then it changes the state to output 3 times a 1 at each clock transition. # Which one is superior: Asynchronous Reset or Synchronous Reset Well, until now I was always using asynchronous resets because u find it in most textbooks ;) not so sure about the right answer here!Article: 129355
Ray Andraka wrote: > Sky465nm@trline5.org wrote: > >>> LFSRs are fine for a psuedo-random sequence. If it needs to be >>> truely random however (such as with crypto), an LFSR is not suitable >>> because the output is predictable given the history. If you do use >>> an LFSR, take only one bit per clock of the LFSR, as the bits are >>> highly correlated in the shift register. >> >> >> >> Maybe one could exploit gated clocks, signal races, metastability >> etc.. to >> get randomness without resorting to hardware? (like transistor white >> noise). >> >> > > I think Jenny tried using ring oscillators to get a seed, but found that > given enough time the ring oscillators sync'ed up thanks to > parasitics. I was hoping she'd post here and maybe provide a link to > her thesis. That would always be a risk, but you could use multiple ring-osc, and run them one at a time ? I did find them to be very good thermometers :) Targeting the metastable window would be another approach, but that seems to be very narrow. Be interesting to see plots of time/aperture width .. -jgArticle: 129356
Clemens Blank schrieb: > Interview questions and the best one I came across was to double the clock frequency. How on earth should this be possible, must be a trap!Article: 129357
Peter Alfke wrote: > On Feb 21, 5:17 am, auguste.chin...@googlemail.com wrote: >> Hallo, >> ich arbeite seit 3 Monaten mit einem Xilinx Ml405 Virtex 4 Board und >> wollte darauf nun mal ein Software Defined Radio (SDR) >> implementieren. >> Ich verstehe alles was auf SDR betrifft (Theorie, Funktionsweise, >> etc..) >> ganz gut . Genauso kann ich auch VHDL und VERILOG. >> Jetzt würde ich gerne wissen, ob Jemand sich damit auch beschäftigt >> einem SDR >> auf oben genanntem Board (oder anderen) zu implementieren zweck >> Erfahrungsaustauch. >> >> Im folgenden einem detaillierten Überblick über was ich bis jetzt >> gemacht habe: >> >> Zunächst strebe ich nur mal den Empfang von AM Signal an, damit man >> auch etwas zum Vorführen hat. >> >> Hardwaremäßig ist auf dem Board einiges da: einer DA-Wandler (LM4550) >> von National und einer externen AD-Wandler (LTC2208) von Linear >> Technology. Ich habe bereit alle Software entwickelt >> (ADC.vhd,DAC.vhd, >> DDC.vhd,...). Nun muss ich meine Signale testen: und zwar mit einem >> Funktionsgenerator möchte ich einem Sinus erzeugen, danach den Sinus >> mit der FPGA verarbeiten durch die AD und DA -Wandler . Allerding >> sollte >> ich die gleiche Signale wieder empfangen. >> >> Beispiel.: >> Sinus(1Khz)----> ADC-->FPGA--->DAC--->Sinus(1Khz) >> Ich kann schon etwas am Ausgang (nach der DA-Wandler) mit dem >> Kopfhörer >> hören. Allerdings könnte ich das mit dem Oszilloskop nicht messen . >> Ich >> habe schon vieles ausprobiert ohne Erfolg und frage wo das Problem >> liegen kann? Ob es am Downsampling liegt oder eher an einer >> Clockstörung? >> >> Hat Jemand vielleicht eine Idee oder einem Tipp für mich?? >> >> Ich freue mich auf alle Vorschläge und bedanke mich im Voraus.. >> >> Chindji > > Chindji,die Sprache in dieser Gruppe ist Englisch. Ich vermute, dass > nur ein paar Prozent der Teilnehmer Deutsch beherrschen, und es ist ja > offensichtlich auch nicht Deine Muttersprache. Englisch ist nun mal > die "lingua franca" dieser Industrie und Technologie. > > Z.Zt. schlaegst Du Dich mit sehr einfachen Problemen herum. Ich > schlage vor, dass Du Dich mit einem Kollegen oder Kommilitonen > zusammensetzst, um mit Deinem Projekt voranzukommen. > Viel Erfolg ! > Peter Alfke, Xilinx Applications Engineering Nach zwanzig Jahren haben wir nicht entschieden, welche HDL-Sprache das "lingua franca" ist. Der Babel-Turm ist nicht zu vermeiden. Solange wir mehrere HDL-Sprachen verwenden, gibt's keinen Grund warum wir nicht mehrere menschliche Sprachen verwenden sollen! Vielleicht koennten wir nun entscheiden: zum menschliche Sprache, English, und zum HDL-Sprache, SystemVerilog. Hat jemand was dagegen? -Kevin, XilinxArticle: 129358
Can't possibly be a single language board, we let VHDL, and Verilog users both post here. :-) <MikeShepherd564@btinternet.com> wrote in message news:rrerr35plpppgllrpj4op09j4ksf3rlavm@4ax.com... > >Chindji,die Sprache in dieser Gruppe ist Englisch. Ich vermute, dass >>nur ein paar Prozent der Teilnehmer Deutsch beherrschen, und es ist ja >>offensichtlich auch nicht Deine Muttersprache. Englisch ist nun mal >>die "lingua franca" dieser Industrie und Technologie. >> >>Z.Zt. schlaegst Du Dich mit sehr einfachen Problemen herum. Ich >>schlage vor, dass Du Dich mit einem Kollegen oder Kommilitonen >>zusammensetzst, um mit Deinem Projekt voranzukommen. >>Viel Erfolg ! >>Peter Alfke, Xilinx Applications Engineering > > If he's more comfortable with German then let him write in German, > whether or not it's his native language. Of course, there may be, as > you say, few who understand him and can reply. I know almost no > German, but that's my loss as much as his. > > If I see here a language I don't understand, I just ignore it. > > If this is a "single-language" group, I'm in the worng place. I don't > do segregation. > > MikeArticle: 129359
On Feb 21, 2:44=A0pm, Kevin Neilson <kevin_neil...@removethiscomcast.net> wrote: > Peter Alfke wrote: > > On Feb 21, 5:17 am, auguste.chin...@googlemail.com wrote: > >> Hallo, > >> ich arbeite seit 3 Monaten mit einem Xilinx Ml405 Virtex 4 Board und > >> wollte darauf nun mal ein Software Defined Radio (SDR) > >> implementieren. > >> Ich verstehe alles was auf SDR betrifft (Theorie, Funktionsweise, > >> etc..) > >> ganz gut . Genauso kann ich auch VHDL und VERILOG. > >> Jetzt w=FCrde ich gerne wissen, ob Jemand sich damit auch besch=E4ftigt= > >> einem SDR > >> auf oben genanntem Board (oder anderen) zu implementieren zweck > >> Erfahrungsaustauch. > > >> Im folgenden einem detaillierten =DCberblick =FCber was ich bis jetzt > >> gemacht habe: > > >> Zun=E4chst strebe ich nur mal den Empfang von AM Signal an, damit man > >> auch etwas zum Vorf=FChren hat. > > >> Hardwarem=E4=DFig ist auf dem Board einiges da: einer DA-Wandler (LM455= 0) > >> von National und einer externen AD-Wandler (LTC2208) von Linear > >> Technology. Ich habe bereit alle Software entwickelt > >> (ADC.vhd,DAC.vhd, > >> DDC.vhd,...). Nun muss ich meine Signale testen: und zwar mit einem > >> Funktionsgenerator m=F6chte ich einem Sinus erzeugen, danach den Sinus > >> mit der FPGA verarbeiten durch die AD und DA -Wandler . Allerding > >> sollte > >> ich die gleiche Signale wieder empfangen. > > >> Beispiel.: > >> Sinus(1Khz)----> ADC-->FPGA--->DAC--->Sinus(1Khz) > >> Ich kann schon etwas am Ausgang (nach der DA-Wandler) mit dem > >> Kopfh=F6rer > >> h=F6ren. Allerdings k=F6nnte ich das mit dem Oszilloskop nicht messen .= > >> Ich > >> habe schon vieles ausprobiert ohne Erfolg und frage wo das Problem > >> liegen kann? Ob es am Downsampling liegt oder eher an einer > >> Clockst=F6rung? > > >> Hat Jemand vielleicht eine Idee oder einem Tipp f=FCr mich?? > > >> Ich freue mich auf alle Vorschl=E4ge und bedanke mich im Voraus.. > > >> Chindji > > > Chindji,die Sprache in dieser Gruppe ist Englisch. Ich vermute, dass > > nur ein paar Prozent der Teilnehmer Deutsch beherrschen, und es ist ja > > offensichtlich auch nicht Deine Muttersprache. Englisch ist nun mal > > die "lingua franca" dieser Industrie und Technologie. > > > Z.Zt. schlaegst Du Dich mit sehr einfachen Problemen herum. Ich > > schlage vor, dass Du Dich mit einem Kollegen oder Kommilitonen > > zusammensetzst, um mit Deinem Projekt voranzukommen. > > Viel Erfolg ! > > Peter Alfke, Xilinx Applications Engineering > > Nach zwanzig Jahren haben wir nicht entschieden, welche HDL-Sprache das > "lingua franca" ist. =A0Der Babel-Turm ist nicht zu vermeiden. =A0Solange > wir mehrere HDL-Sprachen verwenden, gibt's keinen Grund warum wir nicht > mehrere menschliche Sprachen verwenden sollen! > > Vielleicht koennten wir nun entscheiden: =A0zum menschliche Sprache, > English, und zum HDL-Sprache, SystemVerilog. =A0Hat jemand was dagegen? > -Kevin, Xilinx- Hide quoted text - > > - Show quoted text - I appreciate the variety of both HDLs and human languages. While a VHDL to Verilog translator typically runs thousands of US$, a free website I use for the other language issues translate.google.com is very helpful. It seems the original post has to do with troubleshooting a design in a real system. There isn't much to suggest here since there is so much that *can* go wrong. Only by applying debug techniques with controllability and observability at appropriate points to effectively partition the design can the trouble be found. Coding problems might be obvious to the casual (trained) observer, but "it's broke" often gets us nowhere. I can suggest using test points at various points through the design - perhaps even ChipScope - to figure out if everything is progressing as expected until something breaks. Gesundheit, - John_HArticle: 129360
Hi All, I have started a test design in Modelsim Designer. I now have one entity written in VHDL and have placed this entity on a block diagram and added in- and out ports to the entity's signals. The entity simulates OK in a testbench and synthesis is OK (no constraints but 100MHz clock given). Placing all signals on an I/O pin is easy with the PACE tool for 'normal' signals. But I can't figure out how to use a bi-directional differential buffer. My entity has 3 signals for use with this buffer: in, out, output_enable And I want to connect these signals to a Bus-LVDS I/O buffer, but how? Preferrably also using the input synchronization. Next problem is the clock input. There's a 50MHz oscillator connected to a clock input and I want to use the DCM to create a 100MHz (or even a 150MHz) global clock off of that. I've searched the web and the Mentor and Xilinx sites, but found nothing yet. Any hints how to do this or where to look for more information? The Modelsim manuals are reasonable upto and including the simulation, but fail after that. I know the synthesis and P&R are actually performed by Xilinx tools, but they could have made an effort taking you through the whole process as the offer complete integration. Or did I overlook some manual or tutorial? Xilinx on the other hand, only document the ISE design route, so it seems I'm stuck somewhere in the middle. First goal is to get the design running on the S3E starter kit. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) "Computers in the future may weigh no more than 1.5 tons." (Popular Mechanics, 1949)Article: 129361
Clemens Blank wrote: > Clemens Blank schrieb: >> Interview questions > > and the best one I came across was to double the clock frequency. How on > earth should this be possible, must be a trap! For the question about dividing the frequency by two, be sure to note that you wouldn't use the resulting output as a (gated) clock! To double a frequency the best method is to use a PLL, but this requires some analog components. A DLL works well, but is jittery. A simple dirty method requires just an XOR and a delay element, but that's not a good synchronous design practice. -KevinArticle: 129362
On Feb 21, 2:26=A0pm, Clemens Blank <CBl...@hotmail.com> wrote: <snip> > > # Design a divide-by-3/divide-by-5 sequential circuit with 50% duty cycle.= > I was thinking of having here a statemachine that outputs for 3 cycles > 0, and then it changes the state to output 3 times a 1 at each clock > transition. > <snip> Having a state machine with three high states followed by 3 low states is a divide by 6, not a divide by 3! The trick here to getting a 50% duty cycle output is to know that you need the positive edge of the incoming clock to control the rising edge of the output clock and the negative edge to control the falling (or vice-versa). This assumes, of course, that the input clock is 50%. Since most registers can't toggle on both posedge clk and negedge clock in the same flop, the output has to be a combinatorial result from the two edge domains. - John_HArticle: 129363
Stef wrote:
> I have started a test design in Modelsim Designer. I now have one entity
> written in VHDL and have placed this entity on a block diagram and added
> in- and out ports to the entity's signals. The entity simulates OK in a
> testbench and synthesis is OK (no constraints but 100MHz clock given).
Good work.
> Placing all signals on an I/O pin is easy with the PACE tool for 'normal'
> signals. But I can't figure out how to use a bi-directional differential
> buffer.
Your vhdl source and testbench is incomplete.
Add code to infer and test the bidirectional buffer.
related example:
http://home.comcast.net/~mike_treseler/oe_demo.vhd
Pin numbers and I/O selection is best done
at the back end, not it the source code or simulation.
> Next problem is the clock input. There's a 50MHz oscillator connected to
> a clock input and I want to use the DCM to create a 100MHz (or even a
> 150MHz) global clock off of that.
Consider leaving it at 50 Mhz for the first proto.
PLLs and DCMs are fussy vendor-specific black boxes.
-- Mike Treseler
Article: 129364If the converters are AC coupled, DC won't get through them. I prefer testing with AC for that reason. He can perhaps put a signal generator in the FPGA (a CORDIC will work nicely) to drive the DAC to get the output side tested. Make sure the clocks and any data enables are getting through to the converters. Also, make sure that any set-up to the converters has been done properly (many use a serial interface to set up parameters, and won't operate until you've programmed something into them). Unfortunately, I've never learned any German, so I'll have to count on someone else to translate this for Chindqi. austin wrote: > Chindgi, > > I apologize for not replying in German, my written German is worse than > my spoken German, which is only at grammer school level. > > It seems like you have the conversion of the analog sine wave to digital > (AD), and conversion back again (DA) working in both VHDL, and hardware, > yet you say you can not see anything on the oscilloscope. > > First, did you simulate the design? Does the simulation test bench work? > > Second, are you able to input, and output static (unchanging) DC > voltages? This would be my first test, before I tried AC (sine waves). > > If this is an issue with clocking (sampling), the DC will work, and then > the AC will have issues with frequency response (just guessing). > > If the DC does not work, then I would use a logic analyzer (if it is > Xilinx, Chipscope(tm) is soft IP that may be part of your design, and > allows you to probe your digital signals inside the FPGA and see if they > are what you expect in the DC case). > > http://www.xilinx.com/ise/optional_prod/cspro.htm > > Perhaps a German speaker will be more helpful to reply, > > > > AustinArticle: 129365
Jim Granville wrote: > Ray Andraka wrote: > >> Sky465nm@trline5.org wrote: >> >>>> LFSRs are fine for a psuedo-random sequence. If it needs to be >>>> truely random however (such as with crypto), an LFSR is not suitable >>>> because the output is predictable given the history. If you do use >>>> an LFSR, take only one bit per clock of the LFSR, as the bits are >>>> highly correlated in the shift register. >>> >>> >>> >>> >>> Maybe one could exploit gated clocks, signal races, metastability >>> etc.. to >>> get randomness without resorting to hardware? (like transistor white >>> noise). >>> >>> >> >> I think Jenny tried using ring oscillators to get a seed, but found >> that given enough time the ring oscillators sync'ed up thanks to >> parasitics. I was hoping she'd post here and maybe provide a link to >> her thesis. > > > That would always be a risk, but you could use multiple ring-osc, and > run them one at a time ? > > I did find them to be very good thermometers :) > > Targeting the metastable window would be another approach, but that > seems to be very narrow. > Be interesting to see plots of time/aperture width .. > > -jg > I think one approach she was looking at was a high order LFSR seeded by a state machine that divined the phase difference between a pair of ring oscillators. The idea was to obtain a random seed before the ring oscillators got a chance to sync up, and then use the LFSR to get the random sequence. The seeding is necessary to get a random start point in the LFSR. Still, that doesn't give a true random. I know she was looking for techniques that would pass a battery of randomness tests, and very few approaches actually did. I'll give her a call to try to get her to speak up here, and maybe put her thesis up on the 'net somewhere.Article: 129366
On Feb 22, 9:34=A0am, John_H <newsgr...@johnhandwork.com> wrote: > On Feb 21, 2:26=A0pm, Clemens Blank <CBl...@hotmail.com> wrote: > <snip> > > > # Design a divide-by-3/divide-by-5 sequential circuit with 50% duty cycl= e. > > I was thinking of having here a statemachine that outputs for 3 cycles > > 0, and then it changes the state to output 3 times a 1 at each clock > > transition. > > <snip> > > Having a state machine with three high states followed by 3 low states > is a divide by 6, not a divide by 3! > > The trick here to getting a 50% duty cycle output is to know that you > need the positive edge of the incoming clock to control the rising > edge of the output clock and the negative edge to control the falling > (or vice-versa). =A0This assumes, of course, that the input clock is > 50%. > > Since most registers can't toggle on both posedge clk and negedge > clock in the same flop, the output has to be a combinatorial result > from the two edge domains. > > - John_H About clock divider http://www.onsemi.com/pub/Collateral/AND8001-D.PDFArticle: 129367
"austin" <austin@xilinx.com> wrote in message news:47BCF034.5080007@xilinx.com... > Mikhail, > > Only in terms of the number of paralleled output devices selected. > > If you wish 8 mA min drive at 2.5v Vcco, the number of drivers will be > stronger than that at 3.0, or 3.3 v. Conversely, if 8mA is selected for > 3.3v, it will be weaker at 3.0 or 2.5v. > > The hspice models on the website will predict actual results from real > silicon, whereas the IBIS models do not allow for changing Vcco. > > Regardless, simulating 8 mA at 3.3v slow/weak corner in IBIS will give you > some idea of what the typical will be with 3.0 volts. > > A 10% change in Vcco is roughly the same as the difference from slow/weak > to typical, or typical to fast/strong(in IBIS). > > Austin > > Austin Austin, Please set up a web-based interface to your (Xilinx) copy of HSPICE for us peons that work for companies that can't or won't purchase their own $100k version of HSPICE. Thanks in advance, BobArticle: 129368
On Feb 22, 2:17 am, austin <aus...@xilinx.com> wrote: > Antti, > > Yes. For example, if you stopped the system clock, reconfigured, and > started the clock again, that would probably work just fine. > > It was decided (long ago) that some features were more important to some > customers, and since Spartan parts are concerned with: cost, cost, cost > (in order of importance), things like reconfigurability are reserved for > the Virtex line (where we are not so greatly constrained). > > Austin Hi. Thanks for replying so soon. Is there a detailed explanation for the demo (OUT-OF-BOX) as I think that demo program uses the reconfigurability of s3a by accessing the on board PROMs? The demo uses a Picoblaze controller to select the confign from the specific PROM. Does the FPGA reset everytime it is configured from the PROM? ParunoyArticle: 129369
Hi again,
Actually what i currently want to do is:
1. divide the fpga into 2 parts
a) one part will have picoblaze controller.
b) other will have an up counter.
2. Save a partial file for down counter (generated from difference
based partial reconfiguration option) in one of the ROMs.
3. Run the up counter initially and then using picoblaze call the
partial file from the ROM to reconfigure the UP counter to a DOWN one.
Now the BIG question:Is it possible using Spartan 3a? Can multiboot
option be used for it or any other way possible?
Or should i go for Virtex??]
Regards,
Parunoy.
Article: 129370On 22 Feb., 10:01, puneetjamr...@gmail.com wrote: > On Feb 22, 2:17 am, austin <aus...@xilinx.com> wrote: > > > Antti, > > > Yes. For example, if you stopped the system clock, reconfigured, and > > started the clock again, that would probably work just fine. > > > It was decided (long ago) that some features were more important to some > > customers, and since Spartan parts are concerned with: cost, cost, cost > > (in order of importance), things like reconfigurability are reserved for > > the Virtex line (where we are not so greatly constrained). > > > Austin > > Hi. > > Thanks for replying so soon. > Is there a detailed explanation for the demo (OUT-OF-BOX) as I think > that demo program uses the reconfigurability of s3a by accessing the > on board PROMs? The demo uses a Picoblaze controller to select the > confign from the specific PROM. Does the FPGA reset everytime it is > configured from the PROM? > > Parunoy yes, the FPGA will go FULL reset and re-configuration cycle during triggered multi-boot AnttiArticle: 129371
On Feb 21, 8:46 pm, austin <aus...@xilinx.com> wrote: > mp, > > An IO programmed for a specific Vcco as LVCMOS will function at any > higher Vcco applied to the bank. The input threshold depends on the > Vcco voltage to the bank (~ 1/2 Vcco), so that is not an issue. > > The only concern is that a 8 mA slow IO at 1.5 volts, may be a 24 mA > fast IO at 3.3 volts (too many output drivers enabled at a lower voltage > to meet current requirement). > > You would have to consider the signal integrity, and be sure this will > meet your needs. > > Again, it will function as desired, but SI may not be what you want. > > I suggest setting the IO for something like 8 mA slow at 1.8, or 2.5 > volts, and then seeing how they look at 1.5 and 3.3 volts. Split the > difference (compromise). > > Austin Thanks Austin, looks like we need to do some characterization once the boards are ready and come up with drive strengths and slew rates. Thanks -mpArticle: 129372
> Hi , > =A0 =A0 =A0 I have assigned 64k of local memory. > Is there an alternative to this problem im facing. Allocate more memory or try iscanf, which is an integer only version of scanf, that should require less code space. (There should be iprintf too). Cheers, JonArticle: 129373
Hello, Let me right again in this forum on the same topic. But know in English. Whatever my English is very poor. I am working for about 4 month's ego with an ML405 Xilinx Virtex 4 board and I wanted now to implement a Software Defined Radio (SDR). I understand everything that relates to SDR (theory, operation, Etc..) Very good. Likewise, I also understand VHDL and VERILOG. Now I would like to know if someone is thus also employs An SDR Board on the above (or others) to implement appropriate Experience exchange. In following a detailed overview of what I Made now: First, I strive times only to receive an AM signal. Hardware is on the board as much: DA converter (LM4550) National and an external A / D converters (LTC2208) by Linear Technology. I have prepared all software developed (ADC.vhd, DAC.vhd, DDC.vhd ,...)I make already the simulation. Now, I must try my signals: and with a Function generator, I would like to generate a sine wave, and then the sine wave through the FPGA with the process by the AD and DA converters. I Am suppose to have the same signals again after the DAC. Example. Sine (1Khz) ----> ADC -> FPGA ---> DAC ---> sinus (1Khz) I can hear something (signal) at the output (by the DA converter) with the Headphones. However, I cannot measure it with the oscilloscope. I had already tried without much success, and ask what the problem Lie? Whether it down sampling, or rather in a Clock functions? Did someone get an idea or a tip for me? I look forward to all suggestions and thank you in advance... ChindjiArticle: 129374
>Jim Granville wrote: > >> Ray Andraka wrote: >> >>> Sky465nm@trline5.org wrote: >>> >>>>> LFSRs are fine for a psuedo-random sequence. If it needs to be >>>>> truely random however (such as with crypto), an LFSR is not suitable >>>>> because the output is predictable given the history. If you do use >>>>> an LFSR, take only one bit per clock of the LFSR, as the bits are >>>>> highly correlated in the shift register. >>>> >>>> >>>> >>>> >>>> Maybe one could exploit gated clocks, signal races, metastability >>>> etc.. to >>>> get randomness without resorting to hardware? (like transistor white >>>> noise). >>>> >>>> >>> >>> I think Jenny tried using ring oscillators to get a seed, but found >>> that given enough time the ring oscillators sync'ed up thanks to >>> parasitics. I was hoping she'd post here and maybe provide a link to >>> her thesis. >> >> >> That would always be a risk, but you could use multiple ring-osc, and >> run them one at a time ? >> >> I did find them to be very good thermometers :) >> >> Targeting the metastable window would be another approach, but that >> seems to be very narrow. >> Be interesting to see plots of time/aperture width .. >> >> -jg >> > > >I think one approach she was looking at was a high order LFSR seeded by >a state machine that divined the phase difference between a pair of ring >oscillators. The idea was to obtain a random seed before the ring >oscillators got a chance to sync up, and then use the LFSR to get the >random sequence. The seeding is necessary to get a random start point >in the LFSR. Still, that doesn't give a true random. I know she was >looking for techniques that would pass a battery of randomness tests, >and very few approaches actually did. I'll give her a call to try to >get her to speak up here, and maybe put her thesis up on the 'net >somewhere. > Have 'hash functions' been investigated? E.g.: http://www.cris.com/~Ttwang/tech/inthash.htm (Converting the code in the reference from Java to VHDL isn't difficult, but I am not allowed to post my version). For instance, use an LFSR to generate the inputs to the hash function, and use the output of the hash function as the 'random'. But the referenced article does suggest using the Mercenne Twister...
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