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On Feb 16, 12:40 am, wallge <wal...@gmail.com> wrote:
> I am looking at getting a new PC for doing FPGA development.
> I mostly use the altera tools and aldec active HDL.
>
> I was wondering if anyone had any thoughts or comments on
> optimal PC configurations for this.
>
> What affects synthesis time, place and route time -
>
> Cache size? SDRAM speed/bandwidth ,
> amount of total SDRAM (2 vs 4 vs 8 GB main memory).
> Do 32 vs 64 bit architectures make any difference at all?
> What about CPU clock speed -
> Is the price delta from a 2.0 GHz machine to a 3.2 GHz machine
> really worth it in terms of reducing compile times?
>
> What about multicore? Is it possible to have too many cores?
> is there an optimal number in terms of bang for the buck?
>
> Are there any advantages between the various Intel or AMD
> chip architectures?
>
> I know similar questions have been posed before,
> but I thought it would be good to revisit this, now that we are
> seeing the PC market flooded with new multicore processors,
> and EDA tool vendors starting to parallelize their algorithms to take
> advantage of the new CPUs.
CPU Intel Core2 Duo E8200 / E8400
MB ASUS P5K PRO 『http://0rz.tw/
773vW』
or Gigabyte EP35-DS3
RAM 2G DDR2-800 x 2
C2Q can do 4 QuartusII process for different versions in a project $_$
Article: 129176Stephen, I have had no trouble running a 2/3 full FX12-10 PLB bus with 4 devices at 100 Mhz. If you have a lot of random control/status type register access from the CPU, you can offload that onto the DCR bus. And try to use as large as possible burst transfers on the PLB bus. -JeffArticle: 129177
Our friend Antti is out of a job. Is there somebody in the Munich area who can offer a job, or some consulting ? I need not explain that Antti is a really sharp engineer with lots of FPGA experience. You all know that. You can reach him at antti.lukats@googlemail.com Peter Alfke, who posted this on his own, because he cannot stand a friend be so unhappy.Article: 129178
On Jan 31, 2:24=A0pm, jo...@mit.edu wrote: > Has anyone managed to get the xilinx BSCAN primitives (for interfacing > with the USERx jtag registers/comands) working robustly? I've found a > depressing lack of information as to what the actual pins =A0do -- aside > from a (now unavailable?) techXclusive article, "Reconfiguring Block > RAMs - Part 1" (by Kris Chaplin, available via google cache) I can't > find much more info. > > What's the best way to interface with this part? In particular, how do > you deal with the obvious synchronization/metastability issues when > crossing clock domains, esp. if you're hoping for a device that's > still small (i.e. no hardware async fifos or anything). > > Thanks for any advice you can provide, > =A0 =A0...Eric If you need a copy of this article - please let me know at chaplin <at> xilinx <dot> com Regards KrisArticle: 129179
On Sun, 17 Feb 2008 13:22:58 -0800 (PST), Peter Alfke wrote: >Our friend Antti is out of a job. That seems pretty unfair. >I need not explain that Antti is a really sharp engineer with lots of >FPGA experience. >You all know that. No dispute. I'm sure he knows already; but Antti needs to be aware that the DATE exhibition takes place at ICM (at the Munich exhibition centre in Riem) 10-13 March. It would be a good place to be visible to lots of interesting people in the FPGA and tools business, I think. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 129180
"Peter Alfke" <alfke@sbcglobal.net> wrote in message news:cc16e624-1612-49ba-bfc8-0a5da09a622f@h11g2000prf.googlegroups.com... > Our friend Antti is out of a job. > Is there somebody in the Munich area who can offer a job, or some > consulting ? > I need not explain that Antti is a really sharp engineer with lots of > FPGA experience. > You all know that. > > You can reach him at > > antti.lukats@googlemail.com > > Peter Alfke, who posted this on his own, because he cannot stand a > friend be so unhappy. Ask Antti if he wants to move to the northwest Los Angeles county area. I'm sure I could get him into a great company, AND, they're a very large user of Xilinx. BobArticle: 129181
On Feb 16, 6:08 pm, Bob Smith <use...@linuxtoys.org> wrote: > I work for a Linux software house and would like to offer a > "Hello, World!" tutorial for FPGAs. The idea is to keep it > simple and low cost. The Digilent Basys board looks good > for cost but not for (Linux) simplicity. I'd sure like to > avoid the windrv module and the parallel port cable. > > Does anyone know of a way to program the Basys board over > the USB cable using Linux? > > thanks > Bob Smith I don't know about that specific board, but there is an open-source user-space Linux driver for the Xilinx cables (USB and parallel). I am successfully using it with ISE Webpack 9.2i on Ubuntu 7.10 with a Spartan-3 board from Digilent. See http://rmdir.de/~michael/xilinx/ .Article: 129182
On Feb 17, 3:20=A0pm, "BobW" <nimby_NEEDS...@roadrunner.com> wrote: > "Peter Alfke" <al...@sbcglobal.net> wrote in message > > news:cc16e624-1612-49ba-bfc8-0a5da09a622f@h11g2000prf.googlegroups.com... > > > Our friend Antti is out of a job. > > Is there somebody in the Munich area who can offer a job, or some > > consulting ? > > I need not explain that Antti is a really sharp engineer with lots of > > FPGA experience. > > You all know that. > > > You can reach him at > > > antti.luk...@googlemail.com > > > Peter Alfke, who posted this on his own, because he cannot stand a > > friend be so unhappy. > > Ask Antti if he wants to move to the northwest Los Angeles county area. I'= m > sure I could get him into a great company, AND, they're a very large user = of > Xilinx. > > Bob Thanks, Bob, for the kind offer. I tend to discourage the idea of immigrating to the U.S. (funny, coming from me as an immigrant!) because of the horrible bureaucracy and visa delay. I had its easy in 1968, but now it is a nightmare. U.S. competitiveness is bound to suffer... Peter AlfkeArticle: 129183
Peter Alfke wrote: > On Feb 17, 3:20 pm, "BobW" <nimby_NEEDS...@roadrunner.com> wrote: >> "Peter Alfke" <al...@sbcglobal.net> wrote in message >> >> news:cc16e624-1612-49ba-bfc8-0a5da09a622f@h11g2000prf.googlegroups.com... >> >>> Our friend Antti is out of a job. >>> Is there somebody in the Munich area who can offer a job, or some >>> consulting ? >>> I need not explain that Antti is a really sharp engineer with lots of >>> FPGA experience. >>> You all know that. >>> You can reach him at >>> antti.luk...@googlemail.com >>> Peter Alfke, who posted this on his own, because he cannot stand a >>> friend be so unhappy. >> Ask Antti if he wants to move to the northwest Los Angeles county area. I'm >> sure I could get him into a great company, AND, they're a very large user of >> Xilinx. >> >> Bob > > Thanks, Bob, for the kind offer. I tend to discourage the idea of > immigrating to the U.S. (funny, coming from me as an immigrant!) > because of the horrible bureaucracy and visa delay. I had its easy in > 1968, but now it is a nightmare. U.S. competitiveness is bound to > suffer... > Peter Alfke I have sure-fire way to cut through the bureaucracy---come via Mexico.Article: 129184
"Rob" <buzoff@leavemealone.com> wrote in message news:ap5uj.4350$Sa1.698@news02.roc.ny... > Peter Alfke wrote: >> On Feb 17, 3:20 pm, "BobW" <nimby_NEEDS...@roadrunner.com> wrote: >>> "Peter Alfke" <al...@sbcglobal.net> wrote in message >>> >>> news:cc16e624-1612-49ba-bfc8-0a5da09a622f@h11g2000prf.googlegroups.com... >>> >>>> Our friend Antti is out of a job. >>>> Is there somebody in the Munich area who can offer a job, or some >>>> consulting ? >>>> I need not explain that Antti is a really sharp engineer with lots of >>>> FPGA experience. >>>> You all know that. >>>> You can reach him at >>>> antti.luk...@googlemail.com >>>> Peter Alfke, who posted this on his own, because he cannot stand a >>>> friend be so unhappy. >>> Ask Antti if he wants to move to the northwest Los Angeles county area. >>> I'm >>> sure I could get him into a great company, AND, they're a very large >>> user of >>> Xilinx. >>> >>> Bob >> >> Thanks, Bob, for the kind offer. I tend to discourage the idea of >> immigrating to the U.S. (funny, coming from me as an immigrant!) >> because of the horrible bureaucracy and visa delay. I had its easy in >> 1968, but now it is a nightmare. U.S. competitiveness is bound to >> suffer... >> Peter Alfke > > I have sure-fire way to cut through the bureaucracy---come via Mexico. > The real problem is the Canadians. You can't get an ice hockey job unless you were born in Canada. Bastards! BobArticle: 129185
On 2008-02-16, Steve <stephenry@gmail.com> wrote: > > I'm designing a platform on a Xilinx Virtex 4 FX60 chip and I am > somewhat conerned at the capabilities of the PLB bus in the system. One sample: V4 FX100-10, 75MHz PLB (connecting peripherals and MPMC2) and 225MHz PPC. The "theory" said 100MHz but that's what we got. There are higher speed grades that probably would have done 100MHz. -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 129186
On 2008-02-17, veriqiang@gmail.com <veriqiang@gmail.com> wrote: > > I'm currently facing a problem downloading my design to FPGA as my > design has overutilized the FPGA resources (slice and DSP48). I'm > using FIR compiler_v1 for both my lowpass and notch filter, Someone told me (though I have no experience with it myself) that the older versions of the FIR compiler did not take advantage of symmetry or other potential optimizations, but newer ones do. v1 doesn't sound new... -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 129187
Hi,
I want to interface on board ADC to spartan 3E startkit.
Actually I am developing digital filter in FPGA for that I need ADC
and DAC interface with Spartan 3E. I have done with DAC but now I want
to interface amplifier and ADC which are on board in Spartan 3E
starter kit .........If any one have it's VHDL or Verilog code please
give me..........Even I have find a document for implementing
amplifier and ADC usign picoblaze but I don't want it........So please
help me...............
Thank you,
Regards,
Krunal
Article: 129188krunal wrote: > I want to interface on board ADC to spartan 3E startkit. > Actually I am developing digital filter in FPGA for that I need ADC > and DAC interface with Spartan 3E. I have done with DAC but now I want > to interface amplifier and ADC which are on board in Spartan 3E > starter kit .........If any one have it's VHDL or Verilog code please > give me..........Even I have find a document for implementing > amplifier and ADC usign picoblaze but I don't want it........So please > help me............... Where do you have problems with the ADC? If you have already done the DAC, the ADC should be very similar, because both chips on the Spartan3E starter kit uses the SPI protocol and are from the same company. For some code to output something on the DAC, see this VHDL code: http://www.frank-buss.de/SignalGenerator/vhdl/spartan3e_test.vhd The DAC parts needs about 30 lines. Reading the LTC1407 ADC and controlling the LTC6912 amplifier is very similar. Maybe you can save some LUTs, if you are using the Picoblaze. Another interesting idea would be to implement some kind of very simple microcode to define which bytes needs to be transfered to which SPI ports and then using some BRAM (as ROM) to control it. But the Spartan 3E has many free LUTs, so you can do it in pure VHDL (but use functions and procedures to make the code less redundant). -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 129189
On 2008-02-16, Bob Smith <usenet@linuxtoys.org> wrote: > I work for a Linux software house and would like to offer a > "Hello, World!" tutorial for FPGAs. The idea is to keep it > simple and low cost. The Digilent Basys board looks good > for cost but not for (Linux) simplicity. I'd sure like to > avoid the windrv module and the parallel port cable. > > Does anyone know of a way to program the Basys board over > the USB cable using Linux? http://rmdir.de/~michael/xilinx/ has a windrv replacement library which you can LD_PRELOAD before starting impact. Personally I have used it exclusively instead of windrvr for a while now and it works perfectly with the platform USB cable. /AndreasArticle: 129190
>Symon, > >OK, I will go quiz the "experts." > >Not sure, but I do not think the "common large footprint" is a >'no-brainer' (common footprint fits all) for smaller parts (plugged onto >a layout for a larger part) in V4. > >Stand-by, > >Austin > Austin, Do you have any information? Thanks JonArticle: 129191
Hi I am making a time limited offer for full ownership rights sale for "XSIM Xilinx Platform Simulator" The simulator was developed in 2006, it was the first MicroBlaze software simulator able to run u-Boot and ucLinux. If I receive any serious offer, the complete source code and ownership rights will be sold as package. The binaries can be recompiled with new copyright and ownerhsip notes and graphics. The simulator and currently existing plugins are written with Delphi (Borland CodeGear). Plugins can be written in C too, and with CodeGear parts of simulator could also be in C/C++. The simulator has been used to troubleshoot and test u-Boot and uClinux drivers and standalone software. There are some set of plugins available for * TFT LCD controller * Nokia 6610 Display * CompactFlash (can mount raw image) * SD Card (can mount raw image) * I2C Real-time clock * Some other Please contact me per email with offer and/or questions. If I do not receive any offers at all, I will most likely offer the simulator myself as shareware. Antti LukatsArticle: 129192
Hi, and thanks for all your answers.. In fact, I had a lot of problem on this design for several month.. All my problems are due to the structure of the processor which seems to be asynchronous, uses keepers and tristates.. So, at the end of the last week, ( and thanks to Martin : "[...] the most important task before approaching a project was to really think about the representation of the problem [...]"), I decide to take two weeks to try something I thought since a long time : convert this strange design in full synchronous FPGA design.. You are going to tell me why didn't you do it before ?? and you should be right.. but this was due to the among of modifications required ( modify all the source files of the processor.. ) and the risk to obtain differents results from the original on silicium processor.. because the purpose of my design is to emulate the original processor.. So, thanks for your advices, Best regards, Michel.Article: 129193
Just had a look at the ML405 board schematics and it seems to indicate that the board can take an FX20, FX40 or FX60 device.Article: 129194
On Feb 17, 7:39=A0pm, Jeff Cunningham <j...@sover.net> wrote: > Stephen, > > I have had no trouble running a 2/3 full FX12-10 PLB bus with 4 devices > at 100 Mhz. > > If you have a lot of random control/status type register access from the > CPU, you can offload that onto the DCR bus. And try to use as large as > possible burst transfers on the PLB bus. > > -Jeff I had FX12 totally full, with only 2 point-to-point PLB busses connected to MPMC2 and PPC. For access to peripherals I used exclusively DCR (low logic resources and high responsiveness), for high bandwidth NPI port with 64 word transfers and CDMAC for LL_TEMAC. I recommend NPI for very high DMA bandwidth. Too bad that with EDK 9.2 the bus diversity is gone. You have to to use PLB in all cases. Cheers, AlesArticle: 129195
On Feb 14, 10:25=A0am, John Williams <jwilli...@itee.uq.edu.au> wrote: > Hi, > > muthu...@gmail.com wrote: > > Has anyone successfully portedPetalinuxin Microblaze (ML505) and > > There's an ML506 reference design inPetaLinuxv0.30, which should be > fairly simple to modify to run on a ML505. > > > used the SATA AHCI driver? > > Is the AHCI driver fromPetalinuxdistribution working OK? > > I'm not aware of anyone using it - it is jsut the same driver from a > standard 2.6.20 kernel. =A0Assuming you've got a working PCI layer up and > running, I wouldn't expect great difficulties with the AHCI driver. > > Regards, > > John Could you please point me to the Xilinx reference design that uses Petalinux. Sorry, I couldn't find it.Article: 129196
Hello Guys, How to specify with XST that an input of a VHDL entity is a clock ? I guess it is not automatic because after the XST logic synthesis, noone of my "process" have been synthetized ? thanks, JulienArticle: 129197
On Feb 18, 9:17=A0am, Julien Lochen <loc...@noos.fr> wrote: > Hello Guys, > > How to specify with XST that an input of a VHDL entity is a clock ? > > I guess it is not automatic because after the XST logic synthesis, > noone of my "process" have been synthetized ? > > thanks, Julien Use a simulator to verify correct functional operation of your top level design...after that you should find that XST synthesizes your design properly. KJArticle: 129198
On Feb 17, 10:22 pm, Peter Alfke <al...@sbcglobal.net> wrote: > Our friend Antti is out of a job. > Is there somebody in the Munich area who can offer a job, or some > consulting ? > I need not explain that Antti is a really sharp engineer with lots of > FPGA experience. > You all know that. > > You can reach him at > > antti.luk...@googlemail.com > > Peter Alfke, who posted this on his own, because he cannot stand a > friend be so unhappy. To Antti, I have writen you an email on January (on your google mail)! Please recheck it. Contact me on laurent.gauch -AT- amontec.com. We could find a way for freelancer job from Munich. With our new UIPkey , many projects are coming! Regards, LarryArticle: 129199
Anyone ever run into an issue where the PowerPC can write to entities on its DPLB, but cannot read from them? I've added chipscope to the PLB and everything looks right from the control lines. I singled-stepped the first read instruction on the PowerPC and after stepping that instruction the PPC goes off into 'la- la' land. My system consists of a PPC w/ Instruction side and Data side OCMs, a PLB attached the DPLB0 port, a MPMC3, interrupt controller, uartlite, and host I/F for the TEMAC attached to the PLB.
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Compare FPGA features and resources
Threads starting:
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