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Hi Narenda, Narendra Sisodiya wrote: > I Love Linux, but currently i have to boot in XP because of xilinx > toolset (ISE, EDK, sysgen Matlab, chipscope etc) > May any body tell me , Any Linux Distro (other then commercial , like > redhat, i cann't buy) which will work perfectly with all > components(ISE, EDK, sysgen Matlab, chipscope etc). > I am using Fedora 7 and face problem with cable drivers and many such > things, > Is any body working perfectly with this any Linux Distro, ??? I use CentOS exclusively - www.centos.org. It is a source-level, free rebuild/clone of RHEL, which is Xilinx's official supported Linux distro. This means that all of Xilinx's advice re: Linux usage, applies, without actually purchasing RHEL. I am using both CentOS 4 and CentOS 5. A few workarounds required with CentOS 5 (as would be required with RHEL 5 as well), to get the Xilinx tools running happily under SELinux. But, the Xilinx cable drivers, and everything else I've used so far, all work nicely. Regards, JohnArticle: 129276
On 20 Feb., 00:38, MikeShepherd...@btinternet.com wrote: > >how about wiring the prom clock to a pin that can be used as a timer > >output, at startup you > >can use the pin as io and bitbang the prom the usual way to pick the > >right starting address > >and give it the right read commands, after that enable the pin as a > >timer output and run as > >fast as the timer will go... > > Maybe that would work in some cases. The number of clocks would need > to be well-defined (to match exactly the size of a data block). The > micro would then need to discard the CRC which follows the data. (It > needn't check it as the FPGA will check the CRC on the whole of the > configuration). > > In my case, the clock to the flash memory must be set before the clock > to the FPGA (although they can be cleared at the same time), so a > single signal won't work. > > Mike oh, I didn't notice you used an SD card, I was imagining a regular serial prom where you can just keep on clocking till you have enough bits. -LasseArticle: 129277
Nial Stewart wrote: > I'm going to talk to a potential new client about using FPGAs to > accelerate part of their system. > > As part of what needs done there could be a significant amount of > division(s) done. > > Previously I've been able to multiply by a reciprocal then scale to > make division a double clock operation so this can be easily pipelined. > This is only achieveable if the divisor is pre-known and the > reciprocal can be pre-calculated. > > With what's coming up I'm not sure that I can do this, I know that > > Are there any clever techniques for streamlining divisions that > make them deterministic and don't use a big wodge of logic? > > > Thanks for any pointers, > > > Nial > > Nial, Your reciprocal division is reasonably close to a low latency divider I've used many times in the past. Instead of just one reciprocal, use the upper bits of the denominator to address a BRAM containing reciprocals, then use the lower bits of the denominator to interpolate between the stored reciprocals to obtain a corrected reciprocal for more precision. Use that to multiply the numerator to obtain the quotient. It can be pipelined to run at the max clock for the multipliers, and has a latency of a BRAM plus two multipliers plus an adder. For example a divider with 17 bit denominator and numerator and 16 bit quotient can use the upper 10 bits of the denominator to address a 1Kx18 reciprocal ROM to get an approximate reciprocal. Interpolate using a second 1Kx18 ROM (holds the slope at each stored reciprocal) and a multiplier to get a correction equal to the product of the 6 LSBs of the denominator and the entry from the interpolation rom. That gets added to the reciprocal ROM output to get a corrected reciprocal. Multiply that corrected reciprocal by the numerator and round to get the quotient. The entire 17 bit divide uses two multipliers, two BRAMs and two adders plus registers to match delays to give a low latency divider. You can improve the accuracy further if you can normalize the denominator and numerator before the divide and then denormalize by the difference of the normalizing shifts afterwards (basically floating point).Article: 129278
On Feb 20, 1:30 am, Sky46...@trline5.org wrote: > Narendra Sisodiya <narendra.sisod...@gmail.com> wrote: > >On Feb 19, 10:49 pm, Sky46...@trline5.org wrote: > >> Narendra Sisodiya <narendra.sisod...@gmail.com> wrote: > >> >Hi, > >> >I Love Linux, but currently i have to boot in XP because of xilinx > >> >toolset (ISE, EDK, sysgen Matlab, chipscope etc) > >> >May any body tell me , Any Linux Distro (other then commercial , like > >> >redhat, i cann't buy) which will work perfectly with all > >> >components(ISE, EDK, sysgen Matlab, chipscope etc). > >> >I am using Fedora 7 and face problem with cable drivers and many such > >> >things, > >> >Is any body working perfectly with this any Linux Distro, ??? > > >> You can usewww.FreeBSD.org,anysoftware that is stuck with ms-win can be > >> handled withwww.WineHQ.org,orbe run under vmware or qemu. > >> Freebsd also use libusb asfair. > >Using Vmware,, or any virtualization technique to install windows on > >top of Linux is not a good solution,, --as it will take a hell lot of > >time of compile,,, > >I have already tried,,wine,, but i does not work perfectly,, i will > >not suggest wine or vmware,,or quem in context of xilinx tools, > >I will try with Debian, > > The newer virtualization technqiues like Xen etc.. runs at near native > execution speed. It's not perfect, but it can solve the task. > Another approach is a dedicated ms-win box wich is remote controlled via > VNC or RDP. Thanks but again I will not support RDP . Matlab and some software will not start via this type of remote login, infact i do not want to use Xen also because I do not want WinXP at all. I will try centos, as I am Fedora user, so Centos will be a similar one to me.Article: 129279
On Feb 20, 4:56 am, John Williams <jwilli...@itee.uq.edu.au> wrote: > Hi Narenda, > > Narendra Sisodiya wrote: > > I Love Linux, but currently i have to boot in XP because of xilinx > > toolset (ISE, EDK, sysgen Matlab, chipscope etc) > > May any body tell me , Any Linux Distro (other then commercial , like > > redhat, i cann't buy) which will work perfectly with all > > components(ISE, EDK, sysgen Matlab, chipscope etc). > > I am using Fedora 7 and face problem with cable drivers and many such > > things, > > Is any body working perfectly with this any Linux Distro, ??? > > I use CentOS exclusively -www.centos.org. It is a source-level, free > rebuild/clone of RHEL, which is Xilinx's official supported Linux > distro. This means that all of Xilinx's advice re: Linux usage, > applies, without actually purchasing RHEL. > > I am using both CentOS 4 and CentOS 5. A few workarounds required with > CentOS 5 (as would be required with RHEL 5 as well), to get the Xilinx > tools running happily under SELinux. But, the Xilinx cable drivers, and > everything else I've used so far, all work nicely. > > Regards, > > John Thanks Everybody, I will try first with Centos and then DebianArticle: 129280
On 16 f=E9v, 17:10, fcdu...@yahoo.com wrote: > This is a benchmark test cd, to get performance data for a specific > computer setup. Please contribute by posting a followup with the > results from the 'real' column. > > It's a complete 227 MB zipped .iso file that needs to be written to a > cd and booted. Login as toor, type bench.sh, type the data in a > followup to this posting. > A complete collection of testdata can be found in the '/tmp/ > sHHMMSS.tbz' file. And it can be copied by running 'mnt_usb.pl && cp - > p /tmp/s??????.tbz /mountpount/usb0 && umount /mountpoint/usb0' or you > can simple type down the numbers for 'real' and type them here. > If you have any security concerns, please feel free to browse the cd > volume. > > Link to the bootcd:http://www.eatlime.com/download.lc?sid=3D7F88C923-0B51-= 1E23-1EEC-53ED80... > > http://tinyurl.com/2j8bor > > I hope this will shed some better light as to which computer > configurations that will perform better or worse for fpga synhtesis- > place-route process. > A Pentium-III 800 MHz takes approx 25m on the fpga test. Intel core2 > ~300s, AMD64 ~500s (free from memory). Please use exact numbers. Very good idea. I'll give that a try when I finally get some free time... PatrickArticle: 129281
On 19 Feb., 21:16, Jeff Cunningham <j...@sover.net> wrote: > Guru wrote: > >> Ales, > >> I'm still on 9.1. What bus diversity is changed in 9.2? > >> -Jeff > > > DCR and OPB is gone. > > > Guru > > DCR bus is gone? WTF? I have a bunch of DCR peripherals - I cannot use > those in 9.2 or beyond??? > > -Jeff do not worry, you can use PLB2DCR bridge I was about to make the verification of SATA Device IP core that was connected to old PPC SoC with MB 7.0 the DCR would go via bridge thats all, no problems as such AnttiArticle: 129282
Hi,
How to read an integer from hyperterminal onto a microbaze using
EDK 9.1i.
Im trying it using scanf but its giving me errors.
here are the lines of code im trying to achieve the read.
scanf("%d",&var);
xil_print("\r\n Entered %d \r\n",var);
I get the following errors,
At Local date and time: Wed Feb 20 15:08:33 2008
xbash -q -c "cd /cygdrive/d/SCANF/; /usr/bin/make -f system.make
TestApp_Memory_program; exit;" started...
mb-gcc -O2 TestApp_Memory/src/TestApp_Memory.c -o TestApp_Memory/
executable.elf \
-mno-xl-soft-mul -mxl-pattern-compare -mcpu=v6.00.a -Wl,-T -
Wl,TestApp_Memory/src/TestApp_Memory_LinkScr.ld -g -I./
microblaze_0/include/ -L./microblaze_0/lib/ \
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/
3.4.1/../../../../microblaze/bin/ld.real: region ilmb_cntlr_dlmb_cntlr
is full (TestApp_Memory/executable.elf section .text)
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/
3.4.1/../../../../microblaze/bin/ld.real: region ilmb_cntlr_dlmb_cntlr
is full (TestApp_Memory/executable.elf section .text)
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/
3.4.1/../../../../microblaze/bin/ld.real: section .init [00000050 ->
00000077] overlaps section .text [00000050 -> 00010293]
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/
3.4.1/../../../../microblaze/bin/ld.real: section .fini [00000078 ->
00000093] overlaps section .text [00000050 -> 00010293]
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/
3.4.1/../../../../microblaze/bin/ld.real: section .rodata [00000094 ->
00000cdf] overlaps section .text [00000050 -> 00010293]
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/
3.4.1/../../../../microblaze/bin/ld.real: section .data [00000ce0 ->
000013ff] overlaps section .text [00000050 -> 00010293]
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/
3.4.1/../../../../microblaze/bin/ld.real: section .ctors [00001400 ->
00001407] overlaps section .text [00000050 -> 00010293]
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/
3.4.1/../../../../microblaze/bin/ld.real: section .dtors [00001408 ->
0000140f] overlaps section .text [00000050 -> 00010293]
/cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/
3.4.1/../../../../microblaze/bin/ld.real: section .jcr [00001410 ->
00001413] overlaps section .text [00000050 -> 00010293]
/cygdrive/c/DOCUME~1/ADMINI~1/LOCALS~1/Temp/ccGEcfLD.o: In function
`main':
/cygdrive/d/SCANF/TestApp_Memory/src/TestApp_Memory.c:85: undefined
reference to `xil_print'
collect2: ld returned 1 exit status
make: *** [TestApp_Memory/executable.elf] Error 1
Done!
Expecting a quick response
Thanks in advance
Article: 129283>oh, I didn't notice you used an SD card, I was imagining a regular >serial prom where you can just keep on clocking till you have enough >bits. Of course, an SD card wouldn't be first choice for storing the configuration, but the application is based on SD card, so it makes sense to fetch the configuration from there, too. MikeArticle: 129284
On Wed, 2008-02-20 at 01:45 -0800, MAx wrote:
> Hi,
> How to read an integer from hyperterminal onto a microbaze using
> EDK 9.1i.
> Im trying it using scanf but its giving me errors.
>
> here are the lines of code im trying to achieve the read.
>
> scanf("%d",&var);
> xil_print("\r\n Entered %d \r\n",var);
>
> I get the following errors,
>
> At Local date and time: Wed Feb 20 15:08:33 2008
> xbash -q -c "cd /cygdrive/d/SCANF/; /usr/bin/make -f system.make
> TestApp_Memory_program; exit;" started...
> mb-gcc -O2 TestApp_Memory/src/TestApp_Memory.c -o TestApp_Memory/
> executable.elf \
> -mno-xl-soft-mul -mxl-pattern-compare -mcpu=v6.00.a -Wl,-T -
> Wl,TestApp_Memory/src/TestApp_Memory_LinkScr.ld -g -I./
> microblaze_0/include/ -L./microblaze_0/lib/ \
>
>
> /cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/
> 3.4.1/../../../../microblaze/bin/ld.real: region ilmb_cntlr_dlmb_cntlr
> is full (TestApp_Memory/executable.elf section .text)
>
> /cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/
> 3.4.1/../../../../microblaze/bin/ld.real: region ilmb_cntlr_dlmb_cntlr
> is full (TestApp_Memory/executable.elf section .text)
>
> /cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/
> 3.4.1/../../../../microblaze/bin/ld.real: section .init [00000050 ->
> 00000077] overlaps section .text [00000050 -> 00010293]
>
> /cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/
> 3.4.1/../../../../microblaze/bin/ld.real: section .fini [00000078 ->
> 00000093] overlaps section .text [00000050 -> 00010293]
>
> /cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/
> 3.4.1/../../../../microblaze/bin/ld.real: section .rodata [00000094 ->
> 00000cdf] overlaps section .text [00000050 -> 00010293]
>
> /cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/
> 3.4.1/../../../../microblaze/bin/ld.real: section .data [00000ce0 ->
> 000013ff] overlaps section .text [00000050 -> 00010293]
>
> /cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/
> 3.4.1/../../../../microblaze/bin/ld.real: section .ctors [00001400 ->
> 00001407] overlaps section .text [00000050 -> 00010293]
>
> /cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/
> 3.4.1/../../../../microblaze/bin/ld.real: section .dtors [00001408 ->
> 0000140f] overlaps section .text [00000050 -> 00010293]
>
> /cygdrive/c/EDK/gnu/microblaze/nt/bin/../lib/gcc/microblaze/
> 3.4.1/../../../../microblaze/bin/ld.real: section .jcr [00001410 ->
> 00001413] overlaps section .text [00000050 -> 00010293]
>
> /cygdrive/c/DOCUME~1/ADMINI~1/LOCALS~1/Temp/ccGEcfLD.o: In function
> `main':
>
> /cygdrive/d/SCANF/TestApp_Memory/src/TestApp_Memory.c:85: undefined
> reference to `xil_print'
> collect2: ld returned 1 exit status
>
> make: *** [TestApp_Memory/executable.elf] Error 1
>
> Done!
>
> Expecting a quick response
>
> Thanks in advance
You do not have enough code space to use scanf()...
Jan
Article: 129285On Feb 20, 7:26 am, MikeShepherd...@btinternet.com wrote: > >oh, I didn't notice you used an SD card, I was imagining a regular > >serial prom where you can just keep on clocking till you have enough > >bits. > > Of course, an SD card wouldn't be first choice for storing the > configuration, but the application is based on SD card, so it makes > sense to fetch the configuration from there, too. > > Mike Looks like SPI Master Mode is the option. I am interested in Jon's alternative of putting a memory twice the size a program need. Any ideas how to implement this? BTW , I also need to program two FPGA with the same program so I would need to do daisy chain with a Spartan-3E. So for my bad english and thanks AlfredArticle: 129286
On 2008-02-20, Jeff Cunningham <jcc@sover.net> wrote: > I thought the whole point of the DCR was to allow control/status > accesses from the PPC to go on in parallel with PLB operations. If you > have to go through a PLB bridge, then the advantage of the DCR is lost. Personally I thought the idea was that the DCR bus is relatively slow and it should therefore be easy to meet timing on it even if we have many components connected to it. Stuff like parallel ports, uarts, performance monitors, configuration interfaces, etc could sit on the DCR bus in order to make it easier to meet tight timing constraints on the PLB bus. /AndreasArticle: 129287
On 20 Feb., 11:26, MikeShepherd...@btinternet.com wrote: > >oh, I didn't notice you used an SD card, I was imagining a regular > >serial prom where you can just keep on clocking till you have enough > >bits. > > Of course, an SD card wouldn't be first choice for storing the > configuration, but the application is based on SD card, so it makes > sense to fetch the configuration from there, too. > > Mike FPGA configution IP core for MMC card is as small as 21 PLD MC's (more for SD card) or less than 1Kbyte of code for AVR if using micro as boot processor AnttiArticle: 129288
>FPGA configution IP core for MMC card is as small as 21 PLD MC's (more >for SD card) >or less than 1Kbyte of code for AVR if using micro as boot processor Certainly, it's easy to read MMC/SD cards in SPI mode, but that offers only 1-bit-wide data. It's possible to start in SPI mode then switch to "native" mode (but you have to power off the card to do that). I prefer to initialise in "native" mode, read the FPGA configuration and any microcontroller update, then switch to 4-bit mode so that the FPGA can read the card at high speed. MikeArticle: 129289
Hi Narendra Sisodiya, everyone, Narendra Sisodiya wrote: > May any body tell me , Any Linux Distro (other then commercial , like > redhat, i cann't buy) which will work perfectly with all > components(ISE, EDK, sysgen Matlab, chipscope etc). > Is any body working perfectly with this any Linux Distro, ??? For me, things work nearly out of the box on Ubuntu Gutsy Gibbon, which I'm running on my (dual boot) MacBookPro - FPGA design is the only reason for having a second OS on that machine. I haven't tried EDK, Sysgen or Chipscope though, and I use Octave instead of Matlab. The nice thing about Ubuntu is that the Xilinx simulator works (in Suse it only creates error messages). Installing Ubuntu on a second partition was very easy thanks to Bootcamp, rEFIt and some other nifty tools. I set aside 5GB for my Linux/Xilinx partition. Imagine my surprise when, after installing the WebPack, I ran out of space already doing the webupdate... Regards, Paul Boven.Article: 129290
Antti wrote: >>> DCR and OPB is gone. >> DCR bus is gone? WTF? I have a bunch of DCR peripherals - I cannot use >> those in 9.2 or beyond??? >> >> -Jeff > > do not worry, you can use PLB2DCR bridge > I was about to make the verification of SATA Device IP core that was > connected to old PPC SoC > with MB 7.0 the DCR would go via bridge thats all, no problems as such > > Antti I thought the whole point of the DCR was to allow control/status accesses from the PPC to go on in parallel with PLB operations. If you have to go through a PLB bridge, then the advantage of the DCR is lost. -JeffArticle: 129291
Antti schrieb: > Hi Bob and Peter, > > first of all, thanks - while I could move almost anywhere, I do have > two small kids (boy 6, girl 4) and the boy needs special care because > delayed speech development (he talks all the time, but its really hard > to understand what). This limits the options for the re-location with > the family. > Moving away from German spoken region, or even moving away from > Munich could have bad impact on the kids. So options left for my > family Have a look at http://www.freelancermap.de/ and search for projects containing the word fpga. Than become happy TomArticle: 129292
On 20 Feb., 13:27, MikeShepherd...@btinternet.com wrote: > >FPGA configution IP core for MMC card is as small as 21 PLD MC's (more > >for SD card) > >or less than 1Kbyte of code for AVR if using micro as boot processor > > Certainly, it's easy to read MMC/SD cards in SPI mode, but that offers > only 1-bit-wide data. It's possible to start in SPI mode then switch > to "native" mode (but you have to power off the card to do that). I > prefer to initialise in "native" mode, read the FPGA configuration and > any microcontroller update, then switch to 4-bit mode so that the FPGA > can read the card at high speed. > > Mike 21 MC is NATIVE mode MMC init. native SD mode is just a little more. I never use SPI mode if possible AnttiArticle: 129293
On 20 Feb., 15:18, Thomas Reinemann <tom.reinem...@gmx.net> wrote: > Antti schrieb: > > > Hi Bob and Peter, > > > first of all, thanks - while I could move almost anywhere, I do have > > two small kids (boy 6, girl 4) and the boy needs special care because > > delayed speech development (he talks all the time, but its really hard > > to understand what). This limits the options for the re-location with > > the family. > > Moving away from German spoken region, or even moving away from > > Munich could have bad impact on the kids. So options left for my > > family > > Have a look athttp://www.freelancermap.de/and search for projects > containing the word fpga. > > Than become happy > > Tom thanks, I will look. I am right now already little happier, as the last employer did finally pay the last paycheck (with over 20 days delay)! So I paid the rent what was overdue. AnttiArticle: 129294
On 20 Feb., 12:21, Andreas Ehliar <ehliar-nos...@isy.liu.se> wrote: > On 2008-02-20, Jeff Cunningham <j...@sover.net> wrote: > > > I thought the whole point of the DCR was to allow control/status > > accesses from the PPC to go on in parallel with PLB operations. If you > > have to go through a PLB bridge, then the advantage of the DCR is lost. > > Personally I thought the idea was that the DCR bus is relatively slow > and it should therefore be easy to meet timing on it even if we have many > components connected to it. Stuff like parallel ports, uarts, performance > monitors, configuration interfaces, etc could sit on the DCR bus in order > to make it easier to meet tight timing constraints on the PLB bus. > > /Andreas yes, and for me I was about to convert a PPC design to microblaze for Virtex-5LXT and the IP-Core used DCR so i had to use the bridge for DCR AnttiArticle: 129295
Thanks for the reply. No, that is not the problem. The files compile just fine under Modelsim and using the Altera tools. In both of those tools I can specify the order to compile the files. These libraries are files that I have my personal, common definitions and conversions. I know these files work because they have been used many times before. All I need to know is how the Lattice ispLever tool is told the order to compile the files. On Feb 19, 12:17 pm, "Colin Hankins" <Colin.Hank...@touit.com> wrote: > Did you include the use clause in your library package files that require > dependancies? You can either reference the user defined library itself or > just do: use work.my_package; > > The error messages related to library not found is probably due to the > library not being successfully compiled in the first place. > > Colin > > "rickman" <gnu...@gmail.com> wrote in message > > news:284755cf-f23b-4979-9ecd-25d229fde921@e23g2000prf.googlegroups.com... > > >I am trying to pick up the Lattice ispLEVER tool and am having a bit > > of trouble with it in regards to libraries. I have several files for > > the various libraries I have written for my VHDL. In order to use > > them, they have to be compiled in the correct order since some use > > definitions from the others. I can't seem to figure out how to tell > > ispLEVER what order to compile the files. It has a way to telling the > > tool that a given file *is* a library, but that seems to be where it > > stops. I can't order the files in the project and it doesn't seem to > > actually understand that the libraries exist in the VHDL. I get > > several error message all related to libraries not found or > > identifiers not declared that should have been in the library files. > > > I have looked through every piece of documentation I can find and they > > all pretty much gloss over the idea of user defined libraries. Is > > this something so simple I have missed it?Article: 129296
On Feb 20, 8:07 am, Antti <Antti.Luk...@googlemail.com> wrote: > On 20 Feb., 13:27, MikeShepherd...@btinternet.com wrote:> >FPGA configution IP core for MMC card is as small as 21 PLD MC's (more > > >for SD card) > > >or less than 1Kbyte of code for AVR if using micro as boot processor > > > Certainly, it's easy to read MMC/SD cards in SPI mode, but that offers > > only 1-bit-wide data. It's possible to start in SPI mode then switch > > to "native" mode (but you have to power off the card to do that). I > > prefer to initialise in "native" mode, read the FPGA configuration and > > any microcontroller update, then switch to 4-bit mode so that the FPGA > > can read the card at high speed. > > > Mike > > 21 MC is NATIVE mode MMC init. > native SD mode is just a little more. > > I never use SPI mode if possible > > Antti All this talk of SPI vs Native mode has me curious. SPI mode is fairly well documented online, but Googling indicates that getting specs on how to use native mode requires licensing from the SD Card Assoc, which is apparently quite costly. Is this true? Are there any free resources where one could learn more about using Native mode? EBArticle: 129297
I have a project to prototype an ASIC design on FPGA. What are the things I should do? Here is some of my concerns: 1) I understand FPGAs usually have 4 look-up table. Should I rewrite the ASIC combinational logics to be four-inputs logics to improve the utilization of FPGA? 2) Netting if and case statements over three layers might results a poor synthesis result in FPGA . Should I changes those netting codes in ASIC RTL? 3) ASIC synthesis need to generate clock tree and power rails. In FPGA synthesis, Maybe I not need to care too much about it? 4) Is there a to-do-list for this kind of job? Thank you for any advices.Article: 129298
On Feb 20, 9:59 am, emeb <ebromba...@gmail.com> wrote: > On Feb 20, 8:07 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > > On 20 Feb., 13:27, MikeShepherd...@btinternet.com wrote:> >FPGA configution IP core for MMC card is as small as 21 PLD MC's (more > > > >for SD card) > > > >or less than 1Kbyte of code for AVR if using micro as boot processor > > > > Certainly, it's easy to read MMC/SD cards in SPI mode, but that offers > > > only 1-bit-wide data. It's possible to start in SPI mode then switch > > > to "native" mode (but you have to power off the card to do that). I > > > prefer to initialise in "native" mode, read the FPGA configuration and > > > any microcontroller update, then switch to 4-bit mode so that the FPGA > > > can read the card at high speed. > > > > Mike > > > 21 MC is NATIVE mode MMC init. > > native SD mode is just a little more. > > > I never use SPI mode if possible > > > Antti > > All this talk of SPI vs Native mode has me curious. SPI mode is fairly > well documented online, but Googling indicates that getting specs on > how to use native mode requires licensing from the SD Card Assoc, > which is apparently quite costly. Is this true? Are there any free > resources where one could learn more about using Native mode? > > EB Never mind. Apparently the spec is now freely available here: http://www.sdcard.org/about/memory_card/pls/ A quick skim seems to indicate that all the necessary protocol details are there. BTW - I assume that all the previous discussions about loading FPGAs from SD/MMC assume that the data on the SD/MMC is _not_ in a standard filesystem, but was written in some raw format. It's difficult to imagine getting a FAT filesystem reader into 21 macrocells. EBArticle: 129299
On 20 Feb., 18:09, emeb <ebromba...@gmail.com> wrote: > On Feb 20, 9:59 am, emeb <ebromba...@gmail.com> wrote: > > > > > On Feb 20, 8:07 am, Antti <Antti.Luk...@googlemail.com> wrote: > > > > On 20 Feb., 13:27, MikeShepherd...@btinternet.com wrote:> >FPGA configution IP core for MMC card is as small as 21 PLD MC's (more > > > > >for SD card) > > > > >or less than 1Kbyte of code for AVR if using micro as boot processor > > > > > Certainly, it's easy to read MMC/SD cards in SPI mode, but that offers > > > > only 1-bit-wide data. It's possible to start in SPI mode then switch > > > > to "native" mode (but you have to power off the card to do that). I > > > > prefer to initialise in "native" mode, read the FPGA configuration and > > > > any microcontroller update, then switch to 4-bit mode so that the FPGA > > > > can read the card at high speed. > > > > > Mike > > > > 21 MC is NATIVE mode MMC init. > > > native SD mode is just a little more. > > > > I never use SPI mode if possible > > > > Antti > > > All this talk of SPI vs Native mode has me curious. SPI mode is fairly > > well documented online, but Googling indicates that getting specs on > > how to use native mode requires licensing from the SD Card Assoc, > > which is apparently quite costly. Is this true? Are there any free > > resources where one could learn more about using Native mode? > > > EB > > Never mind. Apparently the spec is now freely available here: > > http://www.sdcard.org/about/memory_card/pls/ > > A quick skim seems to indicate that all the necessary protocol details > are there. > > BTW - I assume that all the previous discussions about loading FPGAs > from SD/MMC assume that the data on the SD/MMC is _not_ in a standard > filesystem, but was written in some raw format. It's difficult to > imagine getting a FAT filesystem reader into 21 macrocells. > > EB I have done the impossible, but FAT in 21 MC is beyong my limits as well. however if 1 file is copied to mmc card (the first file after format) then FPGA will configure from that file I have however developed a 0FAT filesystem that allows access to files in FAT file system without fat parsing, it is compatible to almost any filesystem. a microcontroller code that support SD native and 0FAT is still below 1 k of code a SD card hard IP-Core could also support 0FAT with very little extra resources Antti
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