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Messages from 130325

Article: 130325
Subject: Re: Configure Spartan-3E w SD-Card?
From: Antti <Antti.Lukats@googlemail.com>
Date: Thu, 20 Mar 2008 07:15:26 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 20 Mrz., 14:22, j...@amontec.com wrote:
> On Mar 20, 1:07 pm, sky46...@trline4.org wrote:
>
> > I think someone here mentioned the possibility to configure an Xilinx
> > Spartan-3E fpga with an SD-Card (MMC) in SPI mode. However when checking on
> > this by chance today I found that it seems to not work because:
>
> > Read commands are defined as:http://www.sdcard.org/about/memory_card/pls/Simplified_Physical_Layer...
> >   READ_SINGLE_BLOCK  0x51
> >   READ_MULTI..       0x52
>
> > But Spartan-3E SPI uses the commands:http://direct.xilinx.com/bvdocs/publications/ds312.pdfPage79
> >   Fast read   0x0B
> >   Read        0x03
> >   Read array  0xE8
>
> > Or did I miss something?
>
> SPI bus means to have one Master and one Slave.
>
> SD card cannot be master, you need to have a Master to get the data
> from!
> FPGA CONFIG RAM cannot be master, you need to have a master to write
> the data to the FPGA RAM !
>
> For programming FPGA, you need a master getting the data from SD and
> writing to FPGA RAM.
>
> Larry,http://www.amontec.com

SD card doesnt need to be master, the issue is that it is not
compatible to the FPGA command used in master serial mode, etc.

with MMC card (not SD!) a RECONFIGURATION from MMC card could be
possible, if

1 S3E is configured from SPI flash
2 S3E puts SPI flash into DEEP powerdown or any other mode that
prevents configuration in case of PROG toggle
3 S3E prepares MMC card to enter STREAMING READ (not available on SD
cards) mode and pre shifts instruction and address
4 S3E pulses its own PROG pin
5 S3E would be configured from a file located on the MMC card

so while INITIAL load from card is no way possible a repeated
secondary configuration can be possible

S3E should be connected properly SPI flash and MMC card pins in
parallel, MMC card should be operating in non SPI mode

Antti

















Article: 130326
Subject: Configuring a Spartan 3A1800 ExtremeDSP from Spartan3 cable?
From: Paul Boven <boven@jive.nl>
Date: Thu, 20 Mar 2008 15:25:09 +0100
Links: << >>  << T >>  << A >>
Hi everyone,

Just ordered a Spartan 3A ExtremeDSP Starter Kit. It comes without a
programming cable, but I figured I could re-use the cable from my trusty
Digilent parallel cable from the Spartan-3 kit. The pinout is certainly
the same (6 pins single header). But I've just noticed that the Digilent
documentation states there is 2.8V on the connector while the new
Spartan-3A DSP board provides 2.5V. Will this work?

Regards, Paul Boven.

Article: 130327
Subject: Re: Configure Spartan-3E w SD-Card?
From: job@amontec.com
Date: Thu, 20 Mar 2008 07:50:33 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 20, 3:15 pm, Antti <Antti.Luk...@googlemail.com> wrote:
> On 20 Mrz., 14:22, j...@amontec.com wrote:
>
>
>
> > On Mar 20, 1:07 pm, sky46...@trline4.org wrote:
>
> > > I think someone here mentioned the possibility to configure an Xilinx
> > > Spartan-3E fpga with an SD-Card (MMC) in SPI mode. However when checking on
> > > this by chance today I found that it seems to not work because:
>
> > > Read commands are defined as:http://www.sdcard.org/about/memory_card/pls/Simplified_Physical_Layer...
> > >   READ_SINGLE_BLOCK  0x51
> > >   READ_MULTI..       0x52
>
> > > But Spartan-3E SPI uses the commands:http://direct.xilinx.com/bvdocs/publications/ds312.pdfPage79
> > >   Fast read   0x0B
> > >   Read        0x03
> > >   Read array  0xE8
>
> > > Or did I miss something?
>
> > SPI bus means to have one Master and one Slave.
>
> > SD card cannot be master, you need to have a Master to get the data
> > from!
> > FPGA CONFIG RAM cannot be master, you need to have a master to write
> > the data to the FPGA RAM !
>
> > For programming FPGA, you need a master getting the data from SD and
> > writing to FPGA RAM.
>
> > Larry,http://www.amontec.com
>
> SD card doesnt need to be master, the issue is that it is not
> compatible to the FPGA command used in master serial mode, etc.
>
> with MMC card (not SD!) a RECONFIGURATION from MMC card could be
> possible, if
>
> 1 S3E is configured from SPI flash
> 2 S3E puts SPI flash into DEEP powerdown or any other mode that
> prevents configuration in case of PROG toggle
> 3 S3E prepares MMC card to enter STREAMING READ (not available on SD
> cards) mode and pre shifts instruction and address
> 4 S3E pulses its own PROG pin
> 5 S3E would be configured from a file located on the MMC card
>
> so while INITIAL load from card is no way possible a repeated
> secondary configuration can be possible
>
> S3E should be connected properly SPI flash and MMC card pins in
> parallel, MMC card should be operating in non SPI mode
>
> Antti

> SD card doesnt need to be master ...

Do you mean a SD Card could be Master ?????

- Larry
http://www.amontec.com

Article: 130328
Subject: Re: Configure Spartan-3E w SD-Card?
From: Antti <Antti.Lukats@googlemail.com>
Date: Thu, 20 Mar 2008 08:05:00 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 20 Mrz., 15:50, j...@amontec.com wrote:
> On Mar 20, 3:15 pm, Antti <Antti.Luk...@googlemail.com> wrote:
>
>
>
> > On 20 Mrz., 14:22, j...@amontec.com wrote:
>
> > > On Mar 20, 1:07 pm, sky46...@trline4.org wrote:
>
> > > > I think someone here mentioned the possibility to configure an Xilinx
> > > > Spartan-3E fpga with an SD-Card (MMC) in SPI mode. However when checking on
> > > > this by chance today I found that it seems to not work because:
>
> > > > Read commands are defined as:http://www.sdcard.org/about/memory_card/pls/Simplified_Physical_Layer...
> > > >   READ_SINGLE_BLOCK  0x51
> > > >   READ_MULTI..       0x52
>
> > > > But Spartan-3E SPI uses the commands:http://direct.xilinx.com/bvdocs/publications/ds312.pdfPage79
> > > >   Fast read   0x0B
> > > >   Read        0x03
> > > >   Read array  0xE8
>
> > > > Or did I miss something?
>
> > > SPI bus means to have one Master and one Slave.
>
> > > SD card cannot be master, you need to have a Master to get the data
> > > from!
> > > FPGA CONFIG RAM cannot be master, you need to have a master to write
> > > the data to the FPGA RAM !
>
> > > For programming FPGA, you need a master getting the data from SD and
> > > writing to FPGA RAM.
>
> > > Larry,http://www.amontec.com
>
> > SD card doesnt need to be master, the issue is that it is not
> > compatible to the FPGA command used in master serial mode, etc.
>
> > with MMC card (not SD!) a RECONFIGURATION from MMC card could be
> > possible, if
>
> > 1 S3E is configured from SPI flash
> > 2 S3E puts SPI flash into DEEP powerdown or any other mode that
> > prevents configuration in case of PROG toggle
> > 3 S3E prepares MMC card to enter STREAMING READ (not available on SD
> > cards) mode and pre shifts instruction and address
> > 4 S3E pulses its own PROG pin
> > 5 S3E would be configured from a file located on the MMC card
>
> > so while INITIAL load from card is no way possible a repeated
> > secondary configuration can be possible
>
> > S3E should be connected properly SPI flash and MMC card pins in
> > parallel, MMC card should be operating in non SPI mode
>
> > Antti
> > SD card doesnt need to be master ...
>
> Do you mean a SD Card could be Master ?????
>
> - Larryhttp://www.amontec.com

no no,
but when FPGA is configured as MASTER SERIAL then FPGA would generate
CCLK
if CCLK -> SD_CLK

and MMC preinited for streaming read then FPGA would clock out its
bitstream from MMC card

Antti












Article: 130329
Subject: Re: ISE 10.0 finally with multi-threading and SV support ?
From: Kolja Sulimma <ksulimma@googlemail.com>
Date: Thu, 20 Mar 2008 08:08:08 -0700 (PDT)
Links: << >>  << T >>  << A >>
On 19 Mrz., 12:20, ratztafaz <heinerl...@googlemail.com> wrote:
> Will the 10th edition of ISE, to be relealed next week, finally
> support multithreading/SMP machines to reduce synthesis + P&R time?
That is easy to do for high level synthesis, next to impossible for
placement and
very difficult for routing.

> What other major features to you still miss? - Discuss!

VHDL2006 support.

Kolja Sulimma

Article: 130330
Subject: Re: A Challenge for serialized processor design and implementation
From: Steve Goodwin <ng@p2cl.co.uk>
Date: Thu, 20 Mar 2008 15:10:42 +0000
Links: << >>  << T >>  << A >>
In article <87fxulo6h0.fsf@cordelia.devereux.me.uk>, John Devereux
<jdREMOVE@THISdevereux.me.uk> writes
>Steve Goodwin <ng@p2cl.co.uk> writes:
>
>> In article <47e1a2f1$1@clear.net.nz>, Jim Granville <no.spam@designtools
>> .maps.co.nz> writes
>>
>>>8048 ? maybe, but no compilers for this ?
>>
>> Nooooo... please, please noooo... I still have nightmares....
>
>You too? Perhaps we should start a support & recovery group.

I fear denial is the only remedy...

>Didn't you just *love* how you could insert a line of assembler, and
>trigger half a dozen errors elsewhere due to code crossing the page
>boundaries?

We ended up with so much code that we had to we add our own hardware
bank switching on top of the pages... until *finally* we persuaded the
company to change to a Z80 and c...

Happy days ... :)

-- 
Steve Goodwin...  www.p2cl.co.uk (includes contact details)

Article: 130331
Subject: Re: A Challenge for serialized processor design and implementation
From: Walter Banks <walter@bytecraft.com>
Date: Thu, 20 Mar 2008 10:35:28 -0500
Links: << >>  << T >>  << A >>


John Devereux wrote:

> Steve Goodwin <ng@p2cl.co.uk> writes:
>
> > In article <47e1a2f1$1@clear.net.nz>, Jim Granville <no.spam@designtools
> > .maps.co.nz> writes
> >
> >>8048 ? maybe, but no compilers for this ?
> >
> > Nooooo... please, please noooo... I still have nightmares....
>
> You too? Perhaps we should start a support & recovery group.
>
> Didn't you just *love* how you could insert a line of assembler, and
> trigger half a dozen errors elsewhere due to code crossing the page
> boundaries?

Bugs we learned hate. Byte Craft was new, mostly consulting
then one of our customers was having a problem with their
8048 controller just up and failing. A static stack checker
found 14 nested functions in an 8 level stack. (Lots of little
functions so the code would fit)  Processors like that paid the rent.

w..






Article: 130332
Subject: PCI Express Configuration Testing
From: "water9580@yahoo.com" <water9580@yahoo.com>
Date: Thu, 20 Mar 2008 08:57:13 -0700 (PDT)
Links: << >>  << T >>  << A >>
The Linux lspci -xxx command can show my PCIE device header
space(0x00~0xFF). However,simultaneity,the Correctable Error and
Unsupported Request error from PCIE Capabilities device status
register are set.

I run the PCI Express Configuration Testing program from PCISIG to
test configure space.The system is halt after click run all test.Reset
PC and report NMI error.

why?

My configuration: PCIEx1, 16bit customize GTP wrapper same as Endpoint
x1 IP.

Article: 130333
Subject: Power Estimation of Microblaze (Power PC) based architectures
From: ahosyney <ahosyney@gmail.com>
Date: Thu, 20 Mar 2008 09:33:45 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi

I'm trying to estimate the power consumption of an architecture based
on either Microblaze or PowerPC running a simple application (bubble
sort). Using the EDK and ISE I managed to build the timing simulation
model (Post Place and Route Model) for a Microblaze based
architecture . Then I tried to simulate this using ModelSim SE 6. When
I simulate the architecture using Modelsim it appeared to me that the
memory was not initialized with the software program (I'm using only
block rams for both instructions and data memories). I knew that
because the program counter is incremented and addresses are generated
from Microblaze but no data is transferred. After investigation I
found out that Modelsim somehow was unable to initialize the block ram
with the software program (a VHDL configuration is generated by the
EDK to do so but Modelsim just ignored it).

I managed to solve this problem by using data2mem command to convert
the ELF file into MEM files and load it into the block ram using
Modelsim. Using this approach I managed to simulate the architecture
and generate the expected results (except some problems with
interrupts).

So the next step was to generate VCD file using Modelsim and then
using XPower tried to estimate the power consumption. This seamed to
be working fine, and generate some estimation. But when I tried to
change the size of the array to be sorted and redo the simulation
again, I found out that the power estimation is not affected much with
the change I made to the software (although it is a significant one).
To Clarify this I started with an array size of 10 integers, this
array requires 887 clock cycles to be sorted and the total estimated
power consumption was around 488.65 mW. When I increased the array
size to 20 integers (which requires 3069 clock cycles to be sorted)
the estimated power consumption was 492.28mW with increase of about
3.5 mW. When I increased the number of integers to 40 (11298 clock
cycles are needed to sort that), the power consumption just increased
by around 2mW to be 494.29mW. When I raised the number of integers to
be 80 (43280 clock cycles to be sorted), the power consumption was
reduced to 493mW. So it seems that the activities stored in the VCD
file are not affecting the power estimation as I expected. When I
tried to investigate this issue I found out that XPower gave me a
warring saying that it was able to match only 25% of the signals in
the VCD file, and it was not able to change the clock frequency to 100
MHz (although when I checked the frequency applied to the clock
signals in XPower I found it to be 100MHz). So my two questions are:

1- Why is Modelsim not able to load the software application correctly
into the block ram? Is there another approach better than the one I
mentioned above?
2- What is wrong with the VCD file and why XPower is not able to
correctly estimate the power consumptions?

So if have been through this before I would appreciate your feedback..

Best Regards

Article: 130334
Subject: Re: Power Estimation of Microblaze (Power PC) based architectures
From: ahosyney <ahosyney@gmail.com>
Date: Thu, 20 Mar 2008 09:39:35 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 20, 12:33=A0pm, ahosyney <ahosy...@gmail.com> wrote:
> Hi
>
> I'm trying to estimate the power consumption of an architecture based
> on either Microblaze or PowerPC running a simple application (bubble
> sort). Using the EDK and ISE I managed to build the timing simulation
> model (Post Place and Route Model) for a Microblaze based
> architecture . Then I tried to simulate this using ModelSim SE 6. When
> I simulate the architecture using Modelsim it appeared to me that the
> memory was not initialized with the software program (I'm using only
> block rams for both instructions and data memories). I knew that
> because the program counter is incremented and addresses are generated
> from Microblaze but no data is transferred. After investigation I
> found out that Modelsim somehow was unable to initialize the block ram
> with the software program (a VHDL configuration is generated by the
> EDK to do so but Modelsim just ignored it).
>
> I managed to solve this problem by using data2mem command to convert
> the ELF file into MEM files and load it into the block ram using
> Modelsim. Using this approach I managed to simulate the architecture
> and generate the expected results (except some problems with
> interrupts).
>
> So the next step was to generate VCD file using Modelsim and then
> using XPower tried to estimate the power consumption. This seamed to
> be working fine, and generate some estimation. But when I tried to
> change the size of the array to be sorted and redo the simulation
> again, I found out that the power estimation is not affected much with
> the change I made to the software (although it is a significant one).
> To Clarify this I started with an array size of 10 integers, this
> array requires 887 clock cycles to be sorted and the total estimated
> power consumption was around 488.65 mW. When I increased the array
> size to 20 integers (which requires 3069 clock cycles to be sorted)
> the estimated power consumption was 492.28mW with increase of about
> 3.5 mW. When I increased the number of integers to 40 (11298 clock
> cycles are needed to sort that), the power consumption just increased
> by around 2mW to be 494.29mW. When I raised the number of integers to
> be 80 (43280 clock cycles to be sorted), the power consumption was
> reduced to 493mW. So it seems that the activities stored in the VCD
> file are not affecting the power estimation as I expected. When I
> tried to investigate this issue I found out that XPower gave me a
> warring saying that it was able to match only 25% of the signals in
> the VCD file, and it was not able to change the clock frequency to 100
> MHz (although when I checked the frequency applied to the clock
> signals in XPower I found it to be 100MHz). So my two questions are:
>
> 1- Why is Modelsim not able to load the software application correctly
> into the block ram? Is there another approach better than the one I
> mentioned above?
> 2- What is wrong with the VCD file and why XPower is not able to
> correctly estimate the power consumptions?
>
> So if have been through this before I would appreciate your feedback..
>
> Best Regards

I just forgot to mention that I'm using ISE 9.2i and EDK 9.2i and
Vertix-4 XC4VFX12.


Regards


Article: 130335
Subject: Re: A Challenge for serialized processor design and implementation
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 20 Mar 2008 10:36:31 -0700 (PDT)
Links: << >>  << T >>  << A >>
For really frugal concepts we may have to go back further in history,
perhaps further than anybody else on this ng remembers.
In 1964 I was challenged to put a cash register design on a 15000-bit
torsional delay line (and failed miserably..)
In the later 'sixties, I worked at Monroe (part of Litton) on a drum-
based business computer, with an extra short loop to store registers.
Very few transistors. We also played with a torsional delay line.
In 1970 my predecessor to the hp35 used a 100-bit word, organized as
25 serial 4-bit characters.  For their very successful calculator, hp
then modified this architecture to bit serial, to further reduce pin-
count.
Those were the days of 16-pin packages and expensive gates and flip-
flops...

Peter Alfke



Article: 130336
Subject: timing and timing reports (again)
From: "u_stadler@yahoo.de" <u_stadler@yahoo.de>
Date: Thu, 20 Mar 2008 10:36:57 -0700 (PDT)
Links: << >>  << T >>  << A >>
hi

ich have question about timing.
i have an edk design with microblaze (using spartan 3e 500) where i
use an ip core that i wrote myself.
when i implement the design i get the following timing output in my
console.

------------------------------------------------------------------------------------------------------
  Constraint                           |  Check  | Worst Case |  Best
Case | Timing |   Timing
                                            |             |
Slack       | Achievable | Errors |    Score
------------------------------------------------------------------------------------------------------
* TS_dcm_48mhz_dcm_48mhz_CLKFX_BUF = PERIOD | SETUP   |
-1.456ns|    57.246ns|       1|        1456
   TIMEGRP         "dcm_48mhz_dcm_48mhz_CLK | HOLD    |
1.025ns|            |       0|           0
  FX_BUF" TS_sys_clk_pin / 0.96 HIGH 50%    |         |
|            |        |
------------------------------------------------------------------------------------------------------
  TS_dcm_0_dcm_0_CLK0_BUF = PERIOD TIMEGRP  | SETUP   |
5.532ns|    14.468ns|       0|           0
  "dcm_0_dcm_0_CLK0_BUF" TS_sys_clk_pin     | HOLD    |
0.688ns|            |       0|           0
       HIGH 50%                             |         |
|            |        |
------------------------------------------------------------------------------------------------------
  TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | SETUP   |
17.975ns|     2.025ns|       0|           0
  pin" 20 ns HIGH 50%                       | HOLD    |
0.667ns|            |       0|           0
------------------------------------------------------------------------------------------------------


my constraints in the ucf file  for the clock net are (generated by
edk):
Net sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 20000 ps;

clearly the dcm_48mhz_dcm_48mhz_CLKFX_BUF does not meet timing. my
question now is are there are some constraints that i can use to
achieve timing for that signal. or can i change something in the
design.
also when i look at the synthesis report files for the dcm48 and my
own ip they all get implemented far under their timing requirements.
is there a report where i can look up the
dcm_48mhz_dcm_48mhz_CLKFX_BUF signal an why i has such a bad timing?

thanks
urban


Article: 130337
Subject: Re: DDR SDRAM interface for Virtex II Pro and Spartan3a
From: nico@puntnl.niks (Nico Coesel)
Date: Thu, 20 Mar 2008 17:42:42 GMT
Links: << >>  << T >>  << A >>
robertwalczyk@gmail.com wrote:

>Hi
>
>I'd like to share with you my experience concerning DDR SDRAM
>interface development for XUP V2P baord, it may save your time and
>money.
>
>I spent long time working on it, trying to make the code gererated by
>the older MIG tools working. I found that there's more other people
>with similar problem, but finally didn't get answer. Since I got new
>board, Spartan3a Starter Kit, everything works fine.
>
>Here's my advice - if your project requires more memory and you're not
>well experienced FPGA engineer, I strongly recommend Spartan3a (in
>fact DDR2 in this case) with ISE 9.2.

Interesting. What speed did you achieve?

-- 
Programmeren in Almere?
E-mail naar nico@nctdevpuntnl (punt=.)

Article: 130338
Subject: Re: dual clock fifo
From: FPGA <FPGA.unknown@gmail.com>
Date: Thu, 20 Mar 2008 11:04:17 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 19, 8:46=A0pm, Mike Treseler <mike_trese...@comcast.net> wrote:
> Patrick Dubois wrote:
> > I found the source code that was available at edif.org through
> > archive.org:
> >http://web.archive.org/web/20031204114425/http://www.edif.org/lpmweb/...
>
> The internet never forgets ;)
>
> > It looks like complete source code, I'm not sure what additional
> > support I would need from vendors. It seems to me that I could just
> > use lpm_fifo_dc from 220model.vhd. Am I missing something?
>
> The code is synthesizable as is,
> but I would at least clean up the
> non-standard libraries and the
> odd-ball string generics.
>
> =A0 =A0 -- Mike Treseler
>
> ps: here's a first cut:http://home.comcast.net/~mike_treseler/sync_fifo.vh=
d

Thank you everyone for your valuable help.

Article: 130339
Subject: Is there a means to conditional synthesis in VHDL?
From: fl <rxjwg98@gmail.com>
Date: Thu, 20 Mar 2008 11:07:33 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hi,
I am designing a bunch (about 100) of short length tap (5 taps each)
FIR. The tap coefficients would be many 1...31. I want to use
multiplier adder graph method for the multiplication. That is,
multiplying 15 will be implemented as left shift 4 bits, then minus
the original. I would like VHDL can intelligently select one of 16
multiplication structure. Is that possible? Or, I have to write C code
to generate a VHDL doc? Are there other better methods? Thanks

Article: 130340
Subject: Re: Is there a means to conditional synthesis in VHDL?
From: Jonathan Bromley <jonathan.bromley@MYCOMPANY.com>
Date: Thu, 20 Mar 2008 18:29:22 +0000
Links: << >>  << T >>  << A >>
On Thu, 20 Mar 2008 11:07:33 -0700 (PDT), 
fl <rxjwg98@gmail.com> wrote:

>I am designing a bunch (about 100) of short length tap (5 taps each)
>FIR. The tap coefficients would be many 1...31. I want to use
>multiplier adder graph method for the multiplication. That is,
>multiplying 15 will be implemented as left shift 4 bits, then minus
>the original. I would like VHDL can intelligently select one of 16
>multiplication structure. Is that possible? Or, I have to write C code
>to generate a VHDL doc? Are there other better methods? Thanks

You *can* do it with VHDL's if...generate construct.  But it tends
to get pretty clunky, and you may find that a C-based code 
generator is less painful.

VHDL is a ton better than Verilog for this, because you can
freely use functions to manufacture the values of constants
(based on other constants).  Together with VHDL's wonderful
unconstrained array mechanisms, you *should* be able to do
what you need.  But it won't be trivial, and testing it in
all the possible combinations of cases will be a challenge.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 130341
Subject: Re: timing and timing reports (again)
From: Pat <patocarr@gmail.com>
Date: Thu, 20 Mar 2008 11:40:38 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 20, 10:36 am, "u_stad...@yahoo.de" <u_stad...@yahoo.de> wrote:
> hi
>
> ich have question about timing.
> i have an edk design with microblaze (using spartan 3e 500) where i
> use an ip core that i wrote myself.
> when i implement the design i get the following timing output in my
> console.
>
> ------------------------------------------------------------------------------------------------------
>   Constraint                           |  Check  | Worst Case |  Best
> Case | Timing |   Timing
>                                             |             |
> Slack       | Achievable | Errors |    Score
> ------------------------------------------------------------------------------------------------------
> * TS_dcm_48mhz_dcm_48mhz_CLKFX_BUF = PERIOD | SETUP   |
> -1.456ns|    57.246ns|       1|        1456
>    TIMEGRP         "dcm_48mhz_dcm_48mhz_CLK | HOLD    |
> 1.025ns|            |       0|           0
>   FX_BUF" TS_sys_clk_pin / 0.96 HIGH 50%    |         |
> |            |        |
> ------------------------------------------------------------------------------------------------------
>   TS_dcm_0_dcm_0_CLK0_BUF = PERIOD TIMEGRP  | SETUP   |
> 5.532ns|    14.468ns|       0|           0
>   "dcm_0_dcm_0_CLK0_BUF" TS_sys_clk_pin     | HOLD    |
> 0.688ns|            |       0|           0
>        HIGH 50%                             |         |
> |            |        |
> ------------------------------------------------------------------------------------------------------
>   TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | SETUP   |
> 17.975ns|     2.025ns|       0|           0
>   pin" 20 ns HIGH 50%                       | HOLD    |
> 0.667ns|            |       0|           0
> ------------------------------------------------------------------------------------------------------
>
> my constraints in the ucf file  for the clock net are (generated by
> edk):
> Net sys_clk_pin TNM_NET = sys_clk_pin;
> TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 20000 ps;
>
> clearly the dcm_48mhz_dcm_48mhz_CLKFX_BUF does not meet timing. my
> question now is are there are some constraints that i can use to
> achieve timing for that signal. or can i change something in the
> design.
> also when i look at the synthesis report files for the dcm48 and my
> own ip they all get implemented far under their timing requirements.
> is there a report where i can look up the
> dcm_48mhz_dcm_48mhz_CLKFX_BUF signal an why i has such a bad timing?
>
> thanks
> urban

Run the design through Timing Analizer to find out which path(s) are
failing timing.

-P@

Article: 130342
Subject: Modelsim XE III 6.x - huge fonts
From: Dave Pollum <vze24h5m@verizon.net>
Date: Thu, 20 Mar 2008 12:11:54 -0700 (PDT)
Links: << >>  << T >>  << A >>
I'm trying to run the Xilinx version of Modelsim (XE III 6.2g), and it
displays everything in HUGE fonts.  On my 21" monitor, each char is at
least 1" tall.  This happens whether I run Modelsim by itself, or when
I run it from ISE Webpack 9.2.04i.  I've downloaded the latest
versions of both ISE Webpack and Modelsim XE from Xilinx's web site.
I tried searching Xilinx's website but didn't find any answers.  If I
can find an older version of Modelsim, I'll try that, but I'm not sure
where to download it from.
TIA
-Dave Pollum

Article: 130343
Subject: Re: ISE 10.0 finally with multi-threading and SV support ?
From: jb@capsec.org
Date: Thu, 20 Mar 2008 12:30:19 -0700 (PDT)
Links: << >>  << T >>  << A >>
Hello,

> That is easy to do for high level synthesis, next to impossible for
> placement and very difficult for routing.

I did not dig into it -- but I always felt its exact the opposite.
Some time ago, i read most P&R ist based
upon simulated annealing. Is that still true? While SA might not be
the most parallizable
algorithm on earth, it should give you some speedup; at least on
SMP...

Do you've got some read-worthy documents on that topic?


  .

Article: 130344
Subject: Re: Is there a means to conditional synthesis in VHDL?
From: KJ <kkjennings@sbcglobal.net>
Date: Thu, 20 Mar 2008 12:32:41 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 20, 2:07=A0pm, fl <rxjw...@gmail.com> wrote:
<snip>
> I want to use
> multiplier adder graph method for the multiplication.
<snip>
>Are there other better methods? Thanks

If you're targetting an FPGA that has hardware multipliers, a likely
better method is to write your code so that the multiply can be
inferred and implemented using the hardware multiplier.  It's higher
performance, consumes no logic cells and is quicker and easier to
write/debug/maintain.  Take a look at the recommended coding styles
for your intended targetted FPGA.

Kevin Jennings


Article: 130345
Subject: Re: A Challenge for serialized processor design and implementation
From: Jecel <jecel@merlintec.com>
Date: Thu, 20 Mar 2008 12:43:13 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 20, 6:45 am, Kolja Sulimma wrote:
> > [I suggested the Transputer]
>
> Or something similar, more modern: <intellasys>
> 9mW per core at 1GHz.

Well, a FPGA version wouldn't get anywhere near these kinds of
numbers. But I do agree that MISC variations are a very good idea (I
have done some myself and others have suggested some in this thread).
A key MISC feature, the loading of several instructions in a single
memory access, would be missing from a serial implementation, however.

As additional sources of inspiration I would like to mention the
control computer for the Minuteman missile:

http://en.wikipedia.org/wiki/D-17B

and the Kenbak-1 (considered by many as the first personal computer
since it sold for $700 in 1971):

http://en.wikipedia.org/wiki/Kenbak-1
http://www.bitsavers.org/pdf/kenbak/

The documentation for the Kenbak includes a detailed explanation of
how it works as well as all the schematics. It only addressed 256
bytes (in a shift register - not RAM), but otherwise is a pretty neat
design.

-- Jecel

Article: 130346
Subject: Re: Modelsim XE III 6.x - huge fonts
From: Dave Pollum <vze24h5m@verizon.net>
Date: Thu, 20 Mar 2008 12:48:21 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 20, 2:11 pm, Dave Pollum <vze24...@verizon.net> wrote:
> I'm trying to run the Xilinx version of Modelsim (XE III 6.2g), and it
> displays everything in HUGE fonts.  On my 21" monitor, each char is at
> least 1" tall.  This happens whether I run Modelsim by itself, or when
> I run it from ISE Webpack 9.2.04i.  I've downloaded the latest
> versions of both ISE Webpack and Modelsim XE from Xilinx's web site.
> I tried searching Xilinx's website but didn't find any answers.  If I
> can find an older version of Modelsim, I'll try that, but I'm not sure
> where to download it from.
> TIA
> -Dave Pollum

I forgot to mention that I'm running Windows 2000 Prof, SP4.
-Dave Pollum

Article: 130347
Subject: Re: Configuring a Spartan 3A1800 ExtremeDSP from Spartan3 cable?
From: emeb <ebrombaugh@gmail.com>
Date: Thu, 20 Mar 2008 13:17:42 -0700 (PDT)
Links: << >>  << T >>  << A >>
On Mar 20, 7:25 am, Paul Boven <bo...@jive.nl> wrote:
> Hi everyone,
>
> Just ordered a Spartan 3A ExtremeDSP Starter Kit. It comes without a
> programming cable, but I figured I could re-use the cable from my trusty
> Digilent parallel cable from the Spartan-3 kit. The pinout is certainly
> the same (6 pins single header). But I've just noticed that the Digilent
> documentation states there is 2.8V on the connector while the new
> Spartan-3A DSP board provides 2.5V. Will this work?
>
> Regards, Paul Boven.

The Digilent USB<->JTAG cable I bought a few weeks back operates from
1.8V - 5.5V. Which cable do you have?

Eric

Article: 130348
Subject: Re: timing and timing reports (again)
From: "u_stadler@yahoo.de" <u_stadler@yahoo.de>
Date: Thu, 20 Mar 2008 15:02:43 -0700 (PDT)
Links: << >>  << T >>  << A >>
hi

thanks for the tip.
well i did that but to be honest i couldn't quit figure out what to do
with all the info. is there a manual or tutorial what all this means?
if somebody wants to have a look at my design i would appreciate it!
http://193.170.52.132/xilinx/system.ncd
http://193.170.52.132/xilinx/system.pcf

are there perhaps some examples from xilinx that teach you how to use
those tools and to debug?

thanks
urban


Article: 130349
Subject: Re: A Challenge for serialized processor design and implementation
From: Frank Buss <fb@frank-buss.de>
Date: Thu, 20 Mar 2008 23:50:59 +0100
Links: << >>  << T >>  << A >>
Jecel wrote:

> http://en.wikipedia.org/wiki/Kenbak-1
> http://www.bitsavers.org/pdf/kenbak/
> 
> The documentation for the Kenbak includes a detailed explanation of
> how it works as well as all the schematics. It only addressed 256
> bytes (in a shift register - not RAM), but otherwise is a pretty neat
> design.

That's interesting: the instruction set, addressing modes and even the
mnemonics, are looking a bit like the 6502.

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de



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