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"Alan Nishioka" <alan@nishioka.com> wrote in message news:d13512dc-94b3-4533-9cfa-115bf5461b9a@i29g2000prf.googlegroups.com... > > In Amsterdam, I would recommend visiting the Anne Frank House, where > she hid during World War II. That is where she taught herself VHDL > and programmed her first FPGA. not funny :( /MikhailArticle: 130551
Georg Acher wrote: > Jon Elson <elson@pico-systems.com> writes: > >>I got a batch of "Xilinx" Spartan XCS30 FPGAs from a Chinese >>seller, and am having problems with random failures at first >>power up. Sometimes it is a stuck I/O pin, sometimes a failure >>to configure. I first thought maybe we had an ESD problem, but >>I'm now thinking these may be counterfeit. They have white ink >>printed labels on the front, whereas other Xilinx chips have >>laser-etched labels. Also, these Spartan chips don't have the >>Spartan logo just below the Xilinx logo, like my other Xilinx >>chips. Anyone have any comments on this? > > > I have XCS10XL in TQFP100 from around 1999/2000 and they also have printed > labels. They were obtained from the official German distri at that time > (Metronik/Unique). So I guess that white ink labels are no sign of unoffical > chips... > But, I have no other examples of Spartan chips which DON'T have the Spartan(tm) marking right below the Xilinx(tm) logo. That was one of the things that made me curious, although I don't know why a counterfeiter would miss something that obvious. JonArticle: 130552
"BobW" <nimby_NEEDSPAM@roadrunner.com> wrote in message news:M9CdnalC2ZWlh3banZ2dnUVZ_oimnZ2d@giganews.com... > > Mikhail, > > Please explain why you don't find that funny. Please. Bob, Do you REALLY need an explanation of an obvious idea or do you want to start a political flame here? Would you like to make a joke of this http://en.wikipedia.org/wiki/Tanya_Savicheva too? /MikhailArticle: 130553
"MM" <mbmsv@yahoo.com> wrote in message news:650m8hF2e14kfU1@mid.individual.net... > "BobW" <nimby_NEEDSPAM@roadrunner.com> wrote in message > news:M9CdnalC2ZWlh3banZ2dnUVZ_oimnZ2d@giganews.com... >> >> Mikhail, >> >> Please explain why you don't find that funny. Please. > > Bob, > > Do you REALLY need an explanation of an obvious idea or do you want to > start a political flame here? > Would you like to make a joke of this > http://en.wikipedia.org/wiki/Tanya_Savicheva too? > > > /Mikhail > Mikhail, Alan was not making fun of what the Franks (or any other persecuted person) went through before, during, or after WW2. He was poking fun at the OP for making an off-topic post. His suggestion about visiting the Frank House seemed sincere, and he merely added an FPGA twist in an attempt to drive the thread toward on-topicicity. It's akin to people not laughing at the Bavarian cream pie joke because they think it's making fun of a certain group of people. There's no truth to it. It's just a joke. I mean, what terminally-ill person flies all the way from the US to Europe for a piece of Bavarian cream pie, and when he get's there they don't have any, so he says, "Okay, I'll just have coffee." It's not making fun of anyone. It's just a joke. BobArticle: 130554
Ashok Chotai wrote: > Hello, > I am planning to visit Amsterdam and Brussells in July '08 for a week. > What places you would recommend to see for these two cities? This is not really useful for FPGA's but MASER have a site near amsterdam. They do failure analysis and reliability testing. Sorry they don't do VHDL or verilog. Andy > Thanks > Ashok > >Article: 130555
"BobW" <nimby_NEEDSPAM@roadrunner.com> wrote in message news:X9OdnbIQMJTxpHbanZ2dnUVZ_gqdnZ2d@giganews.com... > > Alan was not making fun of what the Franks (or any other persecuted > person) went through before, during, or after WW2. He was poking fun at > the OP for making an off-topic post. His suggestion about visiting the > Frank House seemed sincere, and he merely added an FPGA twist in an > attempt to drive the thread toward on-topicicity. > Bob, I sure hope so, however you need to realize that what's funny for native English speakers is not necessarily funny for Russians or French, etc., and vice versa. In any other case I would say nothing, but there are certain subjects, which are a total taboo for making any fun of (or adding twists to them as you say) in the culture I grew up in... It is considered very low taste and insensitive. With regards to the cream pie joke, it doesn't bother me much, probably because it's fiction not mentioning actual names. However, I don't find it to be very funny either... /MikhailArticle: 130556
On 26 Mar, 18:23, "MM" <mb...@yahoo.com> wrote: > Hi all, > > I was wondering if there is a good VHDL document generation utility (free or > not) out there? I stumbled across an article describing HDLDoc by DualSoft, > which seemed promising, but it seems that that company ceased to exist... I > am looking for something that would be more than just a comments > extractor... > > Thanks, > /Mikhail Hi believe that doxygen now supports VHDL (although I have never actually used it with VHDL). I have briefly used it for S/W (where it is widely used) and find it quite useful (especially the call graphs. Steven StevenArticle: 130557
Hi xilinx geeks, mig2.1 can generate a ddr2 controller only for 3400adsp starter kit. is there a fully tested design suitable for the 1800adsp starter kit available somewhere ? xilinx provides only an edk/mpmc controller in its references designs. thanks, raphArticle: 130558
>>>Hi >>> >>>I have been think and part time working towards a goal to make useable >>>and useful serialized processor. The idea is that it should be >>> >>>1) VERY small when implemented in any modern FPGA (less 25% of >>>smallest device, 1 BRAM) >>>2) be supported by high level compiler (C ?) >>>3) execute code in-place from either serial flash (Winbond quad speed >>>SPI memory delivers 320 mbit/s!) or from file on sd-card >>> >> >> Another advantage would be that it could use serial peripherals. A 16 bit timer with a min prescaling of 16 would be very cheap to implement as a shiftregister. -- Best Regards, Ulf Samuelsson This is intended to be my personal opinion which may, or may not be shared by my employer Atmel Nordic ABArticle: 130559
Mike Treseler wrote: >> The last design I tried on both (A V2-1K, 75% full, 50MHz) Synplify >> Pro was 2 CLB's smaller and 5 Hz faster than XST. > > Unfortunately for mentor, synplicity et. al. > parity has been reached by some fpga vendors > and vendor-independent synthesis licenses > are much harder to justify than they once were. The results are very design specific. I have seen in big timing critical designs that the vendor-independent tools make better end results in terms of density and clock frequency. Also the independent tools are usually much better in inferring complex structures (they tend to find memories in suprising places nowadays :)) Usually it's even hard to get designs that can be used with the two major independent tools trough the vendors tools (due to unsupported VHDL structures, not as good inferring etc.) So it is quite hard to test the vendor tools without major hacking of the code. --KimArticle: 130560
On 26 mar, 17:55, Pablo <pbantu...@gmail.com> wrote: > > Have you use "Export to project navigator " to use Xilinx ISE?? I > don't know if version 9.2 support this utility?. Could you explain me > step by step what you do to know what is the problem? Maybe I didn't use this function. I send you the guide I followed (the problem is at 28 page, highlighted in red) thanksArticle: 130561
> Dear Satan, > I should have changed that nick ... > RTFM. Specifically the constraints guide. Umm... I think I should really do this, you are right ;) > > NET "clk_en_100M" TNM=3DFFS "clock_enable"; > TIMESPEC TS1000 =3D FROM : clock_enable : TO : clock_enable : 100ns =A0; Thank You! > And please, oh dark lord, send my regards to all your little wizards. I'm > looking forward to meeting you all in a few years time. I hope you're > looking after my friends who've already made it to you. Also, I'm practisi= ng > with my violin. hrhr... > > Cheers, Syms. Cheers, tomArticle: 130562
Hi, ISE reports an out of memory error while synthesizing a design which has 10,000 instantiations of a simple verilog module. The module uses Xilinx primitives FDRSE, RAM32X1S and few assign statements and no other type of statement.There are broadcast connections to all above modules from a central controller and some outputs of each module are connected as inputs to the next module in a daisychain manner. When I instantiate this module 1000 times the tool is able to synthesise and implement the design. But for 10,000 instantiations, the Xilinx ISE tool reports an out of memory error during synthesis. I'm using Xilinx ISE evaluation version 9.2i. Target device is Virtex-5 XC5VLX330 and it has plenty of space to accomodate the 10,000 instantiations. The system on which the tool is running has 2GB of memory. Any help in this regard would be greatly appreciated. Thanks in advance AshwiniArticle: 130563
ashwinihs@gmail.com wrote: > Hi, > > ISE reports an out of memory error while synthesizing a design which > has 10,000 instantiations of a simple verilog module. > > > Any help in this regard would be greatly appreciated. > Hi Ashwini, Did you try adding more memory to your computer? HTH., Syms.Article: 130564
Jon Elson <elson@pico-systems.com> writes:
>Georg Acher wrote:
>> I have XCS10XL in TQFP100 from around 1999/2000 and they also have printed
>> labels. They were obtained from the official German distri at that time
>> (Metronik/Unique). So I guess that white ink labels are no sign of unoffical
>> chips...
>>
>
>But, I have no other examples of Spartan chips which DON'T have
>the Spartan(tm) marking right below the Xilinx(tm) logo. That
>was one of the things that made me curious, although I don't
>know why a counterfeiter would miss something that obvious.
My XCS10XL have 5 lines: Xilinx-logo, type, package and date code, lot code and
speed grade. No "Spartan". Maybe it's not on the TQFP/VQFP100 package because
auf the limited area...
--
Georg Acher, acher@in.tum.de
http://www.lrr.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 130565On Thu, 27 Mar 2008 04:03:25 -0700 (PDT), ashwinihs@gmail.com wrote: >Hi, > >ISE reports an out of memory error while synthesizing a design which >has 10,000 instantiations of a simple verilog module. The module uses >Xilinx primitives FDRSE, RAM32X1S and few assign statements and no >other type of statement.There are broadcast connections to all above >modules from a central controller and some outputs of each module are >connected as inputs to the next module in a daisychain manner. > >When I instantiate this module 1000 times the tool is able to >synthesise and implement the design. But for 10,000 instantiations, >the Xilinx ISE tool reports an out of memory error during synthesis. Then insttantiate it 1000 times and create a black box (synthesise that block with no I/O blocks added). Instantiate the black box 10 times in your top level module (attaching a "box_type = black_box" attribute to each instance) The synthesis output files must be available (e.g. in the same directory) when you run the "Translate" stage on the top level module. Searching Xilinx documentation for "black box" should give you details of how to do this. This won't help if the back end tools (Map and PAR) also run out of space. For an LX330, 2GB is not very much... - BrianArticle: 130566
Walter Banks wrote: > > "Ron N." wrote: > >> What's the smallest instruction set supported by an >> existing and available C compiler? Is there a C compiler >> available for any of the tiniest stack machines, or even >> for an OISC (one instruction set computer)? > > I am not sure what the smallest instruction set that a C > compiler has been written for. We have written quite a few > C compilers for processors with unusual instruction sets > and limited resources. > > The key is, > "Can you write code to do +,~, |,>>,conditional branch on z or carry" > > I think that is all that is actually needed. Surely you should include the ability to do indirect calls (or indirect jumps, together with a mechanism for finding the current program counter)? I believe some of the smaller PICs had no indirect call/jump mechanism, which would make it very hard to implement function pointers. You also need to be able to load and store data via a pointer, although I can't think of any cpu I've used which does not have that ability. I'll check the instruction set on my DESMOND* when I get home - that's the smallest instruction set cpu that I have easy access to. Have you every tried writing a C compiler for a Turing machine ? * "Digital electronic system made of nifty devices" - used by the Open University in the UK. > > Some of the implementation may be ugly but it can > be done. A surprising number of the processors 20 years > ago missed some of the logic operators and shifts limited > to rotates. > > Regards, > > -- > Walter Banks > Byte Craft Limited > Tel. (519) 888-6911 > http://www.bytecraft.com > > > > > >Article: 130567
"Ron N." wrote: > What's the smallest instruction set supported by an > existing and available C compiler? Is there a C compiler > available for any of the tiniest stack machines, or even > for an OISC (one instruction set computer)? I am not sure what the smallest instruction set that a C compiler has been written for. We have written quite a few C compilers for processors with unusual instruction sets and limited resources. The key is, "Can you write code to do +,~, |,>>,conditional branch on z or carry" I think that is all that is actually needed. Some of the implementation may be ugly but it can be done. A surprising number of the processors 20 years ago missed some of the logic operators and shifts limited to rotates. Regards, -- Walter Banks Byte Craft Limited Tel. (519) 888-6911 http://www.bytecraft.comArticle: 130568
hi, Did anybody give the new "zpu" core a try located at opencores.org? In a way it's an attractive core with a 32 bits processor which is at the same time very small. Yesterday I compiled the gcc tools for linux. (as usual unfortunately for many opencores projects) the set of vhdl files in different directories is a big mess. several top files, several cpu cores and memory configurations etc. etc. Wondering if anybody got this cpu running with ecos on real hardware. bertArticle: 130569
We have been using Xilinx ISE 8.1 (foundation, evaluation license) and Chipscope Pro 8.1 (evaluation license) with an ML 403 board. Both above tools could talk to the board via a PC IV cable without problems. The trouble started when the evaluation license of Chipscope Pro expired. The original CS Pro install was erased and a reinstall with the new reg. key was done (before erasing, a recursive diff showed that the only difference between the two installs was a single line in the license.dat file). Since the reinstall, whenever CS Pro is invoked from within ISE, the following error messages are output: No other changes have been made to the hardware or software. Any help will be greatly appreciated. RegardsArticle: 130570
> > The key is, > "Can you write code to do +,~, |,>>,conditional branch on z or carry" > > I think that is all that is actually needed. Actually, needed is only ONE instruction, SUBLEQ (SUbtract and Branch if Less than or EQual to zero) - http://en.wikipedia.org/wiki/One_instruction_set_computer or MOVe The Ultimate RISC - http://www.cs.uiowa.edu/~jones/arch/risc/ Everything else can be derived from this ....at "some cost" ;) It's equivalent to NAND gate somehow... Cheers Krzysztof > > Some of the implementation may be ugly but it can > be done. A surprising number of the processors 20 years > ago missed some of the logic operators and shifts limited > to rotates. > > Regards, >Article: 130571
Hi, We have been using Xilinx ISE 8.1 (foundation, evaluation license) and Chipscope Pro 8.1 (evaluation license) with an ML 403 board. Both above tools could talk to the board via a PC IV cable without problems. The trouble started when the evaluation license of Chipscope Pro expired. The original CS Pro install was erased and a reinstall with the new reg. key was done (before erasing, a recursive diff showed that the only difference between the two installs was a single line in the license.dat file). Since the reinstall, whenever CS Pro is invoked from within ISE, the following error messages are output: COMMAND: open_parallel_cable PROXYTYPE=xilinx_parallel4 FREQUENCY=5000000 PORT=LPT1 MODULENAME=libCse_CommProxyPlugin TYPE=xilinx_plugin INFO: Started ChipScope host (localhost:50001) INFO: Opened socket connection: localhost 50001 localhost/127.0.0.1 ERROR: This product is not registered. ChipScope Pro can be purchased online at http://www.xilinx.com/chipscope. ERROR: Failed to open Xilinx Parallel Cable No other changes have been made to the hardware or software. Any help will be greatly appreciated. RegardsArticle: 130572
On Thu, 27 Mar 2008 08:21:16 -0500, Walter Banks <walter@bytecraft.com> wrote: > > >"Ron N." wrote: > >> What's the smallest instruction set supported by an >> existing and available C compiler? Is there a C compiler >> available for any of the tiniest stack machines, or even >> for an OISC (one instruction set computer)? > >I am not sure what the smallest instruction set that a C >compiler has been written for. We have written quite a few >C compilers for processors with unusual instruction sets >and limited resources. > >The key is, >"Can you write code to do +,~, |,>>,conditional branch on z or carry" > >I think that is all that is actually needed. > >Some of the implementation may be ugly but it can >be done. A surprising number of the processors 20 years >ago missed some of the logic operators and shifts limited >to rotates. > >Regards, IIRC first year computer science the requirements for a machine that will run any kind of code at all (a universal Turing Machine) can be surprisingly simple. http://technology.newscientist.com/article/dn12826-simplest-universal-computer-wins-student-25000.html I recall having to write at least one program for a Turing machine: http://en.wikipedia.org/wiki/Turing_machine Anything more just has to do with efficiency, ease of use, and that sort of stuff. Best regards, Spehro Pefhany -- "it's the network..." "The Journey is the reward" speff@interlog.com Info for manufacturers: http://www.trexon.com Embedded software/hardware/analog Info for designers: http://www.speff.comArticle: 130573
Kim Enkovaara wrote:
> The results are very design specific. I have seen in big timing critical
> designs that the vendor-independent tools make better end results in
> terms of density and clock frequency. Also the independent tools are
> usually much better in inferring complex structures (they tend to
> find memories in suprising places nowadays :))
I have seen this also in one tight design.
It is important to keep at least
one vendor-independent synthesis license
for this reason, and as check-off
item for the design and the design rules.
However, if I can fit a standard design and make
Fmax without tying up the fancy licenses,
the group is better off.
> Usually it's even hard to get designs that can be used with the two
> major independent tools trough the vendors tools (due to unsupported
> VHDL structures, not as good inferring etc.) So it is quite hard
> to test the vendor tools without major hacking of the code.
It is possible to construct synchronous design rules
that will pass the front ends of quartus, xst, mentor and synplicity.
It's when I bend the rules with an asynch vendor element like
a PLL or FIFO that testing is complicated.
Sometimes the design can be structured into
synchronous and asynchronous pieces.
-- Mike Treseler
Article: 130574sarah_s wrote: > Hi, > > I have developed a Decoder in verilog and successfully simulated it > on > an FPGA. I am using Actel's ProASIC3E proto kit. Simulink has an > instrument control toolbox which allows one to read and write to the > pc serial port. I plan to have the encoder, modulation and > demodulation blocks > in simulink and want to send the demodulated data to the decoder on > fpga through > serial and recieve the output. How can I do this? My design is > synchronous. It takes 2 bits at every clock cycle which get decoded > into 1bit. Also, what's the > output voltage/current on the pc serial port? If the connect on the > pins directly into one of fpga's input pins on the board.. would I > fry > it? (I don't have a serial port on the fpga proto board). Is this > even > possible? > > > Thanks for the help, > Sarah Hi you cannot connect the pins of a PC serial port directly to a FPGA. I use a tiny selfmade board with a MAX232 chip which translates the levels to standard digital signals (in my case an old spartan 2 protoboard). Take a look at the schematics of spartan3A evaluation boards for other solutions. For the demod data you could use some standard uart cores from internet (opencores.org or http://www.oldcrows.net/~patchell/IpArchive/HdlArchive.html#Uart_Softcore ) Taco
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