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David Brown wrote: > > I am not sure what the smallest instruction set that a C > > compiler has been written for. We have written quite a few > > C compilers for processors with unusual instruction sets > > and limited resources. > > > > The key is, > > "Can you write code to do +,~, |,>>,conditional branch on z or carry" > > > > I think that is all that is actually needed. > > Surely you should include the ability to do indirect calls (or indirect > jumps, together with a mechanism for finding the current program > counter)? I believe some of the smaller PICs had no indirect call/jump > mechanism, which would make it very hard to implement function pointers. We have written a compiler for the 12 bit PIC's. The PC is accessible as a register on these parts. We have written a compiler for a processors that didn't have indirect jump and the PC was not available to be modified. > You also need to be able to load and store data via a pointer, > although I can't think of any cpu I've used which does not have that > ability. Good point. Indirect accesses was missing from my The COP8 has all indirect accesses could only be executed in the current 256 byte page. > Have you every tried writing a C compiler for a Turing machine ? No, but an interesting optimization assignment for a compiler course. It would initiate some abstract thinking. There are at least three move machines around where every operation is a move and there is some logic between some addresses to give it functionality. The GRI Computer Corp built a minicomputer move machine that I first encountered in Mexico being used to do basic data base work in local public health administration offices. All the code for these as far as I know was written in assembler. I wrote a terminal driver for this project. The processor was in-expensive to build but required a lot of code to do anything. There was a startup project in Germany about 10 years ago that had a move machine very similar to the MAXQ. The German project was based on a thesis and from various conversations all three of these evolved separately. GRI in the early 70's the German move machine a few years before MAXQ. The MAXQ has been more of a commercial success than I would have guessed when I first heard about it. Regards, -- Walter Banks Byte Craft Limited Tel. (519) 888-6911 http://www.bytecraft.comArticle: 130576
Krzysztof Kepa wrote: >> The key is, >> "Can you write code to do +,~, |,>>,conditional branch on z or carry" >> >> I think that is all that is actually needed. > > Actually, needed is only ONE instruction, > > SUBLEQ (SUbtract and Branch if Less than or EQual to zero) - > http://en.wikipedia.org/wiki/One_instruction_set_computer > > or MOVe > The Ultimate RISC - http://www.cs.uiowa.edu/~jones/arch/risc/ > > Everything else can be derived from this ....at "some cost" ;) > It's equivalent to NAND gate somehow... I think there is some mis-representation of the definition of RISC vs CISC. The term "reduced" in RISC refers not to the number of instructions, but rather to the reduction in the number of functions that a single instruction performs. The idea of RISC is that "smart" compilers can rearrange these simpler (reduced) instructions to perform larger operations more efficiently. The SUBLEQ instruction as described on the Wikipedia page is *very* CISC in that it performs loads, stores, arithmetic, condition code testing, and branching all in a single instruction. -- Michael N. Moran (h) 770 516 7918 5009 Old Field Ct. (c) 678 521 5460 Kennesaw, GA, USA 30144 http://mnmoran.org "So often times it happens, that we live our lives in chains and we never even know we have the key." "Already Gone" by Jack Tempchin (recorded by The Eagles) The Beatles were wrong: 1 & 1 & 1 is 1Article: 130577
Walter,
>>
>> Actually, needed is only ONE instruction,
>>
>> SUBLEQ (SUbtract and Branch if Less than or EQual to zero) -
>> http://en.wikipedia.org/wiki/One_instruction_set_computer
>>
>> or MOVe
>> The Ultimate RISC - http://www.cs.uiowa.edu/~jones/arch/risc/
>>
>> Everything else can be derived from this ....at "some cost" ;)
>> It's equivalent to NAND gate somehow...
>
> Interesting...
>
> It will take some thought on how to implement the right shift
> and logical operators.
>
> Walter..
>
With SUBLEQ instruction you'd have to produce result that is equivalent to
SHR. It is doable, but not quite time efficient, i.e. it can be done
"manually" by subtracting values an slowly building up value equal to a
half of the shifted val (as SHR = DIV by 2).
Not efficient at all, but this sort of processing is just a theoretical
figure, so don't expect sophistication of such high-level asm instruction
like SHR ;)
Good book on computer arithmetic/architecture could help here...
With MOVe (UltimateRISC) its easier, as you can hook useful bunch of logic
up to the particular addresses and just throw the data between them.
It even get its 5 min on the FPL back in '98.
@inproceedings{738909,
author = {Adam Donlin},
title = {Self Modifying Circuitry - A Platform for Tractable Virtual
Circuitry},
booktitle = {FPL '98: Proceedings of the 8th International Workshop on
Field-Programmable Logic and Applications, From FPGAs to Computing
Paradigm},
year = {1998},
isbn = {3-540-64948-4},
pages = {199--208},
publisher = {Springer-Verlag},
address = {London, UK},
}Cheers
Krzysztof
Article: 130578Krzysztof Kepa wrote: > > > > The key is, > > "Can you write code to do +,~, |,>>,conditional branch on z or carry" > > > > I think that is all that is actually needed. > > Actually, needed is only ONE instruction, > > SUBLEQ (SUbtract and Branch if Less than or EQual to zero) - > http://en.wikipedia.org/wiki/One_instruction_set_computer > > or MOVe > The Ultimate RISC - http://www.cs.uiowa.edu/~jones/arch/risc/ > > Everything else can be derived from this ....at "some cost" ;) > It's equivalent to NAND gate somehow... Interesting... It will take some thought on how to implement the right shift and logical operators. Walter..Article: 130579
> I think there is some mis-representation of the > definition of RISC vs CISC. The term "reduced" in RISC > refers not to the number of instructions, but rather > to the reduction in the number of functions that a > single instruction performs. > > The idea of RISC is that "smart" compilers can > rearrange these simpler (reduced) instructions > to perform larger operations more efficiently. > > The SUBLEQ instruction as described on the Wikipedia > page is *very* CISC in that it performs loads, > stores, arithmetic, condition code testing, and > branching all in a single instruction. I agree with you. However, plethora of taxonomies CISC/RISC/DISC/OISC, SISD/SIMD/MISD/MIMD, hardware/software/configware and so on gives the opportunity that everybody finds what he feels comfortable with... Cheers, KrzysztofArticle: 130580
"MM" <mbmsv@yahoo.com> wrote: >Hi all, > >I was wondering if there is a good VHDL document generation utility (free or >not) out there? I stumbled across an article describing HDLDoc by DualSoft, >which seemed promising, but it seems that that company ceased to exist... I >am looking for something that would be more than just a comments >extractor... Anyone using such a utility on my watch is fired immediately. Proper documentation describes the idea behind an implementation. Tools like doxygen produce nice looking documents, but the contents of the documents are useless because the idea behind it all is missing. -- Programmeren in Almere? E-mail naar nico@nctdevpuntnl (punt=.)Article: 130581
On Mar 27, 8:45 am, Brian Drummond <brian_drumm...@btconnect.com> wrote: > On Thu, 27 Mar 2008 04:03:25 -0700 (PDT), ashwin...@gmail.com wrote: > >Hi, > > >ISE reports an out of memory error while synthesizing a design which > >has 10,000 instantiations of a simple verilog module. The module uses > >Xilinx primitives FDRSE, RAM32X1S and few assign statements and no > >other type of statement.There are broadcast connections to all above > >modules from a central controller and some outputs of each module are > >connected as inputs to the next module in a daisychain manner. > > >When I instantiate this module 1000 times the tool is able to > >synthesise and implement the design. But for 10,000 instantiations, > >the Xilinx ISE tool reports an out of memory error during synthesis. > > Then insttantiate it 1000 times and create a black box (synthesise that block > with no I/O blocks added). > > Instantiate the black box 10 times in your top level module (attaching a > "box_type = black_box" attribute to each instance) > > The synthesis output files must be available (e.g. in the same directory) when > you run the "Translate" stage on the top level module. > > Searching Xilinx documentation for "black box" should give you details of how to > do this. > > This won't help if the back end tools (Map and PAR) also run out of space. > For an LX330, 2GB is not very much... > > - Brian Here is the link to the memory requirements for the Xilinx tools and the corresponding parts: http://www.xilinx.com/ise/products/memory.htm Make sure you have those requirements. I remember telling some of Xilinx ISE developers about my setup and how I had "plenty of RAM w/ 2GB" and they chimed in with having designs that wouldn't build on only 2GB of RAM.Article: 130582
Georg Acher wrote: > Jon Elson <elson@pico-systems.com> writes: > >>Georg Acher wrote: > > >>>I have XCS10XL in TQFP100 from around 1999/2000 and they also have printed >>>labels. They were obtained from the official German distri at that time >>>(Metronik/Unique). So I guess that white ink labels are no sign of unoffical >>>chips... >>> >> >>But, I have no other examples of Spartan chips which DON'T have >>the Spartan(tm) marking right below the Xilinx(tm) logo. That >>was one of the things that made me curious, although I don't >>know why a counterfeiter would miss something that obvious. > > > My XCS10XL have 5 lines: Xilinx-logo, type, package and date code, lot code and > speed grade. No "Spartan". Maybe it's not on the TQFP/VQFP100 package because > auf the limited area... > OK, well that's good to know. But, the chips in question are TQ144, I have some just 20 weeks newer, and they have the Spartan logo on them, the label otherwise looks very similar. Anyway, I sent photos to Xilinx, and am waiting to hear if they can tell anything from a picture. I'm on pins and needles not knowing if I have some kind of process-related problem or a batch of bad chips. I have shipped half of this batch already, so if the chips are failing slowly, they are going to be seeing problems too. Not a good feeling! JonArticle: 130583
Can we stop this silly thread. The OP told me that he posted this accidentally, by hitting the wrong button. No reason for us to perpetuate his mistake... Peter AlfkeArticle: 130584
Nico Coesel wrote:
> Anyone using such a utility on my watch is fired immediately. Proper
> documentation describes the idea behind an implementation. Tools like
> doxygen produce nice looking documents, but the contents of the
> documents are useless because the idea behind it all is missing.
I like to demonstrate this "idea behind it all" in
working and well-commented testbench procedures.
It is a rare exception when anyone other than the
developers care about this level of detail.
...and, if I ever have to work for Nico,
I will at least make it through the first day.
(but probably not much longer ;)
-- Mike Treseler
Article: 130585On Mar 27, 7:33 am, Walter Banks <wal...@bytecraft.com> wrote: > David Brown wrote: > > > I am not sure what the smallest instruction set that a C > > > compiler has been written for. We have written quite a few > > > C compilers for processors with unusual instruction sets > > > and limited resources. > > > > The key is, > > > "Can you write code to do +,~, |,>>,conditional branch on z or carry" > > > > I think that is all that is actually needed. Implementation details: either you would need 3-address instructions, or some form of load/store operations (indirect to support C pointers) to a small stack or small register set. C subroutine support would also seem to require some sort of push PC, and either pop PC or jmp indirect operations. Also, couldn't a nand or nor operator replace the bitwise-invert and "or" operators above? Can anyone point out a C compiler that supports an instruction set this minimal? Can something like LLVM target this small an instruction set? Thanks. -- rhn A.T nicholson d.0.t C-o-MArticle: 130586
"Mike Treseler" <mike_treseler@comcast.net> wrote in message news:65241lF2dqaavU1@mid.individual.net... > Nico Coesel wrote: > >> Anyone using such a utility on my watch is fired immediately. Proper >> documentation describes the idea behind an implementation. Tools like >> doxygen produce nice looking documents, but the contents of the >> documents are useless because the idea behind it all is missing. > > I like to demonstrate this "idea behind it all" in > working and well-commented testbench procedures. > It is a rare exception when anyone other than the > developers care about this level of detail. > One problem with commented testbench procedures though is that those procedures are only testing the certain subset of conditions under which the thing has been tested and verified which is many times a subset of the entire ways that the design will actually operate out in the wild. If you follow the test driven development methodology then your testbench (and therefore the commented code) will be created first before the design so it would be available to the other developers. If you create the design first and then the testbench for that design, then the documentation for those other developers might not be ready when they need it when performing concurrent design. <soapbox> Personally, I prefer creating a design specification. High level design and architectural decisions are made before design or testbench code gets written, putting those decisions into some tangible form and keeping that document up to date are not that hard to do. Plus, by creating such documentation, you can have actual live links to reference information that would be useful to whoever it is that would read the document. After the fact documentation is always tedious, dull and nearly pointless. Presumably 'somebody' needs information on how your design is supposed to work so that they can create their design so that the two can be integrated into a final system (unless of course that 'somebody' is yourself). So, except for the one man show, this after the fact documentation is almost guaranteed to be too late so even if the only audience is the developers, those developers do need the info, they need it in a timely manner to do their part and unless you like to answer phone/e-mails regarding how it eventually will work (and probably giving conflicting answers over the time period that you're creating the design), the design spec provides the common ground for all, filling it out more of the details as one goes along, gives everybody the up to date info that they need to do their job. Using a tool to extract this information after the fact is generally more work than to have simply put that exact same information into a design specification. </soapbox> > ...and, if I ever have to work for Nico, > I will at least make it through the first day. > (but probably not much longer ;) > Ya might've even missed out on the interview ;) Kevin JenningsArticle: 130587
Hi all, Hope to get some guidance here. Target device is the Virtex-5 SX50T on the ML506 eval board. I'm trying to build two independent Aurora links on one GTP tile. Independent meaning the two links will have to start/stop transmitting separate data streams individually. Data rate, clocks, resets, etc. can be the same. I opened a webcase with Xilinx. They told me this is not one of the supported modes of operation of the GTP, they can not provide any guidance. The application engineer said that he've heard about other customers that have done something similar, and he believes that they've got it working. Other than telling me this is possible, no other help was offered. So I go ahead and generated the VHDL example code from ISE's CoreGen wizard. I use two switch signals from a DIP switch on the eval board and called them tx_select(1:0). Hoping to use them to disable individual lanes. I tried AND-ing tx_select(1:0) with signals like TXINHIBIT0, TXINHIBIT1, TXPOWERDOWN0 and TXPOWERDOWN1 in gtp_wrapper.vhd with no success. When I do that, the lane_up signal for the disabled lane will be low, but the channel_up signal will be low as well. Meaning no transmission if one of the lanes is down. I even saw that on the scope. I would like to enable/disable the transmission of one lane without affect the other. Any help will be greatly appreciated, TIA! ScottArticle: 130588
Walter Banks <walter@bytecraft.com> writes: > "Ron N." wrote: > > > What's the smallest instruction set supported by an > > existing and available C compiler? Is there a C compiler > > available for any of the tiniest stack machines, or even > > for an OISC (one instruction set computer)? > > I am not sure what the smallest instruction set that a C > compiler has been written for. We have written quite a few > C compilers for processors with unusual instruction sets > and limited resources. > > The key is, > "Can you write code to do +,~, |,>>,conditional branch on > z or carry" You need XOR for add/subtract so it can be one of the operations at little extra cost. Some sort of CALL and RETURN is needed for the processor to be useful. AND is needed as well. > I think that is all that is actually needed. > > Some of the implementation may be ugly but it can > be done. A surprising number of the processors 20 years > ago missed some of the logic operators and > shifts limited to rotates. ^^^^^^^^^^^^^^^^^^^^^^^^^ as with ARM?Article: 130589
Joseph wrote: > Hi all, > > I am simulating a entity with Modelsim via Xilinx Webpack. Modelsim > only displays the input/output signals of the simulated top entity. > > Is there a way of viewing the internal signals declared in the > architecture of the entity without adding them to the port outputs of > the simulated top entity? > > Thanks very much > > Regards > > Joseph I don't know if this will help you, but I've noticed that the new version of Modelsim optimizes away internal signals by default. I have to use a new argument in vsim: vsim -voptargs="+acc" test -KevinArticle: 130590
Ulf Samuelsson wrote: >>>>Hi >>>> >>>>I have been think and part time working towards a goal to make useable >>>>and useful serialized processor. The idea is that it should be >>>> >>>>1) VERY small when implemented in any modern FPGA (less 25% of >>>>smallest device, 1 BRAM) >>>>2) be supported by high level compiler (C ?) >>>>3) execute code in-place from either serial flash (Winbond quad speed >>>>SPI memory delivers 320 mbit/s!) or from file on sd-card >>>> >>> >>> > > > Another advantage would be that it could use serial peripherals. > A 16 bit timer with a min prescaling of 16 would be very cheap > to implement as a shiftregister. and a SPI port should be simple :) (at least at one CLK speed) -jgArticle: 130591
Everett M. Greene wrote: > Walter Banks <walter@bytecraft.com> writes: >>be done. A surprising number of the processors 20 years >>ago missed some of the logic operators and >>shifts limited to rotates. > > ^^^^^^^^^^^^^^^^^^^^^^^^^ > as with ARM?T The ARM can do logical, arithmetic abd rorates. AndyArticle: 130592
Hey, I have to run these codes related to jpeg compression and motion estimation (dct, quantization etc.....), in order to do that i have to first upload an image into the ram of the fpga. i'm using a virtex4 fpga and the board has a 4 mb flash on it. I need directions as to how i can download the image and how to call for the image from my code. Thanks!!!Article: 130593
On Mar 27, 10:14 am, morphiend <morphi...@gmail.com> wrote: > On Mar 27, 8:45 am, Brian Drummond <brian_drumm...@btconnect.com> > wrote: > > > > > On Thu, 27 Mar 2008 04:03:25 -0700 (PDT), ashwin...@gmail.com wrote: > > >Hi, > > > >ISE reports an out of memory error while synthesizing a design which > > >has 10,000 instantiations of a simple verilog module. The module uses > > >Xilinx primitives FDRSE, RAM32X1S and few assign statements and no > > >other type of statement.There are broadcast connections to all above > > >modules from a central controller and some outputs of each module are > > >connected as inputs to the next module in a daisychain manner. > > > >When I instantiate this module 1000 times the tool is able to > > >synthesise and implement the design. But for 10,000 instantiations, > > >the Xilinx ISE tool reports an out of memory error during synthesis. > > > Then insttantiate it 1000 times and create a black box (synthesise that block > > with no I/O blocks added). > > > Instantiate the black box 10 times in your top level module (attaching a > > "box_type = black_box" attribute to each instance) > > > The synthesis output files must be available (e.g. in the same directory) when > > you run the "Translate" stage on the top level module. > > > Searching Xilinx documentation for "black box" should give you details of how to > > do this. > > > This won't help if the back end tools (Map and PAR) also run out of space. > > For an LX330, 2GB is not very much... > > > - Brian > > Here is the link to the memory requirements for the Xilinx tools and > the corresponding parts:http://www.xilinx.com/ise/products/memory.htm > > Make sure you have those requirements. I remember telling some of > Xilinx ISE developers about my setup and how I had "plenty of RAM w/ > 2GB" and they chimed in with having designs that wouldn't build on > only 2GB of RAM. If you install more than 2GB in your Win32 machine, I believe that is some magic fiddling you need to to to allow a user program to use up to 3GB memory. I believe Xilinx has notes on how to do this. John ProvidenzaArticle: 130594
"Everett M. Greene" wrote: > Walter Banks <walter@bytecraft.com> writes: > > "Ron N." wrote: > > > > > What's the smallest instruction set supported by an > > > existing and available C compiler? Is there a C compiler > > > available for any of the tiniest stack machines, or even > > > for an OISC (one instruction set computer)? > > > > I am not sure what the smallest instruction set that a C > > compiler has been written for. We have written quite a few > > C compilers for processors with unusual instruction sets > > and limited resources. > > > > The key is, > > "Can you write code to do +,~, |,>>,conditional branch on > > z or carry" > > You need XOR for add/subtract so it can be one of the > operations at little extra cost. Some sort of CALL > and RETURN is needed for the processor to be useful. > AND is needed as well. Call return can be implemented it is just slow. We have created a compiler for at least one processor without call return w..Article: 130595
"Ron N." wrote: > On Mar 27, 7:33 am, Walter Banks <wal...@bytecraft.com> wrote: > > > > > > The key is, > > > > "Can you write code to do +,~, |,>>,conditional branch on z or carry" > > > > > > I think that is all that is actually needed. > > Implementation details: either you would need 3-address > instructions, or some form of load/store operations > (indirect to support C pointers) to a small stack or > small register set. C subroutine support would also > seem to require some sort of push PC, and either pop PC > or jmp indirect operations. Also, couldn't a nand or nor > operator replace the bitwise-invert and "or" operators > above? > > Can anyone point out a C compiler that supports an > instruction set this minimal? We have implemented C compilers with missing instructions just not all the instructions alluded to in the post. To implement a C compiler there are about 90 basic sequences that need to be defined. After that 1400 rules or so are needed to generate reasonable code. > Can something like > LLVM target this small an instruction set? LLVM despite its goals is not likely to generally succeed very well in diverse targets. It is an approach many commercial compiler companies including ours has tried and abandoned. Regards, -- Walter Banks Byte Craft Limited Tel. (519) 888-6911 http://www.bytecraft.comArticle: 130596
On Jan 24, 8:08 pm, RK <sun.ra...@gmail.com> wrote:
> Hi There,
>
> I am getting the following error in modelsim when I try to simulate
> some thing.
>
> # Loading C:\Xilinx92i\smartmodel\nt\installed_nt/lib/pcnt.lib/ swiftpli_mti.dll
> # ** Error: (vsim-3193) Load of "C:\Xilinx92i\smartmodel\nt\installed_nt/lib/pcnt.lib/swiftpli_mti.dll" failed: DLL dependent library not found.
> # ** Error: (vsim-PLI-3002) Failed to load PLI object file "C:\Xilinx92i\smartmodel\nt\installed_nt/lib/pcnt.lib/swiftpli_mti.dll".
> # Region: /
>
> I have no idea why this is coming up....any help please!
>
> Thanks
> Kris
>
> PS: I am using Modelsim PE and Xilinx ISE.
Hello,
I also had this problem, and came across this post while trying to
solve it. It took a while, but I finally found a solution that works
with Xilinx ISE 9.2i. I haven't seen the solution anywhere else online
so I thought I'd post it somewhere. Here's some info about by system:
Dell Precision 690
Windows XP Pro 64-bit Edition
Intel Xeon 3.0 GHz (2 quad-core CPUs)
8 GB RAM
Xilinx ISE 9.2 SP4 64-bit
Modelsim SE Plus 6.3c
The error is thrown because Modelsim can't find the smartmodel
libraries. You need to compile the libraries and tell Modelsim where
to find them.
32-bit ISE library compilation:
If you do a Google search, you'll find that there are 3 ways to do
this with a Windows OS. This is fairly straightforward:
1) Go to Start > Programs > Xilinx 9.2i > Accessories > Simulator
Library Compilation Wizard
Follow the steps to compile the libraries, making sure the option
for compiling smartmodels is selected
2) Create a Xilinx Project within ISE for your design. (Make sure you
use the choose the correct target FPGA) Select Behavioral Simulation
from the "Sources for:" drop-down near the upper-left corner of the
window. Right-click the Compile HDL Simulation Libraries task under
Design Utilities in the Processes pane. Make sure the smartmodels
option is selected, and run this task.
3) Open up a command line (Start > Run > cmd). Run the following
command: "compxlib -arch virtex5 -s mti_se -smartmodel_setup -w"
64-bit ISE library compilation:
Problem: There seems to be a nasty but subtle bug in the 64-bit
version where the smartmodel directory is never created during
installation (unlike the 32-bit version). However, the LMC_HOME
environment variable is set by the installer, and points to C:
\Xilinx92i\smartmodel\nt64\installed_nt64. Apparently they had a plan
regarding where the library should live, but just forgot to create it.
If you follow any of the steps above for compiling the libraries, you
may or may not notice the little WARNING (not error) in the log about
a non-existent directory or null list. This is the compiler saying
"$LMC_HOME doesn't exist so I won't save the library I just compiled,
but I'll claim success with a warning". (Sorry if I sound a little
bitter, its very frustrating!)
Solution: You have to manually create this directory, and then
recompile the libraries (follow the instructions above for 32-bit
ISE). An hour later when everything has compiled, you should see a
bunch of folders in your new directory. If not, make sure the
directory you created matches the value of $LMC_HOME (at a command
prompt, type "cd %LMC_HOME%")
Updating Modelsim configuration:
You need to manually open $MODEL_TECH\modelsim.ini (and any *.mpf
project files you're using) with a text editor and make the following
changes. Modelsim.ini is set to read-only by default, so you may need
to disable that in order to save your changes. These changes are
recommended by Xilinx Answer #24800
1) Change the line "Resolution = ns" to "Resolution = ps" (otherwise
DCM models will complain)
2) Add a ";" in front of the line "PathSeparator = /" to comment it
out. (This is apparently to fix the problem of mixed / and \ symbols
in various paths. For example, $LMC_HOME and $XILINX use "\" in paths
while everything else in modelsim-land uses "/")
3) After the line that starts with ";Veriuser=", add the following
line (note that Xilinx Answer #24800 uses "/" here instead of "\".
Modelsim complained about this so I changed it)
"Veriuser=$LMC_HOME\lib\pcnt.lib\swiftpli_mti.dll"
4) Remove the semicolon from the beginning of the following lines to
uncomment them:
"libsm = $MODEL_TECH/libsm.dll"
"libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll"
Updating the environment:
As recommended by by Xilinx Answer #24800, make sure that %LMC_HOME%
\lib\pcnt.lib is in the Path under System variables.
Hope this helps,
John
PS: Here are some related links that may be helpful
Xilinx AR #24800 - ModelSim (SE, PE) SmartModel/SWIFT Interface - How
do I use the MGT and PPC SmartModels in ModelSim for ISE 9.1x and
above?
http://www.xilinx.com/support/answers/24800.htm
AR #24153 - 9.1i SmartModel, Simulation - Can I use 64-bit simulators
and OS with Xilinx SmartModels?
http://www.xilinx.com/support/answers/24153.htm
ISE9.2 Win 64-bit SmartModel Location
http://forums.xilinx.com/xlnx/board/message?board.id=ISE&thread.id=778
AR #12793 - 9.2i Install - How do I run the 32-bit version of ISE on a
64-bit system? Can I install both 32-bit and 64-bit ISE to the same
folder?
http://www.xilinx.com/support/answers/12793.htm
Modelsim Error: component 'this-and-that' is unbound
http://forums.xilinx.com/xlnx/board/message?board.id=ISE&message.id=1456
Forum where all this is posted: problem simulating in modelsim -
swiftpli_mti.dll
http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/7c3518d418a6a268
Article: 130597water9580@yahoo.com wrote: > On Mar 27, 6:23 am, Rube Bumpkin <Some...@somewhere.world> wrote: >> water9...@yahoo.com wrote: >>> On Mar 25, 1:17 pm, John_H <newsgr...@johnhandwork.com> wrote: >>>> water9...@yahoo.com wrote: >>>>> no reply? >>>>> water9...@yahoo.com wrote: >>>>>> The Linux lspci -xxx command can show my PCIE device header >>>>>> space(0x00~0xFF). However,simultaneity,the Correctable Error and >>>>>> Unsupported Request error from PCIE Capabilities device status >>>>>> register are set. >>>>>> I run the PCI Express Configuration Testing program from PCISIG to >>>>>> test configure space.The system is halt after click run all test.Reset >>>>>> PC and report NMI error. >>>>>> why? >>>>>> My configuration: PCIEx1, 16bit customize GTP wrapper same as Endpoint >>>>>> x1 IP. >>>> Do you see anything unusual from your PCI Express protocol analyzer? >>> No,i didn't use any protocol analyzer. Only PCISIG Configuration >>> Testing program >> If this is your first PCI Express design, you need to think about >> getting some tools. PCI-SIG recommends a scope with at least 6GHz of >> bandwidth. There are a couple of different companies that have PCIE >> analyzer solutions. You need to buy, rent, or borrow one. >> >> I've run compliance testing in the Gold suite at PCI-SIG workshops. It >> takes me just a couple of minutes to identify the folks that designed >> and built a device without having the right tools. There's a real >> surprised look on their face when they see the waveforms. Sometimes we >> spend the entire scheduled testing period just debugging their design, >> electrically. >> >> If your device is failing the Config Test program, you may need to write >> some low-level code to generate some simple cycles. You'll want to start >> with a single Cfg Read, Type 0 of Register 0, and look at the results. >> Follow that up with more reads and writes, stepping through the >> enumeration process. If you don't want to do that, the same companies >> that make analyzers make exercisers that can generate the necessary >> cycles and show you the result of the completions. >> >> Good luck... >> >> RB > > but,i use a simple tool of windows ,eg:Pcitree. it can read out my > PCIE device header content. > > why ompliance testing prgrame not? Yes, but PCITree can't tell you why the values that you are reading are wrong. Is it an electrical problem, or a protocol problem? RBArticle: 130598
Hi Bin, bin.arthur@gmail.com wrote: > I have spent the past few months slowly trying to get a PCI design > with Linux 2.6 on the Virtex 4. I have been able to overcome some of > the hurdles; however, I am still unable to boot up a working system. > If anyone has tried to do this (or has already done this) I would > apprecaite any help or suggestions. I can go into more detail as to > what I have done and where I am stuck if there is anyone who would be > willing to guide me! Are you using MicroBlaze or PPC? Have you verified PCI functionality with low level test apps - ie do a standalone EDK application that executes a PCI scan, make sure you can see the configuration space, do some simple config setup and try to move some data around. If that's all working, then in Linux the PPC kernel uses more or less mainline PPC PCI handling code - you just need to do have some Xilinx-specific setup to enable the bridge, and you also need to tweak the config_read and _write routines to only do word accesses. Post on the linuxppc-embedded list to tap into the right channel. Regards, JohnArticle: 130599
grky wrote: > Hey, > I have to run these codes related to jpeg compression and motion > estimation (dct, quantization etc.....), in order to do that i have > to first upload an image into the ram of the fpga. i'm using a virtex4 > fpga and the board has a 4 mb flash on it. I need directions as to how > i can download the image and how to call for the image from my code. > > > Thanks!!! Dear Grky, Did you win your place at Nevada in a poker game? :-) I'm guessing you're a linebacker. Great post! Cheers, Syms.
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