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Hi Vladimir,
for questions like this one comp.lang.vhdl is the prefered forum.
Your Code is just too complicated.
I assume you want to practice with generics and loops.
1.) beeraka already mentiond that your loop is wrong (just for
completeness)
for i in 1 to n-2 loop
2.) You are assigning values to a signal tmp1 in a process.
These values are not readable in while the process runs the first
time. The Signal drivers are only updated at the end of a process.
To force the process to run a second time (and more if needed) you
need to include tmp1 in the sensitivity list of the process.
This would increase simulation time!
Maybe you should consider using variables instead.
You also just need a simple std_logic this way:
e.g.:
process(input)
variable tmp1 : std_logic;
begin
tmp1 := '1'; -- initialize with default
-- erased by the first '0' found
for i in 0 to n-1 loop
tmp1 := input(i) and tmp;
end loop;
output <= tmp1;
end process;
Have a nice synthesis
Eilert
VladimirM schrieb
> Hello,
> I'm beginner in VHDL and practice with Xilinx ISE 9.2. I want to test and8
> with generic, the code is similiar to "Circuit Design with VHDL" books code
> and I don't understand where is problem. The synthesiser shows error: "Line
> 19. parse error, unexpected RANGE"
>
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> entity gener_test is
> generic(n: integer := 8);
> port (input: in std_logic_vector(n-1 downto 0);
> output: out std_logic);
> end gener_test;
>
> architecture Behavioral of gener_test is
> signal tmp1: std_logic_vector(n-2 downto 0);
> --signal tmp2: std_logic;
> begin
> process(input)
> begin
> tmp1(0) <= input(0) and input(1);
> for i in range (1 to n-2) loop
> tmp1(i) <= input(i+1) and tmp(i-1);
> end loop;
> output <= tmp1(n-2);
> end process;
>
> end Behavioral;
>
>
Article: 124726Hi all, We are trying to do the same as in XAPP 704 in the simple examples. All on a Xilinx Virtex4 SX. We have LVDS inputs, ISERDES, a FIFO, which is all fine. As soon as we try to connect the output of the FIFO with a BlockRAM, it cannot be mapped anymore. Funny enough, the placer complains about the ISERDES, although without the BlockRAM they are fine. ERROR:Place:605 - I/O component "data_in_p<0>" is associated with ILOGIC component "ADC_DATA_IN_inst/RX_CLK_AND_DAT_inst/ISERDES_inst_master_0" . These components have to be placed in the same I/O tile into adjacent locations. The following issue has been detected: This structured logic must be placed in a specific relative placement form and with a specific alignment on the CLB-grid. Some of the logic associated with this structure is locked. This should cause the rest of the logic to be locked. The location, the logic would be locked to is not correctly aligned. The problem was found at component ADC_DATA_IN_inst/RX_CLK_AND_DAT_inst/ISERDES_inst_slave_0 that would have to be locked at site ILOGIC_X2Y39. How can we store the input data from the FIFO into a BlockRAM? Could it be that the BlockRAM is to far away? Different clock region? Would another Buffer or FIFO in between help? Thanks for all suggestions.Article: 124727
On 2 Okt., 01:58, Narsi <pna...@gmail.com> wrote: > Hi, > > Is there any body uses the Large FPGA to build test and > measurements equipments. > If you use it, how big is the idle FPGA for you. We build measurement equipment, but none of the FPGAs that we use are idle. Therefore I can't answer your question exactly. However, most FPGAs that we use are between 3cm and 4cm in size. Kolja SulimmaArticle: 124728
Hi, thanks for the answers. I know it should not be difficult to implement the module in Hardware (or SW). But i would like to calculate the operation as quick as possible. In the case of Hardware, i should attach the module to the processor of my system using a bus, and thus with a few more extra cycles. I just would like to be sure that the Microblaze Prozessor does not have such an instruction and know if some of you have already had experiences with CLZ in a EDK system. Thx againArticle: 124729
Dan K wrote: > Ok, this doesn't have much to do with fpga's, but I need some help and you > guys are a great knowledge base. > > In all our designs we use an ARM7 microcontroller, a flash, and a FPGA. The > ARM powers up and downloads the fpga and we are "up". We have been using a > Macraigor "Wiggler" to initially program the flash, or to re-program the > flash after we screw up programming and kill the boot sector. Recently we > upgraded the Wiggler code (without backing up our system - really stupid!) > and since then, we have not been able to program the flash on a couple of > our products while our other products seem to program just fine. We have > sent boards to Macraigor and have asked for old code to see if we could at > least get back to where we were, but they have been very unresponsive and > say they don't even keep copies of microcode that's over a couple years old. > So anyway, is there a wiggler clone out there somewhere that we could buy > and get on with life? We are tired of fighting with Macraigor and more > tired of not being able to reliably program our products. > > Thanks > > Dan > > > Use Amontec JTAGkey + SVF Player for downloading your FPGA code when prototyping (suppoerted FPGA are Altera Lattice Xilinx ...) Use Amontec JTAGkey + OpenOCD for downloading and debugging your ARM. Amontec JTAGkey is supporting : - ARM7 / ARM9 debuggging, programming, flashing - FPGA / CPLD erasing, programming, checking more from http://www.amontec.com LaurentArticle: 124730
Hi, It's better to add the HW module to FSL instead to the bus. There is currently no CLZ instruction for MicroBlaze. You can however do an optimized software implementation by using the pcmbf instruction. The instruction will compare a register with another register byte-wise and you will get the number of bytes that matches from left to right. So if you have the value you want to do a CLZ in a register, you can do a pcmbf against register 0 which always is 0. You will know in which byte the first leading '1' is located and can after that do 8 bit search inside that byte. It will not be done in one clock cycle but is most likely much faster than do a 32-bit search for the first '1'. Goran BilskiArticle: 124731
Antti wrote: > On 29 Sep., 04:49, Peter Alfke <al...@sbcglobal.net> wrote: > >>On Sep 28, 5:05 pm, John Adair <g...@enterpoint.co.uk> wrote:> Austin >> >> >>>Might be worth making the suggestion to your sister grouping of GPD of >>>adding a dedicated oscillator crcuit to their range of products. Given >>>a lot of micros do that already there would be some logic in adding >>>such a circuit in the future to the low cost sector FPGA families. >> >>John, "been there, done that". >>XC3000 used to have a single-stage dedicated inverter, exactly for >>that purpose. It caused us a lot of support grief. Between 32 kHz and >>100 MHz, there is a big variation in xtals, and there also was a >>sensitivity to Vcc ramp-up rate. Nobody wants a circuit to work "most >>of the time". >>I also remember that many of the Intel mask revisions of the 8051 were >>oscillator-related. (We second-sourced that at AMD) >>My advice has always been: spend a few pennies on an oscillator >>circuit made by specialists for a special purpose. And definitely do >>not abuse a multi-stage I/O circuit to be the xtal inverter circuit. >>Far too much gain and uncontrolled phase changes at very high >>frequencies. >>Peter Alfke > > > a few pennies? > FPGA prices start from 2 USD, so extra 20 penny for the oscillator is > over 10% of the FPGA cost. > > there is magic thing called specification: if the oscillator would > work reliable with 10 to 100MHz range then its sufficient to include > that in the spec, and no-one would expect it to work with 32khz > > adding 32khz support would require 1 extra config bit to select LP vs > HS oscillator, very similar to fuse options by Atmel flash MCUs. > > sure its additional engineering but.. MANY MANY MCU companies are > including this option, and it is working and doable. I cant imaging it > would not have been possible to test it without extra mask cost to > xilinx, by addint 2 test pins during say V-4 initial testing. how many > mask revisions was made? if the osc circuit would have been included > xilinx would have plenty of time (mask revisions) to fine tune it. and > in the case of failure those 2 magic pins would have "reserved" or GND > marking in final datasheet. > > simple. just a matter of decision. Antti, you are correct, but so also is Peter. Whilst this is common in the Microcontroller space, it is black magic to the FPGA guys. Also remember, they are working fabless, and are far more focused on MHz and mA, than on Osc details. They do not want, (or need) the hassle/delays, of talking with their Fab partners, and characterising an OSC block - that then may not work, or give poor Phase performance. -jgArticle: 124732
> Antti wrote: > >>Hi >> >>I know many wise men has said NO NO, but >> >>1) >>http://www.latticesemi.com/forums/forum/messageview.cfm?catid=42&threadid=3505 >> >>Lattice engineer suggest that it works (assumable reliable) on machXO >> >>the IO technology between machXO and Xilinx FPGAs isnt so big so I >>wonder why cant it be done with Xilinx ? >> >>for what I see is following >> >>25MHz crystal >>27p caps >>560 series >>1M parallel >> >>when using LVCMOS33 SLEW=FAST >> >>then there is some sort of overdrive, that makes oscillation to >>periodically stop and restart >>200 us work then 75 idle, then restarts again, the FPGA input sees >>however nice 25MHz >>from the crystal ALL time, (also when the output doesnt swing) >> >>by simply changing slew=slow the circuit does start work reliable. >> >>so any technical reasons why this circuit can not (should not) be >>used?? One litmus test for Xtal Osc circuits, is to remove the Xtal. If it stops oscillating that is a good sign! :) If it does not stop oscillating (above), what you actually have, is a crystal locked oscillator - and yes, you CAN make those (have made a few here ) but they are VERY sensistive to process/part changes. So you really have to have a good reason to go down that path. NXP show a LVC2GU04, for 9.7c, so why not just use one of those ? The 74AUP1Z04 includes a bias-resistor, and is more purpose built, for ~12.6c - it also gives faster output edges. [Only minus, is no injection current control] Or, I see 1GU04/1G14 are close to 3.9c now, so if you can tolerate two tiny packages, you can control the injection current on the 1GU04, and work over a very wide frequency range. -jgArticle: 124733
Why don't you download it from their website and try it out--it is free for 30 days. "Pszemol" <Pszemol@PolBox.com> wrote in message news:fds0sr.ats.0@poczta.onet.pl... > Have you tried it yet? How do you like it? > > Does it solve the horrible slow opening of Nios II components in SOPC > Builder?Article: 124734
Hi, I tried to interface a dynamic memory controller (dmc) inside an fpga with a sdram on the fpga board. The problem was that the dmc is 32bits wide (due to pin constraints) but the sdram is 64bits wide. So, to interface the 32 bits wide dmc with the 64 bits wide sdram, I have to use the cpu r/w address bit[2] to differentiate between lower half and higher half of the 64 bits interface. Just wondering whether there are better methods that I can use to interface 32 bits dmc with 64bits dram. thanks! btw, the translation mechanism between normal address and dram row/col addresses would be useful. From news@REMOVE_tlcs_THIS_dot_TO_fsnet_REPLY_dot_co.uk Tue Oct 02 07:39:42 2007 Path: newsdbm05.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!goblin1!goblin.stu.neva.ru!feeder1-2.proxad.net!proxad.net!feeder2-2.proxad.net!news.clara.net!wagner.news.clara.net!proxy01.news.clara.net From: "Tom Lucas" <news@REMOVE_tlcs_THIS_dot_TO_fsnet_REPLY_dot_co.uk> Newsgroups: comp.arch.embedded,comp.arch.fpga Subject: Basic VHDL Development kit Date: Tue, 2 Oct 2007 15:39:42 +0100 Lines: 6 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.3138 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.3138 X-RFC2646: Format=Flowed; Original X-Complaints-To: abuse@clara.net (please include full headers) X-Trace: 6f6506c26f980e0027665202116845845680f2310108784d20d06751470257c5 NNTP-Posting-Date: Tue, 02 Oct 2007 15:37:57 +0100 Message-Id: <1191335877.22751.0@proxy01.news.clara.net> Xref: prodigy.net comp.arch.embedded:260356 comp.arch.fpga:136693 Does anybody have any suggestions for a cheap and basic development kit to practice VHDL on? It doesn't need to do much more than toggle a few output pins and I'm happy to make up my own programming leads etc. UK based distributors would be preferred.Article: 124735
"Tom Lucas" <news@REMOVE_tlcs_THIS_dot_TO_fsnet_REPLY_dot_co.uk> wrote in message news:1191335877.22751.0@proxy01.news.clara.net... > Does anybody have any suggestions for a cheap and basic development kit to > practice VHDL on? It doesn't need to do much more than toggle a few output > pins and I'm happy to make up my own programming leads etc. UK based > distributors would be preferred. Maybe something here? :o) http://search.ebay.co.uk/search/search.dll?from=R40&_trksid=m37&satitle=xilinx -- Regards, Richard. + http://www.FreeRTOS.org 13 official architecture ports, 1000 downloads per week. + http://www.SafeRTOS.com Certified by TÜV as meeting the requirements for safety related systems. From news@REMOVE_tlcs_THIS_dot_TO_fsnet_REPLY_dot_co.uk Tue Oct 02 08:35:58 2007 Path: newsdbm05.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!goblin1!goblin.stu.neva.ru!feeder1-2.proxad.net!proxad.net!feeder2-2.proxad.net!news.clara.net!wagner.news.clara.net!proxy01.news.clara.net From: "Tom Lucas" <news@REMOVE_tlcs_THIS_dot_TO_fsnet_REPLY_dot_co.uk> Newsgroups: comp.arch.embedded,comp.arch.fpga References: <1191335877.22751.0@proxy01.news.clara.net> <HZsMi.24379$c_1.18057@text.news.blueyonder.co.uk> Subject: Re: Basic VHDL Development kit Date: Tue, 2 Oct 2007 16:35:58 +0100 Lines: 24 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.3138 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.3138 X-RFC2646: Format=Flowed; Response X-Complaints-To: abuse@clara.net (please include full headers) X-Trace: 60617508c02014ad1f401543f060706096bf655422560c4a1660718b470264f5 NNTP-Posting-Date: Tue, 02 Oct 2007 16:34:13 +0100 Message-Id: <1191339253.28703.0@proxy01.news.clara.net> Xref: prodigy.net comp.arch.embedded:260361 comp.arch.fpga:136695 "FreeRTOS.org" <noemal@address.com> wrote in message news:HZsMi.24379$c_1.18057@text.news.blueyonder.co.uk... > "Tom Lucas" <news@REMOVE_tlcs_THIS_dot_TO_fsnet_REPLY_dot_co.uk> wrote > in message news:1191335877.22751.0@proxy01.news.clara.net... >> Does anybody have any suggestions for a cheap and basic development >> kit to practice VHDL on? It doesn't need to do much more than toggle >> a few output pins and I'm happy to make up my own programming leads >> etc. UK based distributors would be preferred. > > > Maybe something here? :o) > > http://search.ebay.co.uk/search/search.dll?from=R40&_trksid=m37&satitle=xilinx > You'd have thought there would have been something but it all seems thin on the ground. I managed to dig out an old lattice development kit at work but someone's had the board away and just left the books. Cypress do cheapish CPLD dev kits so perhaps that might be a better road to follow - VHDL is the same on CPLDs and FPGAs, right? I might even have a copy or Warp somewhere around.Article: 124736
Have a look at our range http://www.enterpoint.co.uk/boardproducts.html. We may have some old rev Raggedstone1s coming onto Ebay in the next few days with either a small or no reserve. We found some in a box that didn't get sold. John Adair Enterpoint Ltd. On 2 Oct, 15:39, "Tom Lucas" <news@REMOVE_tlcs_THIS_dot_TO_fsnet_REPLY_dot_co.uk> wrote: > Does anybody have any suggestions for a cheap and basic development kit > to practice VHDL on? It doesn't need to do much more than toggle a few > output pins and I'm happy to make up my own programming leads etc. UK > based distributors would be preferred.Article: 124737
Tom Lucas wrote:
> Does anybody have any suggestions for a cheap and basic development kit
> to practice VHDL on? It doesn't need to do much more than toggle a few
> output pins and I'm happy to make up my own programming leads etc. UK
> based distributors would be preferred.
If the objective is to learn vhdl, all you need is
1. A simulator to verify and debug
the uut and testbench code and
2. Quartus or ise to view the rtl schematic.
If the objective is to toggle a few output pins,
then buy a board and run the demos.
-- Mike Treseler
Article: 124738Mike Treseler wrote: > 1. A simulator to verify and debug > the uut and testbench code and I've recently been learning VHDL myself and have found GHDL to be quite useful and *free* with-out all that dreadful IDE stuff. Combined with gtkwave under Linux, it is a nice little system. ymmv. <http://ghdl.free.fr/> -- Michael N. Moran (h) 770 516 7918 5009 Old Field Ct. (c) 678 521 5460 Kennesaw, GA, USA 30144 http://mnmoran.org "So often times it happens, that we live our lives in chains and we never even know we have the key." "Already Gone" by Jack Tempchin (recorded by The Eagles) The Beatles were wrong: 1 & 1 & 1 is 1Article: 124739
On 2 Oct, 19:09, "Michael N. Moran" <mnmo...@bellsouth.net> wrote: > Mike Treseler wrote: > > 1. A simulator to verify and debug > > the uut and testbench code and > > I've recently been learning VHDL myself and have > found GHDL to be quite useful and *free* with-out > all that dreadful IDE stuff. Combined with gtkwave > under Linux, it is a nice little system. ymmv. > > <http://ghdl.free.fr/> > > -- > Michael N. Moran (h) 770 516 7918 > 5009 Old Field Ct. (c) 678 521 5460 > Kennesaw, GA, USA 30144 http://mnmoran.org > > "So often times it happens, that we live our lives in chains > and we never even know we have the key." > "Already Gone" by Jack Tempchin (recorded by The Eagles) > > The Beatles were wrong: 1 & 1 & 1 is 1 Try this out for really cheap boards for beginners - http://www.knjn.com/ also try this for some "fun projects" - http://www.fpga4fun.com/Article: 124740
probably the problem is in the offset address. my system has
addresses:
Address Map for Processor ppc405_0
(0b0000010000-0b0000010011) ppc405_0
(0b0000100000-0b0000100011) ppc405_0
(0000000000-0x00003fff) plb_bram_if_cntlr_1 plb
(0x80000000-0x80007fff) docm_cntlr docm
(0xffff8000-0xffffffff) iocm_cntlr iocm
Address map generated successfully.
When i am loading data in the DSOCM_ BRAM from PORT B i am giving it
like:
In VHDL --> dsocm_bram_BRAM_EN_B_pin <= '1';
dsocm_bram_BRAM_WEN_B_pin <= ("1111");
dsocm_bram_BRAM_Addr_B_pin <= (X"00000010");
-- memory location
dsocm_bram_BRAM_Dout_B_pin <= (X"00000444");
-- 32bits data
In Inline Assembly--> asm(" lis 5,0x80000010@ha");
asm(" lwz 5,0x80000010@l(5)");
So if i am right the offset of the DSOCM is 0x8000000F(offset) and
the address location i am wirting in the Bram is ( 0x00000010) then i
have to read (from the inline assembly code) from location 0x8000000F
- 0x00000010 = 0x7FFFFFFF
i.e asm(" lis 5,0x7FFFFFFF @ha");
asm(" lwz 5,0x7FFFFFFF@l(5)");
where i am doing wrong on that?
Regards and really thanx :)
xenix
Article: 124741Jon Elson wrote: (snip) >> to generate color NTSC output, so far my results show less quality > Cool! For color, you would want your main clock to be some multiple of > the color subcarrier frequency. In the US (NTSC) that is 3.57954525 > MHz, so a good frequency might be 128 times that, or 458.1819 MHz. > You have to generate the color subcarrier, whose amplitude is > proportional to color saturation, and whose phase (relative to the > reference burst at the beginning of each line) gives the angle around > the hue wheel. This is mixed with the luminance signal. A portion of > the luminance bandwidth is chopped out and sent to the color decoder. In the olden days (Apple II, IBM CGA) it was done with on/off switching at four times the subcarrier frequency. That gives you 16 combinations of phase and amplitude to choose from, which was good enough in those days. If you allow for 128 times the subcarrier and allow for all on/off combinations (that is, allow 128 bits per subcarrier cycle) you should get a good number of hue/saturation/intensity combinations. -- glenArticle: 124742
On 28 Sep., 08:42, Tommy Thorn <tommy.th...@gmail.com> wrote: > > TYPE array_type is ARRAY (1 to 6) of std_ulogic_vector(7 downto 0); > > signal my_array : array_type; > > attribute syn_ramstyle of my_array is register; > > ... > > process (clk, rst) > > variable cnt: integer range 0 to 7; > > if rst='0' then > > my_array <= (others => (others =>'0')); > > D'oh. No SRAM can be reset in one cycle. I expect so, but Synplify infers RAM out of this process. So the tools seems to know a RAM with asynch reset. The syn_ramstyle pragmas are mainly used, because I like to have registers used. bye ThomasArticle: 124743
On 28 Sep., 23:24, Andy <jonesa...@comcast.net> wrote: > I've also seen Synplify put a feedback mux around a ram that did not > have a reset, but was inferred from a process that did have an async > reset (due to the 'elsif rising_edge()' not executing during reset). > I wonder if that could be related to what's going on? Without code, it > is really hard to tell. Seems to be realted to me. Could you say, which technology you used to have synplicity infering a ram out of a process with asynch reset? bye ThomasArticle: 124744
On 2 Pa , 18:54, Mike Treseler <mike_trese...@comcast.net> wrote: > Tom Lucas wrote: > > Does anybody have any suggestions for a cheap and basic development kit > > to practice VHDL on? It doesn't need to do much more than toggle a few > > output pins and I'm happy to make up my own programming leads etc. UK > > based distributors would be preferred. > > If the objective is to learn vhdl, all you need is > > 1. A simulator to verify and debug > the uut and testbench code and Good solution is a Aldec Active-HDL 7.2 SE (student edition). Very good simulation and verification tool. Nice schematic diagrams, easy waveform manipulation. Very good choice (personal opinion) for learning. Moreover, for this purposes it is free :)Article: 124745
On Oct 1, 4:58 pm, Narsi <pna...@gmail.com> wrote: > Hi, > > Is there any body uses the Large FPGA to build test and > measurements equipments. > If you use it, how big is the idle FPGA for you. > > thanks > Narsi I am sorry, I meant IDEAL FPGA size in terms of densityArticle: 124746
Narsi wrote:
> I am sorry, I meant IDEAL FPGA size in terms of density
I never know until the HDL is written
and working in simulation.
At that point, I can test the fit
for any device I prefer.
-- Mike Treseler
Article: 124747Narsi wrote: > Hi, > > Is there any body uses the Large FPGA to build test and > measurements equipments. > If you use it, how big is the idle FPGA for you. I know Device programmers that used FPGAs ( smaller/older ones, on today's scales ) - these are mostly smart IO, and higher Voltage IO compliance matters. I also know of oscilloscopes using FPGAs, - there they push things more, and need more logic, and less IO. Generic design is ADC + Memory + FPGA (+ some SW..) -jgArticle: 124748
On Oct 2, 8:52 pm, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > Narsi wrote: > > Hi, > > > Is there any body uses the Large FPGA to build test and > > measurements equipments. > > If you use it, how big is the idle FPGA for you. > > I know Device programmers that used FPGAs > ( smaller/older ones, on today's scales ) - these are > mostly smart IO, and higher Voltage IO compliance matters. > > I also know of oscilloscopes using FPGAs, - there they > push things more, and need more logic, and less IO. > Generic design is ADC + Memory + FPGA (+ some SW..) > > -jg You may want to check out Catalyst enterprises http://www.getcatalyst.com/ They make a number of bus analyzers using FPGA's. In fact they tout the uploadable FPGA as a feature in the datasheets. In my experience the long start-up times due to configuration over a slow interface can be a drag. On the other hand I'm guessing their newer products have faster programming interfaces than the old serial stull I used in the past. Cheers, GaborArticle: 124749
"Tom Lucas" <news@REMOVE_tlcs_THIS_dot_TO_fsnet_REPLY_dot_co.uk> wrote in message news:1191335877.22751.0@proxy01.news.clara.net... > Does anybody have any suggestions for a cheap and basic development kit to > practice VHDL on? It doesn't need to do much more than toggle a few output > pins and I'm happy to make up my own programming leads etc. UK based > distributors would be preferred. > http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=250169954376 No affiliation by the way. Red From news@REMOVE_tlcs_THIS_dot_TO_fsnet_REPLY_dot_co.uk Wed Oct 03 01:48:27 2007 Path: newsdbm05.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!goblin1!goblin.stu.neva.ru!feeder1-2.proxad.net!proxad.net!feeder2-2.proxad.net!news.clara.net!wagner.news.clara.net!despina.uk.clara.net From: "Tom Lucas" <news@REMOVE_tlcs_THIS_dot_TO_fsnet_REPLY_dot_co.uk> Newsgroups: comp.arch.embedded,comp.arch.fpga References: <1191335877.22751.0@proxy01.news.clara.net> <1191340502.789799.236030@w3g2000hsg.googlegroups.com> Subject: Re: Basic VHDL Development kit Date: Wed, 3 Oct 2007 09:48:27 +0100 Lines: 25 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.3138 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.3138 X-RFC2646: Format=Flowed; Original X-Complaints-To: abuse@clara.net (please include full headers) X-Trace: f5d26a00f5940ba81204c423777621411d66745756c064e066561584470356f2 NNTP-Posting-Date: Wed, 03 Oct 2007 09:46:42 +0100 Message-Id: <1191401202.28759.0@despina.uk.clara.net> Xref: prodigy.net comp.arch.embedded:260402 comp.arch.fpga:136711 "John Adair" <g1@enterpoint.co.uk> wrote in message news:1191340502.789799.236030@w3g2000hsg.googlegroups.com... > Have a look at our range > http://www.enterpoint.co.uk/boardproducts.html. > We may have some old rev Raggedstone1s coming onto Ebay in the next > few days with either a small or no reserve. We found some in a box > that didn't get sold. > > John Adair > Enterpoint Ltd. I'll keep an eye out for those then. > On 2 Oct, 15:39, "Tom Lucas" > <news@REMOVE_tlcs_THIS_dot_TO_fsnet_REPLY_dot_co.uk> wrote: >> Does anybody have any suggestions for a cheap and basic development >> kit >> to practice VHDL on? It doesn't need to do much more than toggle a >> few >> output pins and I'm happy to make up my own programming leads etc. UK >> based distributors would be preferred. > > From news@REMOVE_tlcs_THIS_dot_TO_fsnet_REPLY_dot_co.uk Wed Oct 03 01:54:08 2007 Path: newsdbm05.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newshub.sdsu.edu!feeder1-2.proxad.net!proxad.net!feeder2-2.proxad.net!news.clara.net!wagner.news.clara.net!despina.uk.clara.net From: "Tom Lucas" <news@REMOVE_tlcs_THIS_dot_TO_fsnet_REPLY_dot_co.uk> Newsgroups: comp.arch.embedded,comp.arch.fpga References: <1191335877.22751.0@proxy01.news.clara.net> <5mfbenFd8h6cU1@mid.individual.net> <BPvMi.24$i7.14@bignews2.bellsouth.net> <1191349922.467508.71410@d55g2000hsg.googlegroups.com> Subject: Re: Basic VHDL Development kit Date: Wed, 3 Oct 2007 09:54:08 +0100 Lines: 40 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.3138 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.3138 X-RFC2646: Format=Flowed; Original X-Complaints-To: abuse@clara.net (please include full headers) X-Trace: 12686001051480c09c71b0106710a84f2fd6c662565c87981650604447035847 NNTP-Posting-Date: Wed, 03 Oct 2007 09:52:23 +0100 Message-Id: <1191401543.28797.0@despina.uk.clara.net> Xref: prodigy.net comp.arch.embedded:260405 comp.arch.fpga:136712 "ratemonotonic" <niladri1979@gmail.com> wrote in message news:1191349922.467508.71410@d55g2000hsg.googlegroups.com... > On 2 Oct, 19:09, "Michael N. Moran" <mnmo...@bellsouth.net> wrote: >> Mike Treseler wrote: >> > 1. A simulator to verify and debug >> > the uut and testbench code and >> >> I've recently been learning VHDL myself and have >> found GHDL to be quite useful and *free* with-out >> all that dreadful IDE stuff. Combined with gtkwave >> under Linux, it is a nice little system. ymmv. >> >> <http://ghdl.free.fr/> >> >> -- >> Michael N. Moran (h) 770 516 7918 >> 5009 Old Field Ct. (c) 678 521 5460 >> Kennesaw, GA, USA 30144 http://mnmoran.org >> >> "So often times it happens, that we live our lives in chains >> and we never even know we have the key." >> "Already Gone" by Jack Tempchin (recorded by The Eagles) >> >> The Beatles were wrong: 1 & 1 & 1 is 1 > > Try this out for really cheap boards for beginners - > > http://www.knjn.com/ The Pluto 3 looks like just the thing. Are they available from a UK supplier or do I need to look at getting one imported? > also try this for some "fun projects" - > > http://www.fpga4fun.com/ > > >
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