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Hi, I am a Grad student. I intend to do a project examining the aspects surrounding interconnections between FPGAs. I figure that this group might have professionals working in this area - so it would be a good place to ask. I am looking for the following information: Companies that Manufacture Multi-FPGA Hardware: Here, I am looking for company manufacturing Multi-FPGA boards or even emulation machines. I figure that from this I would be able to find out details regarding the architecture that they are using. I have not had much luck in trying to find such companies - but I still feel I might be missing the obvious ones. Here is what I found. I hope you could add to the list if you happen to know some more: 1. Pro Design Chipit - http://www.uchipit.com/ce/index.htm: These folks seem like they have a lot of products. But now I am looking for their competitors. 2. Simpod: http://www.simpod.com/: I have not taken a good look at this company 3. The Dini Group: http://www.dinigroup.com/ Sounds like they do have some products. Thanks a lot. O.O.Article: 124776
Hello Arnim,
> > I try to use Xilinx' tools without GUI. I can't find method to config
> > "Generate Programming File" bitgen tool in tcl shell.
>
> I'm not 100% sure what you're looking for, but you can set/configure the
> "Generate Programming File" (and others) with TCL commands like the
> following ones:
>
> project set {Signature /User Code} {0831} -process {Generate Programming
> File}
> project set {Create Binary Configuration File} 1 -process {Generate
> Programming File}
> project set {Done (Output Events)} 5 -process {Generate Programming File}
Thank you.
It's exactly what I've looked for.
It works.
I've checked now that "project properties" lists all configuration
options.
I have no idea I couldn't find it yesterday.
Greetings,
Jerzy Gbur
Article: 124777[posted to comp.arch.fpga + comp.lang.vhdl] Hi All I've had a quote from a 3rd party to develop a floating point FFT core for us (1Mpt). Probably for a Xilinx Virtex5 SXT. Obviously I'd like to get some more quotes, but would like to know if you have any recommendations? Thanks.Article: 124778
Hi You may find this link helps http://www.fpga-faq.com/FPGA_Boards.shtml JonArticle: 124779
Try www.sundance.com big modularity - you can build the topology you want in just a few steps ... "O. Olson" <olson_ord@yahoo.it> a écrit dans le message de news:1191471360.422373.39180@d55g2000hsg.googlegroups.com... > Hi, > > I am a Grad student. I intend to do a project examining the aspects > surrounding interconnections between FPGAs. I figure that this group > might have professionals working in this area - so it would be a good > place to ask. > > I am looking for the following information: > Companies that Manufacture Multi-FPGA Hardware: > Here, I am looking for company manufacturing Multi-FPGA boards or > even emulation machines. I figure that from this I would be able to > find out details regarding the architecture that they are using. > I have not had much luck in trying to find such companies - but I > still feel I might be missing the obvious ones. Here is what I found. > I hope you could add to the list if you happen to know some more: > > 1. Pro Design Chipit - http://www.uchipit.com/ce/index.htm: These > folks seem like they have a lot of products. But now I am looking for > their competitors. > > 2. Simpod: http://www.simpod.com/: I have not taken a good look at > this company > > 3. The Dini Group: http://www.dinigroup.com/ Sounds like they do have > some products. > > Thanks a lot. > O.O. >Article: 124780
On 4 Okt., 06:16, "O. Olson" <olson_...@yahoo.it> wrote: > I am looking for the following information: > Companies that Manufacture Multi-FPGA Hardware: - Sony had high end studio mixer with something like 400 XC4K in them. - Many applications that required arrays of FPGAs now are often done in one big FPGA. You can easily find older products that emplay arrays of FPGAs if you search for products doing: - Logic Emulation, also including Fault Emulation (ATPG) - DNA pattern matching Are you aware of this line of research? http://portal.acm.org/citation.cfm?id=567060 Have fun, Kolja From news@REMOVE_tlcs_THIS_dot_TO_fsnet_REPLY_dot_co.uk Thu Oct 04 01:48:08 2007 Path: newsdbm05.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!goblin1!goblin.stu.neva.ru!feeder1-2.proxad.net!proxad.net!feeder2-2.proxad.net!news.clara.net!wagner.news.clara.net!despina.uk.clara.net From: "Tom Lucas" <news@REMOVE_tlcs_THIS_dot_TO_fsnet_REPLY_dot_co.uk> Newsgroups: comp.arch.embedded,comp.arch.fpga References: <1191335877.22751.0@proxy01.news.clara.net> <5mfbenFd8h6cU1@mid.individual.net> <1191420648.836140.188050@g4g2000hsf.googlegroups.com> <1191422537.39588.0@despina.uk.clara.net> <1191434195.876205.222290@w3g2000hsg.googlegroups.com> <4dRMi.296052$BX3.157770@newsfe13.lga> <1191445567.264534.197790@19g2000hsx.googlegroups.com> Subject: Re: Basic VHDL Development kit Date: Thu, 4 Oct 2007 09:48:08 +0100 Lines: 33 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.3138 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.3138 X-RFC2646: Format=Flowed; Original X-Complaints-To: abuse@clara.net (please include full headers) X-Trace: 171030306f805c4266602d80665022994060607c20f157c2168450904704a85e NNTP-Posting-Date: Thu, 04 Oct 2007 09:46:22 +0100 Message-Id: <1191487582.74594.0@despina.uk.clara.net> Xref: prodigy.net comp.arch.embedded:260446 comp.arch.fpga:136746 <cs_posting@hotmail.com> wrote in message news:1191445567.264534.197790@19g2000hsx.googlegroups.com... > On Oct 3, 2:25 pm, Ray Andraka <r...@andraka.com> wrote: >> cs_post...@hotmail.com wrote: >> > You can control your degree of vendor lock in fairly easy - if you >> > don't use their unique library functions, and use only the free >> > download versions of the tools, and don't utilize any abuses of the >> > language that one tool or the other might permit, then you should >> > remain portable. >> >> ...and far less efficient than you could be if you designed to the >> architecture. Now that doesn't necessarily mean instantiating >> primitives, but it does play into how you architect your design so >> that >> it makes best use of the target FPGA structure. Not doing this may >> lead >> to a design that is far larger and slower than one that is >> specifically >> designed to the architecture. > > I thought we were talking about exploration and initial learning, not > making products. Well my eventual goal is to implement FPGA in my production systems so it probably makes sense to keep that in mind as I begin my first forays. My philosophy with the C I've written for the system is to keep it all as portable as possible and perhaps have lost efficiency in doing so but the products are low-volume and the cost of a bigger/faster part is far less than the cost of rewriting platform specific code. I think I will carry on that methodology with FPGAs and then look toward performance gains with platform specific optimisations if my hands get really tied.Article: 124781
Nial Stewart wrote: (snip) > Antti, you'll only be able to generate a black and white signal > with this technique. > For colour you need to generate a reference colour burst at the start > of each frame, then output a sinusoid whose relative frequency to this > reference burst indicated the colour. You do need the burst, but you don't need sinusoids. Square waves (they will be filtered soon enough) work pretty close, too. If you clock is a multiple of the color subcarrier frequency those gray dots have components (consider an FFT) at the appropriate frequency and phase. > This is superimposed on the luminance signal to provide a composite > output. > With just the resistors all you'll get is levels of grey. -- glenArticle: 124782
Hi, I am currently working on a circuit which has to perform Hamming distance computation between large bit vectors (>500 bits). I was surprised not to find much information on how to implement this type of operation *efficiently* on FPGA technology. So far I have been investigating two approaches (combining tables and counter for the bitcouting part). I observed that the choice of table size (3 or 4 address bits) had a significant impact (20%) on the area cost of the operator. I feel that there are many subtle trade-offs in such implementations, and I was wondering if anybody had been looking at this problem (most of the articles I stumbled accross dealt with the correcting code issue, rather than focusing on the Hamming distance realization in itself). Thanks in advances for the input. Regards, StevenArticle: 124783
Hi All, We are an enthusiasts who are written hardware JPEG-LS IP core. Visit project site http://www.jpegls.com. It's working in the simulator and we are sure about it. Although sufficient effort should be applied to public this project and prove its rights to life :) In case if we decide to do it the big amount of work appears in front of us: we have to write full documentation, assemble set of demo testbenches, fit and verify core with many FPGA chips and make some software utilities. Therefore I would hear some opinions from the community about such type of projects: is it really interest for somebody or it will be simple junk efforts. What do you think about practical usage hardwared compression? Who can be interested in it? We haven't careful thought about licensing terms yet, but I expect it will be free core in any way. There are some reasons to don't open sources so we can't apply GNU but GPL looks quite well. P.S. I know about opencores.org and I've had done two projects there, so I'll probably place jpeg-ls coder too. Digitally yours, Michael http://www.jpegls.comArticle: 124784
"O. Olson" <olson_...@yahoo.it> wrote: > Hi, > > I am a Grad student. I intend to do a project examining the aspects > surrounding interconnections between FPGAs. I figure that this group > might have professionals working in this area - so it would be a good > place to ask. > > I am looking for the following information: > Companies that Manufacture Multi-FPGA Hardware: > Here, I am looking for company manufacturing Multi-FPGA boards or > even emulation machines. I figure that from this I would be able to > find out details regarding the architecture that they are using. > I have not had much luck in trying to find such companies - but I > still feel I might be missing the obvious ones. Here is what I found. > I hope you could add to the list if you happen to know some more: > > 1. Pro Design Chipit -http://www.uchipit.com/ce/index.htm:These > folks seem like they have a lot of products. But now I am looking for > their competitors. > > 2. Simpod:http://www.simpod.com/:I have not taken a good look at > this company > > 3. The Dini Group:http://www.dinigroup.com/Sounds like they do have > some products. > > Thanks a lot. > O.O. http://setdsp.com/root/products/instrumental/pci/setmatrixs2/ I figure there are enough - 24 Spartan FPGAs. Although I should say based on my own expirience that one big FPGA always better than bunch of small ones. Interfacing between chips, especially high-speed interfacing, is a quite odd task.Article: 124785
On 4 okt, 13:07, cms <Michael.Tsvet...@gmail.com> wrote: > Digitally yours, > Michael > > http://www.jpegls.com Link doesn't work ? Regards, BartArticle: 124786
On 4 , 15:24, zeeman_be <zeema...@gmail.com> wrote: > On 4 okt, 13:07, cms <Michael.Tsvet...@gmail.com> wrote: > > > Digitally yours, > > Michael > > >http://www.jpegls.com > > Link doesn't work ? > > Regards, > Bart No, it works now. Periodically somebody ddos-attacked hosting and site goes down. But I hope it's temporary problem.Article: 124787
Hi, thank you for your tip. But i don't know how tu use the instruction set. I suppose i should write some assemble Code, but how and what are the commands?? Is there a datasheet or example on internet? I am working with EDK 9 and SDK. Thanks for the help On 2 Okt., 11:33, G=F6ran Bilski <goran.bil...@xilinx.com> wrote: > Hi, > > It's better to add the HW module to FSL instead to the bus. > > There is currently no CLZ instruction for MicroBlaze. > You can however do an optimized software implementation by using the pcmb= f instruction. > The instruction will compare a register with another register byte-wise a= nd you will get the number of bytes that matches from left to right. > So if you have the value you want to do a CLZ in a register, you can do a= pcmbf against register 0 which always is 0. > You will know in which byte the first leading '1' is located and can afte= r that do 8 bit search inside that byte. > > It will not be done in one clock cycle but is most likely much faster tha= n do a 32-bit search for the first '1'. > > G=F6ran Bilski > > From MicroBlaze reference guide: > > pcmpbf Pattern Compare Byte Find > Description > The contents of register rA is bytewise compared with the contents in reg= ister rB. > =B7 rD is loaded with the position of the first matching byte pair, start= ing with MSB as position 1, and comparing until LSB as position 4 > =B7 If none of the byte pairs match, rD is set to 0 > Pseudocode > if rB[0:7] =3D rA[0:7] then > (rD) 1 > else > if rB[8:15] =3D rA[8:15] then > (rD) 2 > else > if rB[16:23] =3D rA[16:23] then > (rD) 3 > else > if rB[24:31] =3D rA[24:31] then > (rD) 4 > else > (rD) 0 > > > > <armando...@googlemail.com> wrote in messagenews:1191316036.966644.326500= @50g2000hsm.googlegroups.com... > > Hi, > > > thanks for the answers. > > I know it should not be difficult to implement the module in Hardware > > (or SW). > > But i would like to calculate the operation as quick as possible. > > > In the case of Hardware, i should attach the module to the processor > > of my system using a bus, and thus with a few more extra cycles. > > > I just would like to be sure that the Microblaze Prozessor does not > > have such an instruction and know if some of you have already had > > experiences with CLZ in a EDK system. > > > Thx again- Zitierten Text ausblenden - > > - Zitierten Text anzeigen -Article: 124788
Hi, Here is the link to the MicroBlaze reference guide. http://www.xilinx.com/ise/embedded/mb_ref_guide.pdf If you have EDK, you will find the documentations under /doc in your install. For how to program MicroBlaze, you will need to read about the software tools. But I would suggest doing a tutorial first to get a feeling on how things are done. Göran Bilski "Anacrom" <armandolou@googlemail.com> wrote in message news:1191499714.812910.21380@g4g2000hsf.googlegroups.com... Hi, thank you for your tip. But i don't know how tu use the instruction set. I suppose i should write some assemble Code, but how and what are the commands?? Is there a datasheet or example on internet? I am working with EDK 9 and SDK. Thanks for the help On 2 Okt., 11:33, Göran Bilski <goran.bil...@xilinx.com> wrote: > Hi, > > It's better to add the HW module to FSL instead to the bus. > > There is currently no CLZ instruction for MicroBlaze. > You can however do an optimized software implementation by using the pcmbf > instruction. > The instruction will compare a register with another register byte-wise > and you will get the number of bytes that matches from left to right. > So if you have the value you want to do a CLZ in a register, you can do a > pcmbf against register 0 which always is 0. > You will know in which byte the first leading '1' is located and can after > that do 8 bit search inside that byte. > > It will not be done in one clock cycle but is most likely much faster than > do a 32-bit search for the first '1'. > > Göran Bilski > > From MicroBlaze reference guide: > > pcmpbf Pattern Compare Byte Find > Description > The contents of register rA is bytewise compared with the contents in > register rB. > ˇ rD is loaded with the position of the first matching byte pair, starting > with MSB as position 1, and comparing until LSB as position 4 > ˇ If none of the byte pairs match, rD is set to 0 > Pseudocode > if rB[0:7] = rA[0:7] then > (rD) 1 > else > if rB[8:15] = rA[8:15] then > (rD) 2 > else > if rB[16:23] = rA[16:23] then > (rD) 3 > else > if rB[24:31] = rA[24:31] then > (rD) 4 > else > (rD) 0 > > > > <armando...@googlemail.com> wrote in > messagenews:1191316036.966644.326500@50g2000hsm.googlegroups.com... > > Hi, > > > thanks for the answers. > > I know it should not be difficult to implement the module in Hardware > > (or SW). > > But i would like to calculate the operation as quick as possible. > > > In the case of Hardware, i should attach the module to the processor > > of my system using a bus, and thus with a few more extra cycles. > > > I just would like to be sure that the Microblaze Prozessor does not > > have such an instruction and know if some of you have already had > > experiences with CLZ in a EDK system. > > > Thx again- Zitierten Text ausblenden - > > - Zitierten Text anzeigen -Article: 124789
Hello, I'm working with a new xup rev. 04 board: Whenever I connect the integrated USB Platform cable I only get USB full speed (1.1) although I need the faster USB 2.0 connection. I tried 4 different machines, 3 different operating systems (VIsta, WinXP SP2, Ubuntu) even switched the USB A-B cable -- various combinations tried. The XUP board connects with 1.1, while in each and every case my Spartan 3E starter kit connects with USB 2.0. The vendor ids: Spartan3E : ID 03fd:000d Xilinx, Inc. xup-v2p: ID 03fd:0009 Xilinx, Inc. I could post the usb endpoint configuration as reported by linux, but I cross checked with the Cypress EZ USB datasheet, and the USB 1.1 configuration for the xup looked like the one in the Cypress datasheet, when cypress decides it must do usb 1.1. Any ideas how to proceed? j.Article: 124790
"cms" <Michael.Tsvetkov@gmail.com> wrote in message news:1191497591.671967.88400@y42g2000hsy.googlegroups.com... > > No, it works now. Periodically somebody ddos-attacked hosting and site > goes down. But I hope it's temporary problem. I've tried about 20 times over the last 24 hours (since you first posted on comp.compression). No luck.Article: 124791
joerg@zilium.de wrote:
> Hello,
>
> I'm working with a new xup rev. 04 board: Whenever I connect the
> integrated USB Platform cable I only get USB full speed (1.1) although
> I need the faster USB 2.0 connection.
>
> I tried 4 different machines, 3 different operating systems (VIsta,
> WinXP SP2, Ubuntu) even switched the USB A-B cable -- various
> combinations tried. The XUP board connects with 1.1, while in
> each and every case my Spartan 3E starter kit connects with USB 2.0.
>
> The vendor ids:
>
> Spartan3E : ID 03fd:000d Xilinx, Inc.
> xup-v2p: ID 03fd:0009 Xilinx, Inc.
>
>
> I could post the usb endpoint configuration as reported by linux, but
> I
> cross checked with the Cypress EZ USB datasheet, and the USB
> 1.1 configuration for the xup looked like the one in the Cypress
> datasheet,
> when cypress decides it must do usb 1.1.
>
> Any ideas how to proceed?
>
>
> j.
If you think you're only running at Full Speed because of the warning
from Windows that says something like
"This hardware is not performing at optimum speed.
Try using a high-speed USB port."
then you probably DON'T have a problem. The USB programmer has problems
being recognized properly. I have no idea why this problem still
lingers after all these years but I certainly hate seeing it. It took
me days before I was comfortable that it was actually running at the
higher rate.
Silly stuff.
Article: 124792Check-out the BEE2. ---Matthew Hicks > Hi, > > I am a Grad student. I intend to do a project examining the aspects > surrounding interconnections between FPGAs. I figure that this group > might have professionals working in this area - so it would be a good > place to ask. > > I am looking for the following information: > Companies that Manufacture Multi-FPGA Hardware: > Here, I am looking for company manufacturing Multi-FPGA boards or > even emulation machines. I figure that from this I would be able to > find out details regarding the architecture that they are using. > I have not had much luck in trying to find such companies - but I > still feel I might be missing the obvious ones. Here is what I found. > I hope you could add to the list if you happen to know some more: > > 1. Pro Design Chipit - http://www.uchipit.com/ce/index.htm: These > folks seem like they have a lot of products. But now I am looking for > their competitors. > > 2. Simpod: http://www.simpod.com/: I have not taken a good look at > this company > > 3. The Dini Group: http://www.dinigroup.com/ Sounds like they do have > some products. > > Thanks a lot. > O.O.Article: 124793
Grumps wrote: > [posted to comp.arch.fpga + comp.lang.vhdl] > Hi All > I've had a quote from a 3rd party to develop a floating point FFT core for > us (1Mpt). Probably for a Xilinx Virtex5 SXT. > Obviously I'd like to get some more quotes, but would like to know if you > have any recommendations? Dillon Engineering has a fact sheet about a floating point core on their web site: http://www.dilloneng.com/documents/fpfft_fact.pdf Maybe that would give you an alternative to your quote? Cheers, GuenterArticle: 124794
On Oct 2, 4:37 pm, Thomas Stanka <usenet_nospam_va...@stanka-web.de> wrote: > On 28 Sep., 23:24, Andy <jonesa...@comcast.net> wrote: > > > I've also seen Synplify put a feedback mux around a ram that did not > > have a reset, but was inferred from a process that did have an async > > reset (due to the 'elsif rising_edge()' not executing during reset). > > I wonder if that could be related to what's going on? Without code, it > > is really hard to tell. > > Seems to be realted to me. Could you say, which technology you used > to have synplicity infering a ram out of a process with asynch reset? > > bye Thomas Xilinx. The process had an asynchronous reset, but the ram array was not reset: process (rst, clk) is begin if rst = '1' then reg <= '0'; elsif rising_edge(clk) then reg <= something; ram(addr) <= something_else; end if; end process; If reset is asserted, the rising_edge() condition is not evaluated or run for any of the other assignments. So even though ram() is not reset, it is not updated on clock cycles when reset is asserted either. A better way to code it is: process (rst, clk) is begin if rising_edge(clk) then reg <= something; ram(addr) <= something_else; end if; if rst = '1' then reg <= '0'; end if; end process; AndyArticle: 124795
I have a design that was built with XPS 8.2.03. I want to lock down everything in the design except one custom OPB peripheral I created. I want other users to be able to modify that peripheral (from user_logic.vhd down) and recompile the design with only the ISE software. If I use "export to ISE" are they still able to modify user_logic.vhd and below? Do they still need an XPS install to build? Does ISE allow them to initialize the BRAMs with my bootloader .elf? Maybe somebody in this group has already done this? I want users to be able to implement some custom hardware on my product but I don't want them messing with the CPU and other peripherals and I'm trying to avoid the expense of forcing them to buy XPS since they don't really need it. Thanks, ClarkArticle: 124796
Hi,
Everyone. I am debugging an image capture board. In this board, the
ADV7181B is used to digitalize one channel analog TV signal and the analog
video signal is AC-coupled to ADV7181B input pin AIN6, while other analog
input pins (AIN1-AIN5) float. The digital image is then sent to FPGA. I
powered on the board without configuring ADV7181B, so the ADV7181B should
run by the default register values. But I find that ADV7181B failed to
clamp the AC-coupled video input signal to a DC level, so the input signal
is a pure AC signal. I have checked all the peripheral circuits of
ADV7181B. I do not find any problem. The LLC pin output is right and the
REFOUT is 1.71v ...,which looks good. By the way the ADV7181B is a little
bit over-heated.
Anyone ever met the same problem or have any advice?
Thank you!
Leon
Article: 124797Guenter Dannoritzer wrote: > Grumps wrote: >> [posted to comp.arch.fpga + comp.lang.vhdl] >> Hi All >> I've had a quote from a 3rd party to develop a floating point FFT >> core for us (1Mpt). Probably for a Xilinx Virtex5 SXT. >> Obviously I'd like to get some more quotes, but would like to know >> if you have any recommendations? > > Dillon Engineering has a fact sheet about a floating point core on > their web site: > > http://www.dilloneng.com/documents/fpfft_fact.pdf > > Maybe that would give you an alternative to your quote? Thanks. I'll see what they have to say. From removethisthenleavejea@replacewithcompanyname.co.uk Thu Oct 04 08:10:41 2007 Path: newsdbm05.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!goblin2!goblin.stu.neva.ru!news.unit0.net!newsfeed.freenet.de!border2.nntp.ams.giganews.com!nntp.giganews.com!proxad.net!feeder2-2.proxad.net!news.clara.net!wagner.news.clara.net!iris.uk.clara.net From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk> Newsgroups: comp.arch.fpga References: <1191471360.422373.39180@d55g2000hsg.googlegroups.com> Subject: Re: Companies that Manufacture Multi-FPGA Hardware Date: Thu, 4 Oct 2007 16:10:41 +0100 Lines: 40 X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2900.3028 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.3028 X-RFC2646: Format=Flowed; Original X-Complaints-To: abuse@clara.net (please include full headers) X-Trace: fa8a86c0c75ea369580468c8765806816511101a86c307040890ad7147050275 NNTP-Posting-Date: Thu, 04 Oct 2007 16:10:45 +0100 Message-Id: <1191510645.24182.0@iris.uk.clara.net> Xref: prodigy.net comp.arch.fpga:136764 Have a look at our Broaddown4. Can support up to 4 large Virtex-4s when use the expansion socktes. More if we stack boards. Details here http://www.enterpoint.co.uk/moelbryn/broaddown4.html. John Adair Enterpoint Ltd. "O. Olson" <olson_ord@yahoo.it> wrote in message news:1191471360.422373.39180@d55g2000hsg.googlegroups.com... > Hi, > > I am a Grad student. I intend to do a project examining the aspects > surrounding interconnections between FPGAs. I figure that this group > might have professionals working in this area - so it would be a good > place to ask. > > I am looking for the following information: > Companies that Manufacture Multi-FPGA Hardware: > Here, I am looking for company manufacturing Multi-FPGA boards or > even emulation machines. I figure that from this I would be able to > find out details regarding the architecture that they are using. > I have not had much luck in trying to find such companies - but I > still feel I might be missing the obvious ones. Here is what I found. > I hope you could add to the list if you happen to know some more: > > 1. Pro Design Chipit - http://www.uchipit.com/ce/index.htm: These > folks seem like they have a lot of products. But now I am looking for > their competitors. > > 2. Simpod: http://www.simpod.com/: I have not taken a good look at > this company > > 3. The Dini Group: http://www.dinigroup.com/ Sounds like they do have > some products. > > Thanks a lot. > O.O. >Article: 124798
Grumps wrote: > [posted to comp.arch.fpga + comp.lang.vhdl] > Hi All > I've had a quote from a 3rd party to develop a floating point FFT core for > us (1Mpt). Probably for a Xilinx Virtex5 SXT. > Obviously I'd like to get some more quotes, but would like to know if you > have any recommendations? > Thanks. > > I've got a floating point FFT engine for V4 that I am porting to V5. It is the fastest floating point FFT for FPGAs available anywhere (up to 1.2 GS for the 32-2K point FFT). It can be adapted for 1M points and will still beat anything out there for speed/density. There is info on my website http://www.andraka.com regarding my IP, including a paper discussing it.Article: 124799
Steven Derrien wrote: > Hi, > > I am currently working on a circuit which has to perform Hamming > distance computation between large bit vectors (>500 bits). > > I was surprised not to find much information on how to implement this > type of operation *efficiently* on FPGA technology. > > So far I have been investigating two approaches (combining tables and > counter for the bitcouting part). I observed that the choice of table > size (3 or 4 address bits) had a significant impact (20%) on the area > cost of the operator. > > I feel that there are many subtle trade-offs in such implementations, > and I was wondering if anybody had been looking at this problem (most of > the articles I stumbled accross dealt with the correcting code issue, > rather than focusing on the Hamming distance realization in itself). > > Thanks in advances for the input. > > Regards, > > Steven > Most Modern FPGAs have block RAM that can be used for look-ups. Use these as larger LUTs to get partial counts, and then sum up the partials. If you can afford a multiplied clock, you can time multiplex segments of your input vector into a smaller number of RAMs followed by accumulators.
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