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On 7 Mai, 11:22, "Sven" <s...@is.com> wrote: > If i have an external SPI FLASH connected to the FPGA and uses 'Disable > Readback' in the configuration. What does it do exactly? > > It is still possible to read the SPI FLASH externall? the main feature of any ROM (including SPI Flash) is to be readable so if you have some SPI flash then it is always possible to read back if the flash pins can be accessed by any means under software control. AnttiArticle: 118901
On 7 May 2007 01:10:36 -0700, Antti <Antti.Lukats@xilant.com> wrote: <..> > >nono - there was NO PROBLEM..:) >I was just confused that with default setting the INIT LED is 50% on >state.. >this is however NORMAL behaviour, I did not recognize that, and >assumed something was wrong. > >all things work ok on s3astarter, including MicroBlaze - well without >DDR2 support :( > I have not tried yet the DDR2. What is the problem with mch_opb_ddr2 controller? It is a PREFERRED IP type, I thought it should work. I will try to take a look at it, anyway.. Best regards, ZaraArticle: 118902
On 7 Mai, 11:35, Zara <me_z...@dea.spamcon.org> wrote: > On 7 May 2007 01:10:36 -0700, Antti <Antti.Luk...@xilant.com> wrote: > > <..> > > > > >nono - there was NO PROBLEM..:) > >I was just confused that with default setting the INIT LED is 50% on > >state.. > >this is however NORMAL behaviour, I did not recognize that, and > >assumed something was wrong. > > >all things work ok on s3astarter, including MicroBlaze - well without > >DDR2 support :( > > I have not tried yet the DDR2. What is the problem with mch_opb_ddr2 > controller? It is a PREFERRED IP type, I thought it should work. > > I will try to take a look at it, anyway.. > > Best regards, > > Zara Hi Zara, I hope mch_opb_ddr2 will work, but I have been wondering why such demo design is not available - this could be an indication that the "out of the box" DDR2 IP core will not work on Spartan-3A, so I am in a waiting mode, hoping for someone to confirm the useability of EDK DDR2 ipcore on Xilinx Spartan-3A starterkit board. AnttiArticle: 118903
Hi everyone! I'm working with DDR SDRAM but I don't know how to choose row address and column address. Can you help me, please?Article: 118904
Hi I was confronted with such a problem when I opened an old project (which was made in ISE-7.1) in ISE-8.2i. I regenerated all the cores for ISE-8.2i and the problem was solved. Try regenerating the netlists for black boxes. hope it worksArticle: 118905
"Gordon Freeman" <gordonfreeman1983@gmail.com> wrote in message news:1178531084.255221.183550@y5g2000hsa.googlegroups.com... > Hi everyone! > I'm working with DDR SDRAM but I don't know how to choose row address > and column address. > Can you help me, please? > Google 'datasheet'Article: 118906
Hi are there anybody who have knowledge about some free VHDL core for Hitachi H8S or H8/300H CPU? Regards /Michael WilspangArticle: 118907
Gordon Freeman wrote: > Hi everyone! > I'm working with DDR SDRAM but I don't know how to choose row address > and column address. > Can you help me, please? > The Micron website has good datasheets and some application notes for all the SDRAMS. Here's a place to start: http://www.micron.com/products/dram/ddr/partlist.aspx?Select=Select This newsgroup has had many discussions about SDRAMs, both single and double data rate. The basic operation of SDRAMs are the same (active, precharge, read, write, refresh) whether they are single or double data rate, DDR or DDR2. A good tutorial on any of the families would probably answer many of your questions. --- Joe Samson Pixel VelocityArticle: 118908
Does oneone have a Xilinx UCF file for the Spartan Device on the linear technology FastDAACS board, and is willing to share it? Thanks, ThomasArticle: 118909
Hi, can any one please clarify me that all the FF in the FPGA has same setup time and hold time values? If not why and where these different FF can be used? Thanks in advance. regards, Himassk.Article: 118910
On May 5, 6:36 am, Sean Durkin <news_ma...@durkin.de> wrote: > At X-Fest they said that raw mode will be available with EDK9.2, which > is supposed to be available sometime after ISE9.2, which is scheduled > for September, IIRC. Thanks for the info. Unfortunately September is a little too late in my case... PatrickArticle: 118911
On May 7, 5:26 am, Antti <Antti.Luk...@xilant.com> wrote: > On 7 Mai, 11:22, "Sven" <s...@is.com> wrote: > > > If i have an external SPI FLASH connected to the FPGA and uses 'Disable > > Readback' in the configuration. What does it do exactly? > > > It is still possible to read the SPI FLASH externall? > > the main feature of any ROM (including SPI Flash) is to be readable > > so if you have some SPI flash then it is always possible to read back > if the flash pins can be accessed by any means under software control. > > Antti To clarify further, "Disable Readback" means to disable reading the state of the FPGA from its internal SRAM. It has no effect on the configuration storage device. HTH GaborArticle: 118912
I'm trying to code an 'enhanced' binary-to-7segments display decoder
with ATF750CL and WinCUPL.
I'm experiencing problems using the truth table CUPL construct , so I
wrote these test code lines:
Name ATF750CL;
Partno XXXX;
Date Apr 2007;
Revision 0.0 GEAT Floor Display Decoder;
Designer mf;
Company c companyname snc, 2007;
Assembly Custom;
Location Naples;
Device v750c;
/* Input pins */
PIN [1..11] = [in1, in2, in3, in4, in5, in6, in7, in8, in9, in10,
in11];
PIN 13 = in12;
/* Output pins */
PIN [14..23] = [o1, o2, o3, o4, o5, o6, o7, o8, o9, o10];
FIELD input = [in4, in3, in2, in1] ;
FIELD output = [o7, o8, o9, o10] ;
FIELD output2 = [o3, o4, o5, o6] ;
/* Basically the output is a copy of the input */
TABLE input => output {
'b'0000 => 'b'0000;
'b'0001 => 'b'0001;
'b'0010 => 'b'0010;
'b'0011 => 'b'0011;
'b'0100 => 'b'0100;
'b'0101 => 'b'0101;
'b'0110 => 'b'0110;
'b'0111 => 'b'0111;
'b'1000 => 'b'1000;
'b'1001 => 'b'1001;
'b'1010 => 'b'1010;
'b'1011 => 'b'1011;
'b'1100 => 'b'1100;
'b'1101 => 'b'1101;
'b'1110 => 'b'1110;
'b'1111 => 'b'1111;
}
/* And this also, but on different output pins */
output2 = input;
Well, 'output2' behaves correctly, while 'output' pins are always at 0
level.
Do you know why?!?!?!?!?!
PLS HELP!!!!
Article: 118913The output voltage at its most positve will be Vcc, the Vcm will be Vcc - 0.275 and the low voltage will be Vcc - 0.55 This gives 550 mv swing on each arm and 1100mv differential swing. This is an Inphi driver which supports PCML standard. Here is a text directly from Inphi application note: "The HSL outputs are VCC referenced. This means that if an output has a typical 1100 mVp-p differential swing (i.e. 550 mVp-p on each arm), then each output (primary and complementary) varies between approximately Vcc and Vcc - 0.55V, which suggests a common mode voltage, Vcm, that is the average of that range (i.e. Vcc - 0.275V)."Article: 118914
The non-Xilinx driver is not LVPECL. It is CML driver from Inphi.Article: 118915
On May 7, 7:47 am, Test01 <cpan...@yahoo.com> wrote: > The non-Xilinx driver is not LVPECL. It is CML driver from Inphi. A "differential voltage" of 1100 mv implies that each leg is Vcm +/- 550 mv. If Vcm = Vcc - 0.275, then the high leg is in fact above Vcc for the driver. One or more parts of your original specification are likely not correct. AndyArticle: 118916
I have the V5 GTP transceiver differential output going to a non-xilinx receiver. The non-Xilinx receiver has following specifciation for its LVPECL input. Input High Common Mode range is 1.2V to 3.3V The differntial input swing range is 300mv to 2400mv. I would like to know what V5 GTP IO standarad I should use so it meets the receiver requirements. Thanks. Test01.Article: 118917
Has anyone tried to install xilinx webpack on ubuntu 6.06LTS? If I run the web download tool (sudo ./setup) I get through the questions but it dies shortly after I click install. If I use the single file download it asks for a registration ID which as far as I can tell doesn't exist for webpack? Any help is appreciated. Thanks, ClarkArticle: 118918
Andy, It will be great if you can elaborate.Article: 118919
Andy, Here is what I have from the datsheet. The HSL outputs are VCC referenced. This means that if an output has a typical 1100 mVp-p differential swing (i.e. 550 mVp-p on each arm), then each output (primary and complementary) varies between approximately Vcc and Vcc - 0.55V, which suggests a common mode voltage, Vcm, that is the average of that range (i.e. Vcc - 0.275V)."Article: 118920
Gordon Freeman wrote: > I'm working with DDR SDRAM but I don't know how to choose row address > and column address. > Can you help me, please? I'm only familiar with SDRAM, DDR should be somewhat similar wrt/ the commands you must issue (PRECHARGE, ACTIVATE, etc.) To get started on the basics: http://en.wikipedia.org/wiki/SDRAM http://download.micron.com/pdf/datasheets/dram/sdram/512MbSDRAM.pdf http://www.maxwell.com/pdf/me/app_notes/Intro_to_SDRAM.pdf Some technical notes worth reading: http://download.micron.com/pdf/technotes/ZT05.pdf http://download.micron.com/pdf/technotes/ZT01.pdf http://download.micron.com/pdf/technotes/TN4801.pdf An interesting article from Ars Technica: http://arstechnica.com/paedia/r/ram_guide/ram_guide.part2-4.html Hope that helpsArticle: 118921
Hi, Hi, i saw the circuit for computation of branch metric in the following paper ( figure 3 a ), but i cant understand how it functions, can any body plz explain it. http://www.tmssales.com/Application_Notes/Digital_Test/viterbi.pdf thanks. sawaakArticle: 118922
On May 7, 3:25 pm, himassk <hima...@gmail.com> wrote: > Hi, > can any one please clarify me that all the FF in the FPGA has same > setup time and hold time values? > If not why and where these different FF can be used? > > Thanks in advance. > > regards, > Himassk. There are two different FF as a minimum - IO registers and internal logic FF. More specially look into the datasheet for your FPGA. As a rule all datasheets have separate sections for I/O timing parametres and Internal timing ones.Article: 118923
Be aware... DDR SDRAMs have many many other nuances beyond just selecting addresses properly... tons of startup constraints, all sorts of timing requirements between operations, etc... you NEED to read the datasheet cover to cover about a half a dozen times or you will absolutely miss something. On May 7, 5:44 am, Gordon Freeman <gordonfreeman1...@gmail.com> wrote: > Hi everyone! > I'm working with DDR SDRAM but I don't know how to choose row address > and column address. > Can you help me, please?Article: 118924
On May 5, 2:04 pm, fpga_t...@yahoo.com wrote: > When their management learn the products can be supported better with > the same number of people leading the project, and the developers > learn they are not likely to lose their jobs, it should be an easier > decision. It's hard sometimes to understand why they think remaining in the > stone age is better. I've been poking Xilinx through various techniques about this. I talked to three or four people Xilinx about it at the recent Embedded Systems Conference in San Jose; I also tried to talk to Steve Long(? might be misremembering his name) who apparently is a software manager, but I kept missing him. I also asked the support guy who has been handling the bugs I file to pass an email up the chain, and he said he did. Perhaps it'll land with someone who is willing to take me up on an offer to talk about it more. If everyone with a complaint about the quality of the software does this, perhaps Xilinx would realize that there are people out there (such as myself) who think FPGAs are incredibly cool and are willing to work on the software without expectation of payment as long as certain open-source rules are observed. The single best example of this is Michael Gernoth in the thread entitled "Xilinx Platform cable USB and impact on linux without windrvr"[1]. He was willing to work on it despite the lack of source, and his result is /quite/ impressive. I think the main problem is some level of confusion. Open-sourcing XST and the various GUI apps does not mean that map/par need to be fully open-source. Providing map and par as libraries that user-written apps could call would be perfectly acceptable, given the level of trade- secrecy involved. Xilinx is not a software company, and it shows. They should be leveraging the software to increase adoption of the hardware, not limiting industry growth with low software quality. Once the realization of this percolates up, perhaps we'll see some changes. So, once again. If you have a complaint about the quality, make a reasoned argument to whoever at Xilinx will listen. Remember that zealotry and insults won't work here; there is a strong business case for this to happen, but it requires such a shift from traditional thinking that every overzealous attempt will cancel out quite a few reasonable ones. Perhaps one who is a better wordsmith and evangelist than I can come up with a template that others can use. 1) http://groups.google.com/group/comp.arch.fpga/browse_thread/thread/f149e5b6028e2c70
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