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On Apr 20, 11:09 am, "Symon" <symon_bre...@hotmail.com> wrote: > "Matt Sorrensen" <mafr...@optusnet.com.au> wrote in message > > news:132hkt62dc1a9a9@corp.supernews.com...> Hey Guys/Gals, > > > I'm only fairly new to FPGA's, > > Indeed you are, or you'd know there're not many 'Gals' on this newsgroup, > more's the pity... :-) > > > > > I've used the xilinx xc2s400e, but this was on a digilent board and the > > whole environment was set up for me. > > I'm doing my final year thesis for engineering and am highly interested in > > using an FPGA as the IC's I am after, well, dont exist. > > The main purpose of the FPGA is to replace a 32input or gate (which is > > made out of 4-8input or gates and 1x4 input), 32 bit mux (made out of > > 2x16 bit muxes and 1x2bit mux) and 32 d-latches (each latch also has to > > have logic on its input - ie. an extremely simple finite state machine (2 > > states)) > > I am considering using the xilinx xc2s50e... however I do have a couple of > > concerns... > > Do I actually have to 'clock' the chip? or can I have it run > > asynchronously like most logic gates?? > > I do have a few other questions, but thats the main one. > > Cheers > > Matt > > Yep, async will work fine. I guess you have some input which 'clocks' the > latches? > Of course, you're almost certain to want to do something clever later on > which needs a clock. I'd make provision for a oscillator module just in > case. Use something > 24MHz so there are no restrictions on using the > on-chip digital clock managers. > Good luck, Syms. Actually spartan 2e only has DLL's not DCM's so your clock may also want to be related to a useful system frequency. Also be aware that although the internal logic is quite fast (John's note about glitches), getting on and off the chip in a timely manner may require the fastest speed grade. I use a spartan 2 (not e) as a clock multiplexer and needed to use -6 speed grade to get about 6-7 nS pin-to-pin timing. I'm not sure if it's cheaper, but the spartan 2 comes in a smaller core part XC2S15 which is probably still bigger than you need for a few gates. Also when using an FPGA for pin-to-pin combinatorial functions you'll find that keeping the input and output pins near eachother will greatly improve timing, as the routing delays can be larger than logic delays. So for example if you had a 32-bit wide mux, you'd run much faster with a pinout like A0, B0, Y0, A1, B1, Y1, ... than with a pinout like A0, A1, A2, A3, ... A31, B0, B1, ... B31, Y0, Y1, Y2, ... Y31.Article: 118251
I'm looking for a (low-cost) spartan 3 based board, containing a low to medium sized spartan 3 fpga, two 100 MSPS 12 bit AD converters, and ideally also one or two 8-12 bit DA converters, but I didn't find any. Does someone know of such a board? Thanks, ThomasArticle: 118252
On a sunny day (20 Apr 2007 08:37:57 -0700) it happened Antti <Antti.Lukats@xilant.com> wrote in <1177083477.214936.26030@n76g2000hsh.googlegroups.com>: >On 20 Apr., 17:17, DJ Delorie <d...@delorie.com> wrote: >> Colin Paul Gloster <Colin_Paul_Glos...@ACM.org> writes: >> >> > Perhaps he had not been aware of code written in hardware >> > description languages which had >> >> The key word here is "code". IMHO RMS's point is that the types of >> freedoms that the GPL provides (use, change, share) do not apply to >> physical objects, because the cost of copying physical objects is >> non-trivial. So, you can GPL the code *in* an FPGA (software), but >> you can't GPL the FPGA itself (hardware). How could you copy a chip >> and share it with your friends? "Hey Colin, could you email me a >> Spartan 3?" > >well FPGA's DO MAKE it possible to send HARDWARE per email. > >the only assumption is that the receiving party has some equipment >with an FPGA inside. >this maybe the LCD TV as example or some other equipment. > >so by loading the new bit file to the FPGA in his LCD TV the FPGA will >transform to some hardware that did not previously exist at the >premises of the receiver of the "hardware per email"... > >so the issue about licensing is not trivial :) > >Antti Actually there is no difference between what you describe and software. "Hardware" refers to transistors, diodes, silicon, etc... Programs and HDL code (could even contain sequential stuff, a processor) are 'soft', in the sense as paint that can be applied to a canvas. The FPGA / PC, micro, what not, is the canvas. This will all change the day somebody markets the 'replicator' (as in Startrek). Man that would be a day:-) Laws would have to be made, people would be locked away (like the ones who did dollar bills on the first photo color copier)... LOL.Article: 118253
"Jan Panteltje" <pNaonStpealmtje@yahoo.com> wrote in message news:f0aoni$af8$1@news.datemas.de... > > This will all change the day somebody markets the 'replicator' (as in > Startrek). > Man that would be a day:-) > Laws would have to be made, people would be locked away (like the ones who > did > dollar bills on the first photo color copier)... LOL. > You could replicate yourself before the Feds arrive. Which one would they gaol? Syms :-)Article: 118254
"Matt Sorrensen" <mafroew@optusnet.com.au> wrote in message news:132hkt62dc1a9a9@corp.supernews.com... > Hey Guys/Gals, > > I'm only fairly new to FPGA's, I've used the xilinx xc2s400e, but this was > on a digilent board and the whole environment was set up for me. > > I'm doing my final year thesis for engineering and am highly interested in > using an FPGA as the IC's I am after, well, dont exist. > > The main purpose of the FPGA is to replace a 32input or gate (which is > made out of 4-8input or gates and 1x4 input), 32 bit mux (made out of > 2x16 bit muxes and 1x2bit mux) and 32 d-latches (each latch also has to > have logic on its input - ie. an extremely simple finite state machine (2 > states)) > > I am considering using the xilinx xc2s50e... however I do have a couple of > concerns... > > Do I actually have to 'clock' the chip? or can I have it run > asynchronously like most logic gates?? > > I do have a few other questions, but thats the main one. > > Cheers > Matt > For the simple functions you are trying to implement I would recommend a CPLD over an FPGA. Either Altera MaxII or Xilinx equivalent. These will be much cheaper ($2 or $3) and are standalone non volatile instant boot devices, as opposed to an FPGA which will need some separate boot flash and a loader.Article: 118255
On Apr 20, 11:11 am, Jan Panteltje <pNaonStpealm...@yahoo.com> wrote: > Actually there is no difference between what you describe and software. > "Hardware" refers to transistors, diodes, silicon, etc... > Programs and HDL code (could even contain sequential stuff, a processor) are > 'soft', in the sense as paint that can be applied to a canvas. > The FPGA / PC, micro, what not, is the canvas. But doesn't Xilinx being a fabless chip vendor emphasize the point that the transistors, diodes, etc are also "software" in the sense that they too come out of the designers computers as data files? Likewise all modern PCB's. You could argue that becuase they aren't changeable in a given device they are permanent, but then so is software (firmware) in a ROM.Article: 118256
On Apr 20, 12:00 pm, Thomas Heller <thel...@python.net> wrote: > I'm looking for a (low-cost) spartan 3 based board, containing a > low to medium sized spartan 3 fpga, two 100 MSPS 12 bit AD converters, > and ideally also one or two 8-12 bit DA converters, but I didn't find any. > > Does someone know of such a board? > > Thanks, > Thomas 100 MSPS @ 12 bits is a little out of the ordinary for a low-cost FPGA board. I'd suggest looking for an FPGA board with sufficient I/O connections and cobble the system together with an A/D converter board (if you can find that - perhaps an evaluation module from the converter manufacturer?).Article: 118257
On a sunny day (20 Apr 2007 10:14:48 -0700) it happened cs_posting@hotmail.com wrote in <1177089288.591175.246610@d57g2000hsg.googlegroups.com>: >On Apr 20, 11:11 am, Jan Panteltje <pNaonStpealm...@yahoo.com> wrote: > >> Actually there is no difference between what you describe and software. >> "Hardware" refers to transistors, diodes, silicon, etc... >> Programs and HDL code (could even contain sequential stuff, a processor) are >> 'soft', in the sense as paint that can be applied to a canvas. >> The FPGA / PC, micro, what not, is the canvas. > >But doesn't Xilinx being a fabless chip vendor emphasize the point >that the transistors, diodes, etc are also "software" in the sense >that they too come out of the designers computers as data files? >Likewise all modern PCB's. > >You could argue that becuase they aren't changeable in a given device >they are permanent, but then so is software (firmware) in a ROM. Thats is true. You can even think of a relais system, that in fact executes a hardwired sequence -say program- as only hardware. Maybe then it is only 'soft' as long as it is changable and can be copied. There are cases where it is not clear at all, a read protected FLASH micro or FPGA for example. It cannot be read and it cannot be changed (without losing the info), so then it is hardware. This is my view actually, I have sold PICs with code I wrote that just do some hardware function - so it is a different chip say now it is a display driver - as hardware. The new call it 'firmware'. In the patent world. although software here in Europe may not be patentable, 'firmware connected to some functionality is'. I am no lawyer, big companies could kill each other with lawsuits over things this. It is very tricky, should a processor that runs Linux OS make its micro code available under GPL too ;-)? LOLArticle: 118258
Gabor schrieb: > On Apr 20, 12:00 pm, Thomas Heller <thel...@python.net> wrote: >> I'm looking for a (low-cost) spartan 3 based board, containing a >> low to medium sized spartan 3 fpga, two 100 MSPS 12 bit AD converters, >> and ideally also one or two 8-12 bit DA converters, but I didn't find any. >> >> Does someone know of such a board? >> >> Thanks, >> Thomas > > > 100 MSPS @ 12 bits is a little out of the ordinary for a low-cost FPGA > board. I'd suggest looking for an FPGA board with sufficient I/O > connections and cobble the system together with an A/D converter > board (if you can find that - perhaps an evaluation module from the > converter manufacturer?). > I came to the same conclusion by now. I found a 'piggy back' module carrying two A/D and two D/A converters 12 bit@200MSPS [1], maybe I can combine this with an FPGA board type that you mention. The system does not really not to be low cost (I'm not a student), but I assume a board with a Virtex II device [2] with 1 million gates is too large for me. [1] http://www.iaf-bs.de/products/add-on-boards/adda.de.html [2] http://www.hunteng.co.uk/products/fpga/heron-io2.htm Thanks, ThomasArticle: 118259
On Apr 19, 11:39 pm, Jhoberg <jrqueve...@gmail.com> wrote: > This it is a message of Richard Staman creator of free softeare > fundation and GNU on an idea to construct free hardware in FPGAs. > > http://lists.duskglow.com/open-graphics/2007-January/008663.html > > http://en.wikipedia.org/wiki/Richard_Stallman Some nonfree architectures exist at the moment but it is known as a processor JAVA and Core of processor ARM work like in which I could run GNU/Linux in FPGA, like a Spartan3: JAVA Processor http://www.jopdesign.com/ Core ARM http://www.opencores.org/cvsweb.shtml/sARM7TM/ Microblaze http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=micro_blaze http://en.wikipedia.org/wiki/MicroBlazeArticle: 118260
John Adair wrote: > Finally first picture of Darnaw1 our PGA style FPGA board is here here > http://www.enterpoint.co.uk/moelbryn/darnaw1.html. More information on > pricing and spec in the next couple of days will appear on the > website. Those with eagle eyes can work it out the spec from the > picture. Are all the components shown - no photo of the rear ? Does the PGA plug into the side we see, or the other side ? [and the side we see is for probing - but not labelled ? ] -jgArticle: 118261
Icky Thwacket wrote: > "Matt Sorrensen" <mafroew@optusnet.com.au> wrote in message > news:132hkt62dc1a9a9@corp.supernews.com... <snip> >>The main purpose of the FPGA is to replace a 32input or gate (which is >>made out of 4-8input or gates and 1x4 input), 32 bit mux (made out of >>2x16 bit muxes and 1x2bit mux) and 32 d-latches (each latch also has to >>have logic on its input - ie. an extremely simple finite state machine (2 >>states)) > > For the simple functions you are trying to implement I would recommend a > CPLD over an FPGA. Either Altera MaxII or Xilinx equivalent. > These will be much cheaper ($2 or $3) and are standalone non volatile > instant boot devices, as opposed to an FPGA which will need some separate > boot flash and a loader. > Good advice - CPLDs are easier to learn. Most vendors also support simpler language flows, for CPLDs The logic above is close to the bottom end of the scale. So 64 or 128 macrocell CPLDs would be candidates, which points to Vendor Boolean Language Devices Atmel : CUPL : ATF1504/ATF1508 Lattice : ABEL : MACH4064/4128 Xilinx : ABEL : XC2C64, XC2C128, or the XC95xx series Altera : AHDL : MAX7064/MAX7128 ICT : WinPlace : See web link http://www.diodes.com/products/catalog/list.php?parent-id=43 The ICT ones might be light on IO lines.Article: 118262
Hello, I intalled the ISE9.1i and updated it. It can work. Then I installed EDK9.1i. But when I run it, it told me "The procedure entry point ptw32_push_cleanup" could not be located in the dynamic link library libpthread.dll." I intalled them on a Windows XP machine. I have no clue about this error. Can anybody give me some suggestion? Thanks a lot, RebeccaArticle: 118263
On Apr 20, 8:09 am, "maroni" <mar...@interia.pl> wrote: > Hi All, > > I have problem with clock signal in FGPA XC95288XL144. I have 3,3V signal on > the output but I want get 5V signal. I say in addition that I use chip with > 3.3V power supply. Should I use pull up or different operation? What do you > do with clock signal in FPGA? > > Thank you The Xilinx XC9500XL _CPLD_ chips will handle 5 volts on the inputs, but as you noticed, it can only output a 3.3 volt signal. If you need to connect the chip to a CMOS chip that has TTL levels (i.e. 74HCT), then you can directly connect them. However, If you need to connect to a 5-volt CMOS chip (i.e. 74HC), then you need to use a bus switch or a voltage-level translator chip. These chips will usually have both a 5-volt and a 3.3-volt power pin. You can get around this problem by using the XC9500 (not XL) CPLD chips, that run on 5-volts and ouput 5-volt signals. They are more expensive than the XC9500XL chips, especially for the larger chips (i.e. 288 Macro Cells). -Dave PollumArticle: 118264
On Apr 20, 8:31 am, John Adair <g...@enterpoint.co.uk> wrote: I don't know about wirewrap boards with ground availability but one of our thoughts with this product was the user that likes 2-4 layer low technology pcb boards they can assemble themselves. With this product we allow them to stay with the board technology they like but they can have a high performance bga based FPGA in their system. I have seen wirewrap sockets I believe from Mill-Max or Precidip if someone wants to do that. John I've used wire-wrap boards that had plated-thru holes and copper planes on each side. They're made by Twin Industries and I bought them from DigiKey. I use the bottom plane for ground and the top plane for VCC. On the bottom I solder a 1206 cap from the power pin of a chip's socket to the gound plane. I run my wires between pins as if I was laying out a PCB and I DO NOT bundle the wire-wrap wires! I also make sure that I run the wires up against the ground plane to reduce wire inductance and ringing. I've had no problems running 40MHz clocks with 74HCT logic and Xilinx CPLDs (on home-made adapters) with this method. But I think that wire-wrapping a PGA device would be pushing it. -Dave PollumArticle: 118265
Hi, I have designed a motor controller with the Virtex 4 FX-12 Mini-Module and I of course would like the PWM output pins to never go high during startup or programming. They do go high during this time like I don't have control over this. Do I need external circuitry to prevent this? I have already fabricated a board and it would be nice if this could be handled without doing something like that. I am using ISE/ EDK 8.2. In my system.ucf file I specify the pins to be outputs. Run away motors are not acceptable at startup or during programming. Thanks for any help. -EdArticle: 118266
Hi, Dave Pollum wrote: > But I think that wire-wrapping a PGA device would be pushing it. http://www.fpga-games.com/images/game_top.jpg http://www.fpga-games.com/images/game_bot.jpg The Xilinx FPGA is a PG191. Some of us just don't know when to stop! EricArticle: 118267
Greetings... I have been trying to use a block memory component (in this case just a single port ROM to start with... will be adding a dual port RAM once I get this part working) in ISE Webpack 9.1i, generated of course by the Core Generator. I'm quite sure that my syntax is correct; I have the component declared in my main vhdl module's architecture header, and an instance declared in the body with the ports mapped to the intended signals/ports in my main module. XST synthesizes this with no errors. However, for some reason I'm finding that both the input and output signals connected with the ROM (addr in and data out) are always showing up as indeterminate in both simulation and implementation. Is there any common reason why this might be? Thanks, SteveArticle: 118268
Haha, Indeed it is a shame there isnt that many 'gals' on here, but its better to be safe than sorry :-) With the latches, what I hope to achieve is basically like a storage device. I have 32 inputs coming in and wish to read back the values at a later time, hence the mux, which i described wrong as being a 32-bit mux, I should've said a 32input mux (32 inputs to 1 output, 5 select lines). When you say "Yep, async will work fine. I guess you have some input which 'clocks' the latches?" - all I want the latches to do is to be able to decide when the input has gone high and to latch this value, that is, the input to the latch is the "output of the latch" OR "the input". I will also have a Reset Line to clear these values. Does this mean that I wont have to add a clock signal to it? I do agree that having provisions for a clock input is a great idea - thanks :-) Thanks for all the hints and tips guys it is very much appreciated - Regards Matt "Gabor" <gabor@alacron.com> wrote in message news:1177084401.664989.74460@q75g2000hsh.googlegroups.com... > On Apr 20, 11:09 am, "Symon" <symon_bre...@hotmail.com> wrote: >> "Matt Sorrensen" <mafr...@optusnet.com.au> wrote in message >> >> news:132hkt62dc1a9a9@corp.supernews.com...> Hey Guys/Gals, >> >> > I'm only fairly new to FPGA's, >> >> Indeed you are, or you'd know there're not many 'Gals' on this newsgroup, >> more's the pity... :-) >> >> >> >> > I've used the xilinx xc2s400e, but this was on a digilent board and the >> > whole environment was set up for me. >> > I'm doing my final year thesis for engineering and am highly interested >> > in >> > using an FPGA as the IC's I am after, well, dont exist. >> > The main purpose of the FPGA is to replace a 32input or gate (which is >> > made out of 4-8input or gates and 1x4 input), 32 bit mux (made out of >> > 2x16 bit muxes and 1x2bit mux) and 32 d-latches (each latch also has >> > to >> > have logic on its input - ie. an extremely simple finite state machine >> > (2 >> > states)) >> > I am considering using the xilinx xc2s50e... however I do have a couple >> > of >> > concerns... >> > Do I actually have to 'clock' the chip? or can I have it run >> > asynchronously like most logic gates?? >> > I do have a few other questions, but thats the main one. >> > Cheers >> > Matt >> >> Yep, async will work fine. I guess you have some input which 'clocks' the >> latches? >> Of course, you're almost certain to want to do something clever later on >> which needs a clock. I'd make provision for a oscillator module just in >> case. Use something > 24MHz so there are no restrictions on using the >> on-chip digital clock managers. >> Good luck, Syms. > > > Actually spartan 2e only has DLL's not DCM's so your clock may also > want to be > related to a useful system frequency. Also be aware that although the > internal > logic is quite fast (John's note about glitches), getting on and off > the chip in a > timely manner may require the fastest speed grade. I use a spartan 2 > (not e) > as a clock multiplexer and needed to use -6 speed grade to get about > 6-7 nS > pin-to-pin timing. I'm not sure if it's cheaper, but the spartan 2 > comes in a smaller > core part XC2S15 which is probably still bigger than you need for a > few gates. > > Also when using an FPGA for pin-to-pin combinatorial functions you'll > find that > keeping the input and output pins near eachother will greatly improve > timing, as > the routing delays can be larger than logic delays. So for example if > you had a > 32-bit wide mux, you'd run much faster with a pinout like A0, B0, Y0, > A1, B1, Y1, ... > than with a pinout like A0, A1, A2, A3, ... A31, B0, B1, ... B31, Y0, > Y1, Y2, ... Y31. >Article: 118269
That was another of my concerns, so the memory on the xilinx xc2s50e is volatile? The main reason I was considering using an FPGA was that I have access through uni to the development boards - which mind you are a pain to set up as well as lecturers/students who have done the courses. Plus I already have the code written for what I require. :-) and 'hopefully' it works I will check out the CPLD's however Thanks for your advice Cheerrs Matt "Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message news:46291d9a$1@clear.net.nz... > Icky Thwacket wrote: > >> "Matt Sorrensen" <mafroew@optusnet.com.au> wrote in message >> news:132hkt62dc1a9a9@corp.supernews.com... > <snip> >>>The main purpose of the FPGA is to replace a 32input or gate (which is >>>made out of 4-8input or gates and 1x4 input), 32 bit mux (made out of >>>2x16 bit muxes and 1x2bit mux) and 32 d-latches (each latch also has to >>>have logic on its input - ie. an extremely simple finite state machine (2 >>>states)) >> >> For the simple functions you are trying to implement I would recommend a >> CPLD over an FPGA. Either Altera MaxII or Xilinx equivalent. >> These will be much cheaper ($2 or $3) and are standalone non volatile >> instant boot devices, as opposed to an FPGA which will need some >> separate boot flash and a loader. > > Good advice - CPLDs are easier to learn. > Most vendors also support simpler language flows, for CPLDs > > The logic above is close to the bottom end of the scale. > So 64 or 128 macrocell CPLDs would be candidates, which points to > > Vendor Boolean Language Devices > Atmel : CUPL : ATF1504/ATF1508 > Lattice : ABEL : MACH4064/4128 > Xilinx : ABEL : XC2C64, XC2C128, or the XC95xx series > Altera : AHDL : MAX7064/MAX7128 > ICT : WinPlace : See web link > > http://www.diodes.com/products/catalog/list.php?parent-id=43 > > The ICT ones might be light on IO lines. > > > >Article: 118270
cs_posting@hotmail.com wrote: > On Apr 19, 12:14 pm, Kunal <kunal.yadwad...@gmail.com> wrote: > >> Some suggestions were the spartan-3 starter kit, XSK40 and the XSK95. >> Being a poor student, I can't afford anything else (and being a >> beginner I guess I may not be able to _use_ anything else :) ) > > The Spartan-3 kit is pretty good, complete out of the box, and you'll > find some projects for it around the net. I would spend the extra $20 > to get an XC3S400 chip on it though (get it from Digilent rather than > Xilinx). > > I see they are also offerings the XC3S1000, though you could get that > chip cheaper on the nexys board. The nexys board is interesting if > you want to play with USB for high-bandwidth things, and it has better > digital I/O's. But it lacks the serial, keyboard, and VGA ports of > the S3kit. Also, if you go that route you may want to buy one of > their great-deal power supplies and parallel port programmer cables so > you aren't completely dependent on the USB for power and programming. > > Which brings up the point: if your development computer doesn't have a > parallel port, get they nexys rather than the s3kit. > The Nexys is a pretty decent board for a beginner, I think. The Spartan 3E looks a little bit more daunting with all of the extra gizmos. If you have a professor/possible mentor who knows a lot about these things, then you'd be fine either way.. if you don't have anybody to refer to when you're stuck on something, I'd recommend a simpler board. I have to say I'm not terribly impressed with some of the add-on boards: for example, the analog VGA RGB signals are generated by four digital inputs going into various resistors, combined with direct analog addition.. seems kind of cheap for what they charge for it, but I have tested it out, and it does actually work. Also the documentation on their graphic LCD board is quite terrible.. nowhere on digilent's site is there any information on what the interface is, you can find the site of the Chinese company that made it, but their documentation is also really spotty. These are kind of specific complaints. I do like the breadboard that connects to the hirose board-to-board connector, though I haven't used it yet.. it seems handy.Article: 118271
On Fri, 20 Apr 2007 16:09:18 +0100, "Symon" <symon_brewer@hotmail.com> wrote: >"Matt Sorrensen" <mafroew@optusnet.com.au> wrote >> Hey Guys/Gals, >> I'm only fairly new to FPGA's, >Indeed you are, or you'd know there're not many 'Gals' on this newsgroup, >more's the pity... :-) Oh, I don't know. I think Lattice still manufacture GALs, don't they? :-) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK jonathan.bromley@MYCOMPANY.com http://www.MYCOMPANY.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 118272
In article <f08isd$9mg$1@news.lysator.liu.se>, Andreas Ehliar <ehliar@lysator.liu.se> wrote: > (I'd love to hear about a Xilinx board with Audio input/output in > the same price range. We are interested in such a board for a course > we are giving since it would be nice if students could afford the > board.) The Spartan 3E starter kit has dual-channel A/D and D/As. MHz+ sampling rate per channel. You will have to add audio amplifiers, probably, but that's no big deal. > Personally, I would also like to point out that getting DDR memory > to work is not straightforward. If DDR memory is your only external > memory (and you are building a design which needs more memory than > is available on the FPGA) you are going to be in trouble. (Unless > you buy the EDK which can automatically generate a design with > a DDR memory controller for you.) DDR is complicated by the fact > that you have to run it quite fast if you are going to follow > the standard. The EDK has a short time free trial when you buy the starter kit. I know that Xilinx has a 'Memory Interface Generator' for producing a DDR interface that's free-as-in-beer if you register http://www.xilinx.com/products/design_resources/mem_corner/ I haven't tried it, and most of what I know is that 'how do I get it work?' is a FAQ on this group. -- David M. Palmer dmpalmer@email.com (formerly @clark.net, @ematic.com)Article: 118273
To Peter Alfke, Symon and John Larkin: Thank you for your help. We had design a PCB board to test the method you told us and we could get it next Tuesday (April, 24th). However, we do a simple experiment to have a simple qualitative analysis. We use a scope of 2.5G/S and 10GSa/S. The conclusion is fairly positive. The figures can not be posted here, so they are posted on my blog. So please visit the site: http://xieyu1219.blogspot.com/ to see it. Thank you! If we have further information, we will also tell you.Article: 118274
Jim What you see on the current photo are the solder joints of a double ended pin so the pins come out the bottom as currently done. Given we don't need to meet a specific pinout we could take them out the top if someone need one that way or even have a socket + pin assembly like we use in out OVERCOAT arrays. We can also make these with an un- populated header and this could be a lot cheaper for high numbers used in production say in a low pin count application. The PGA pin header is not cheap either to purchase or even to assemble so I would recommend anyone with a specific interest that would want a a few+ should come and talk to us. We can deal with Bill of of Materials variants for 5-10+ shipping units and can even be economic on a customised pcb variant of any of our products in fairly small numbers (say 25+ off on a small product like this). Our development board products really are only a demo of what we can do and supply ideas to be used in a mix and match fashion on customer specific designs. John Adair Enterpoint Ltd. On 20 Apr, 20:58, Jim Granville <no.s...@designtools.maps.co.nz> wrote: > John Adair wrote: > > Finally first picture of Darnaw1 our PGA style FPGA board is here here > >http://www.enterpoint.co.uk/moelbryn/darnaw1.html. More information on > > pricing and spec in the next couple of days will appear on the > > website. Those with eagle eyes can work it out the spec from the > > picture. > > Are all the components shown - no photo of the rear ? > > Does the PGA plug into the side we see, or the other side ? > [and the side we see is for probing - but not labelled ? ] > > -jg
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