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I don't know about ultraedit, but emacs VHDL mode does a wonderful job colorizing and beautifying source code. I use it exclusively... It also has a nice hierarchy browser and lots of other VHDL specific functionality built in. There are some nice cheat sheets available through a google search that have all the important keyboard shortcuts as well... On Apr 23, 10:11 am, "mans" <(myname_here)_123...@yahoo.com> wrote: > Hello, > I decided to test UltraEdit to see how good is it in reformatting a > VHDL code and indenting smartly. To do this I installed ultraedit and I did > a test by asking UE to reformat this code for me: > > process (Rst) > begin > if clk='1' then > > if Rst='1' then system_state <= wait_for_input; > > end if; > end if; > end process; > > and I got this: > > process (Rst) begin if clk='1' then > > if Rst='1' then system_state <= wait_for_input; > > end if; end if; end process; > > which I think is not a good reformatting. > > My question is: > > Can UE reformat VHDL code and doing the smart indentation on it? > Is the result that I am getting correct? > Am I missing anything? > My search on the web showed that I should get a new file for this, Am I > right? Where can I get it? > > RegardsArticle: 118301
On Apr 19, 8:50 am, Derek Simmons <dereks...@gmail.com> wrote: > Can anyone explain to me what the difference is betweenMPM7064LC84 > and EPM7064LC84? > > Thanks, > Derek Hi Derek, The MPM7064 is the mask-programmed version of the EPM7064. This was the early 90s version of HardCopy (Altera's current Structured ASIC product). Basically a designer would take the design and POF file, give it to Altera, and Altera would make a version that is hard-wired. Cheaper, but not reprogrammable. Like HardCopy devices are today, but much smaller. This program is no longer in place, at least for new designs. The march of technology means that for this density, the mask-programmed option is not really cheaper. These devices tend to be IO pad-limited, so it doesn't really matter how small the logic area is. For new designs in this density the MAX3000 or MAX II product lines will be cheaper while retaining the reprogammability. If you have some old chips marked MPM7064LC84 then they really can't be used for anything else in the way that old EPM7064LC84s could be. Sincerely, Greg Steinke Altera Corporation gregs@altera.comArticle: 118302
Hello, I was wondering if anyone knows if it's possible to perform a "non- intrusive" readback operation on the FPGA configuration data in order to verify its correctness and to ensure that it hasn't been corrupted (specifically for a Xilinx Virtex 5). Looking through the datasheet, I can find all the information required to DO a readback, but I can't seem find anything regarding whether or not it's intrusive. Thanks a lot. PepiArticle: 118303
Pepi, The readback for all Xilinx FPGA's is non-intrusive by design. It wouldn't be very useful if it wasn't. The LUTRAM bits are marked as "volatile" by the programming software so that a readback of the CLB contains only that information that is intended to be static (not changing) so a compare may be done to see which bits have flipped. There is a mask file which is also created by the programming software that marks all the commands and non-information bits so they are not part of the readback compare. Note that the readback does contain the BRAM contents, and if the design is changing the BRAM contents, then those changes will show up as differences. You may intentionally mask out the BRAM contents if you are not interested in those bits changing (see app note below). The application note: http://www.xilinx.com/bvdocs/appnotes/xapp714.pdf Details how an IP core may be used to have the device check (and correct) itself. The BRAM may be excluded from this check (and correct). This core is also useful for testing, as it may be used to inject errors. By injecting errors one can determine if the system you have is robust in terms of how it mitigates against failures (does it fail gracefully? and recover? does it meet what you intended?). AustinArticle: 118304
More, The app note is for V4, but also applies to V5. Austin Austin Lesea wrote: > Pepi, > > The readback for all Xilinx FPGA's is non-intrusive by design. > > It wouldn't be very useful if it wasn't. > > The LUTRAM bits are marked as "volatile" by the programming software so > that a readback of the CLB contains only that information that is > intended to be static (not changing) so a compare may be done to see > which bits have flipped. > > There is a mask file which is also created by the programming software > that marks all the commands and non-information bits so they are not > part of the readback compare. > > Note that the readback does contain the BRAM contents, and if the design > is changing the BRAM contents, then those changes will show up as > differences. You may intentionally mask out the BRAM contents if you > are not interested in those bits changing (see app note below). > > The application note: > > http://www.xilinx.com/bvdocs/appnotes/xapp714.pdf > > Details how an IP core may be used to have the device check (and > correct) itself. The BRAM may be excluded from this check (and correct). > > This core is also useful for testing, as it may be used to inject > errors. By injecting errors one can determine if the system you have is > robust in terms of how it mitigates against failures (does it fail > gracefully? and recover? does it meet what you intended?). > > AustinArticle: 118305
On Apr 23, 11:47 am, ddal...@gmail.com wrote: > Hi, > I am having a problem with a design. When DONE cycle is set to 5 or 6 > DONE pin never goes high. I have confirmed that the part is > configuring by scoping the output from the DCM. The part is a 2S300E. > > When I scope out the INIT line I find that after 280mS the INIT line > returns to a High-Z state - I believe that this is interupting the > state machine so causing the DONE pin not to go high. > > If I set the DONE cycle to 1, 2, 3 or 4 - DONE goes high and INIT > stays high. > > Any help would be appreciated > > Dave What mode are you using to program the part? Is your configuration clock continuing to run at the end of configuration? Often stopping the clock too soon is the cause of this sort of problem. HTH, GaborArticle: 118306
cs_posting@hotmail.com wrote: > On Apr 23, 8:45 am, Eli Hughes <emh...@psu.edu> wrote: > >>> Unless someone really needs an S3E chip, I might stay away from that >>> board, as part of its schematics (around the USB chip) are withheld, >>> limiting your options for programming and communicating with it to >>> what is officially supported or laboriously reverse engineered. >> IMHO this argument for a student using the kit is somewhat absurd. I >> work at a Government lab tied to a University and see Undergrad and Grad >> students all the time (we provide a great deal of funding for them). >> >> The USB interfaces is for JTAG download (probably the guts to the Xilinx >> USB cable). If they are just learning about FPGAs, the last thing they >> are going to worry about is the mechanism the USB cable uses to download >> the bitstream. > > The poster is not a student using a school supplied board, he's > someone with the personal funding to buy one board and one board > only. So it should be something that he can get long term varied use > out of. Something that might not be limiting to a studnet who will > soon move on to other platforms or courses could be a real limitation > in this case. And one of the long term issues with FPGAs is what do > you want to do with them - if it involves quantities of data, getting > that into and out of the board becomes a challenge. USB is a great > interface for that - but if its not documented, it becomes even harder > than it needs to be. > >> To make the argument that you options for communicating and configuring >> are limiting to student the board is just plain wrong. There is spot >> for a normal JTAG header on the PCB to use the VIII and IV cables. >> Trust me, most don't really care about how the USB download circuit >> operates. People just care that they can get the code in the chip. > > Great, another cable to buy. Hopefully it at least can accomodate the > $12 digilent cable as supplied with the S3Kit (I know nexys can, but > that's a digilent-unique product rather than one done for xilinx) > > You can still be a student and not be at a University. :-) H I can understand wanting to have information about a PCB, but there is a certain point when you just use what is given. For $150 you pretty much have everything you could need for learning FPGAs. You get a fat FPGA with RAM, FLASH, Screen, Ethernet, a multitude of ways of getting you program to the chip, expansion port and free software tools. This board would keep just about anyone busy for a long time. Just because the USB download cable is considered 'closed', I am not sure you can do a whole of complaining for $150. Given that it states in the manual that it is used for *EASY* configuration (just what someone learning needs), I wouldn't think that this would be a deal breaker.Article: 118307
motty wrote:
> I am using ModelSim SE and was wondering if there is a way to make a
> waveform display mnemonics. I am simulating a state machine and it
> would be convenient to have the waveform display the state name
> instead of the binary/hex of the state. I looked all over the
> documentation and didn't find anything.
>
> The module is written in verilog and the states are parameterized. NC-
> Sim had an easy way to map numerical values to text. You create the
> mapping and then can apply it to any waveform. I just haven't found
> an easy way to do this in ModelSim. It is probably staring me in the
> face!
>
I've started using the SystemVerilog enumerated types; these are also
accepted by Synplify. Synplify will also display the state names in its
state machine diagrams.
For Verilog 2001, I set up a separate string as described in another
post but I put it in its own combinational process and then display it
as a string in Modelsim. E.g.,
reg [32*8-1:0] StateStr;
parameter IDLE=1,START=2;
always@(State)
case(State)
IDLE: StateStr="IDLE";
START: StateStr="START";
endcase
-Kevin
Article: 118308I am using using the Xilinx project navigator Version 6.2i for writing the VHDL code and synthesize it .I am facing a problem with the signals defined with the real data type.The navigator indicates that the code (with some signals defined as real ) is syntactically correct but it gives an error during synthesis.It states this feature is not supported. After checkin out for a solution we ended up finding that a math_real package in ieee.std_logic_1164.all is copyright protected.So actually am unable to understand wat to do to get teh package.Article: 118309
I am using using the Xilinx project navigator Version 6.2i for writing the VHDL code and synthesize it .I am facing a problem with the signals defined with the real data type.The navigator indicates that the code (with some signals defined as real ) is syntactically correct but it gives an error during synthesis.It states this feature is not supported. After checkin out for a solution we ended up finding that a math_real package in ieee.std_logic_1164.all is copyright protected.So actually am unable to understand wat to do to get teh package.Article: 118310
cs_posting@hotmail.com wrote: > On Apr 20, 3:08 pm, Jim Granville <no.s...@designtools.maps.co.nz> > wrote: > > >>>For the simple functions you are trying to implement I would recommend a >>>CPLD over an FPGA. Either Altera MaxII or Xilinx equivalent. >>>These will be much cheaper ($2 or $3) and are standalone non volatile >>>instant boot devices, as opposed to an FPGA which will need some separate >>>boot flash and a loader. >> >>Good advice - CPLDs are easier to learn. >>Most vendors also support simpler language flows, for CPLDs > > > Very true, alas I suspect CPLD's are to blame for the present lack of > gals... Oh, the gals are still about, now just a bit long in the tooth, and not as attractive as they were in the past! :) -jgArticle: 118311
I have an application where I need to use 20 V5 GTPs each running at 3.2 Gbps to trasmit data out to a source synchronous device. I will have a separate FPGA for 20 channel transmitter and separate FPGA 20 channel receiver. My application does not require 8b/10b encoding. Thus it can be disabled in all 20 transceivers. For transmitter portion, I was thiking about enableing the serial loop back mode of each transciever. The loopback can be used to determine all 20 channels are aligned to one another. I keep reseting all 20 transceivers until all 20 channels are aligned. In addition to this, I can have a precise delay element with 10 ps resolution in line with each transceivers. On power up, I can have a training algorithm to do to channel alignment with respct to a 3.2 GHz clock. I would like to know if this is possible using Xiilnx V5 FPGA. I have looking into using the High speed LVDS I/O of V5 but that does not give the data rate I am looking for. Any help in this will be greatly appreciated.Article: 118312
On Apr 23, 4:43 am, Colin Paul Gloster <Colin_Paul_Glos...@ACM.org> wrote: > Colin Paul Gloster posted: > "On 2000 March 8th Richard M. Stallman has made a presentation in > Trinity > College Dublin. Near the end, a member of the audience has asked a > question re the GPL and hardware. Richard M. Stallman has responded > appreciating no relevance of freedom to hardware. Perhaps he had not > been aware of code written in hardware description languages which had > already been licensed according to the second version of the GPL by > that time, and perhaps he has revised his opinion." > > Innews:xn7is7dqij.fsf@localhost.localdomaintimestamped 20 Apr 2007 > 11:17:24 -0400, DJ Delorie <d...@Delorie.com> of DJGPP responded: > "The key word here is "code". IMHO RMS's point is that the types of > freedoms that the GPL provides (use, change, share) do not apply to > physical objects, because the cost of copying physical objects is > non-trivial. So, you can GPL the code *in* an FPGA (software), but > you can't GPL the FPGA itself (hardware). How could you copy a chip > and share it with your friends? "Hey Colin, could you email me a > Spartan 3?"" > > DJ's point may be completely true. I can not remember word for word > what the hardware question slightly over seven years and one month ago > was, and I do not remember word for word what Stallman's answer was > then, but Stallman definitely did not demonstrate any awareness of > HDLs at the time. He did not answer then by saying "We encourage the > idea of free hardware designs", in contrast to > HTTP://Lists.DuskGlow.com/open-graphics/2007-January/008663.html The concept would be a free architecture in this implemented which drivers and some functions of DSP of, but for this could be to constuir a sintetizer with GPLArticle: 118313
On Apr 23, 4:31 am, "david.oriot" <david.or...@rftronic.com> wrote: > Hello, > > One other solution is to use the HSWAP_EN pin of your FPGA... > > This pin control the behavior of the user I/O pins (i.e internal > pull-ups activated or not) when the FPGA configures itself... > > You may apply a high level on the HSWAP pin to disable pull ups, and, on > the other hand, connect pull-down resistors on the PWM outputs. > > Hope this helps. > > With best regards > > David Oriot > > > > Peter Alfke wrote: > > The cleanest solution is to change the external logic from active High > > to active Low. > > Or to insert simple CMOS inverters to achieve the same result. > > Peter Alfke > > > On Apr 21, 7:42 am, "Rob" <robns...@frontiernet.net> wrote: > >> You should have more thoroughly read the datasheet. Yes, you will need > >> external pull-down resistors. I'm sure the V4 uses a weak-pull up > >> (specified in the datasheet) during this time so you won't need a strong > >> pull-down. I think you'll have to re-work your board. > > >> "Ed" <RobotBuil...@charter.net> wrote in message > > >>news:1177111861.217085.11500@e65g2000hsc.googlegroups.com... > > >>> Hi, > >>> I have designed a motor controller with the Virtex 4 FX-12 Mini-Module > >>> and I of course would like the PWM output pins to never go high during > >>> startup or programming. They do go high during this time like I don't > >>> have control over this. Do I need external circuitry to prevent > >>> this? I have already fabricated a board and it would be nice if this > >>> could be handled without doing something like that. I am using ISE/ > >>> EDK 8.2. In my system.ucf file I specify the pins to be outputs. Run > >>> away motors are not acceptable at startup or during programming. > >>> Thanks for any help. > >>> -Ed- Hide quoted text - > > - Show quoted text - >From Xilinx Answer Record 18277 Virtex, Spartan I/O - I/O outputs might transition during configuration http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=18277 Within the Answer Record is : "Xilinx strongly recommends designing systems in such a way that outputs from the device are ignored during configuration." You might want to read this Answer Record. NewmanArticle: 118314
This it is a message of Richard Staman creator of free softeare fundation and GNU on an idea to construct free hardware in FPGAs. http://lists.duskglow.com/open-graphics/2007-January/008663.html http://en.wikipedia.org/wiki/Richard_Stallman Some nonfree architectures exist at the moment but it is known as a processor JAVA and Core of processor ARM work like in which I could run GNU/Linux in FPGA, like a Spartan3: JAVA Processor http://www.jopdesign.com/ Core ARM http://www.opencores.org/cvsweb.shtml/sARM7TM/ Microblaze http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.j... http://en.wikipedia.org/wiki/MicroBlaze The concept would be a free architecture in this implemented which drivers and some functions of DSP of, but for this could be to constuir a sintetizer with GPLArticle: 118315
"Hrishi" <sankpalhrishi@gmail.com> wrote in message news:1177355988.516759.66970@d57g2000hsg.googlegroups.com... >I am using using the Xilinx project navigator Version 6.2i for writing > the VHDL code and synthesize it .I am facing a problem with the > signals defined with the real data type.The navigator indicates that > the code (with some signals defined as real ) is syntactically correct > but it gives an error during synthesis.It states this feature is not > supported. After checkin out for a solution we ended up finding that a > math_real package in ieee.std_logic_1164.all is copyright protected.So > actually am unable to understand wat to do to get teh package. And how do you think it should work? VHDL is a hardware description language, not a programming language. More likely than not your problem can be solved in fixed-point arithmetic. If it can't then you need to create some sort of a floating-point hardware in your FPGA to work with real numbers. This topic was discussed here in the past. Google the group for floating point... /MikhailArticle: 118316
Test01, Better is to use the IP already developed for this, known as "channel bonding." Transceivers identified as being part of a group thus have all of the sequencing taken care of for you (and you do not have to figure out the best way to do it, we already did). 8B10B allows the links to pass any stream of data: without 8B10B you must have some kind of coding to prevent long strings of 0's or 1's (which leads to loss of clock). Channel bonding is a standard feature of Xilinx MGTs (since VII Pro). The core to support this is the Aurora protocol (any number of channels), or XAUI core (for 10Gbs Ethernet): http://www.xilinx.com/products/design_resources/conn_central/grouping/aurora.htm http://www.xilinx.com/bvdocs/ipcenter/data_sheet/gtpwizard_ds590.pdf http://www.xilinx.com/bvdocs/ipcenter/data_sheet/xaui.pdf AustinArticle: 118317
On 23 Apr., 21:20, Hrishi <sankpalhri...@gmail.com> wrote: > I am using using the Xilinx project navigator Version 6.2i for writing > the VHDL code and synthesize it .I am facing a problem with the > signals defined with the real data type.The navigator indicates that > the code (with some signals defined as real ) is syntactically correct > but it gives an error during synthesis.It states this feature is not > supported. After checkin out for a solution we ended up finding that a > math_real package in ieee.std_logic_1164.all is copyright protected.So > actually am unable to understand wat to do to get teh package. "Real" is not supported for synthesis. As simple as that. There is a floating point logi core available that you can use instead. Kolja SulimmaArticle: 118318
Hello all, my question - I/O-Standards - I have searched the WWW up and down, but I'm really not happy what I have found. Especially HSTL vs. SSTL - what is better, newer... Some comments/hints/infos/pdfs from you? Many thanks in advance UdoArticle: 118319
It seems to me that all these problems are eliminated when there is an external pull-up resistor, and the external logic is active Low. i.e. a High output coming from the FPGA disables external logic, or forces it idle or otherwise into a safe condition. Peter Alfke On Apr 23, 1:04 pm, Newman <newman5...@yahoo.com> wrote: > On Apr 23, 4:31 am, "david.oriot" <david.or...@rftronic.com> wrote: > > > > > Hello, > > > One other solution is to use the HSWAP_EN pin of your FPGA... > > > This pin control the behavior of the user I/O pins (i.e internal > > pull-ups activated or not) when the FPGA configures itself... > > > You may apply a high level on the HSWAP pin to disable pull ups, and, on > > the other hand, connect pull-down resistors on the PWM outputs. > > > Hope this helps. > > > With best regards > > > David Oriot > > > Peter Alfke wrote: > > > The cleanest solution is to change the external logic from active High > > > to active Low. > > > Or to insert simple CMOS inverters to achieve the same result. > > > Peter Alfke > > > > On Apr 21, 7:42 am, "Rob" <robns...@frontiernet.net> wrote: > > >> You should have more thoroughly read the datasheet. Yes, you will need > > >> external pull-down resistors. I'm sure the V4 uses a weak-pull up > > >> (specified in the datasheet) during this time so you won't need a strong > > >> pull-down. I think you'll have to re-work your board. > > > >> "Ed" <RobotBuil...@charter.net> wrote in message > > > >>news:1177111861.217085.11500@e65g2000hsc.googlegroups.com... > > > >>> Hi, > > >>> I have designed a motor controller with the Virtex 4 FX-12 Mini-Module > > >>> and I of course would like the PWM output pins to never go high during > > >>> startup or programming. They do go high during this time like I don't > > >>> have control over this. Do I need external circuitry to prevent > > >>> this? I have already fabricated a board and it would be nice if this > > >>> could be handled without doing something like that. I am using ISE/ > > >>> EDK 8.2. In my system.ucf file I specify the pins to be outputs. Run > > >>> away motors are not acceptable at startup or during programming. > > >>> Thanks for any help. > > >>> -Ed- Hide quoted text - > > > - Show quoted text - > >From Xilinx Answer Record 18277 > > Virtex, Spartan I/O - I/O outputs might transition during > configuration > > http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountry... > > Within the Answer Record is : > > "Xilinx strongly recommends designing systems in such a way that > outputs from the device are ignored during configuration." > > You might want to read this Answer Record. > > NewmanArticle: 118320
Udo, HSTL and SSTL are I/O standards, that is all. Some chips use one, some use the other. There is no such thing as "better" or "newer." SSTL pre-dates HSTL (SSTL: Stub Series Terminated Logic) with a 3.3 V version, a 2.5V version, and a 1.8V version. HSTL came right after SSTL(High-Speed Transceiver Logic) with a 1.5 volt version. Many HSTL implementations were not fast enough, and a 1.8 volt version of HSTL was "created" in order to meet the speed that was desired (just ran the ASIC at 1.8 volts instead of 1.5 volts). In the FPGA, the only difference between HSTL and SSTL is choice of drive strength, as the input comparator is identical in implementation for both (both use an externally provided reference voltage). The termination schemes are the same (resistors to termination reference power supply). There are four classes of termination, to handle single direction, or bi-directional data paths. Some classes may be better for your application than others. The standards are often ignored when components are placed very close to the FPGA, and resistors are omitted (not used). If you choose a standard, you are best to stick by it. If you decide to not follow the standard, you may be successful, but you are required to do all the signal integrity engineering to prove it works. You are best to do the SI engineering (simulate the interfaces) anyway, as just because it is a standard does not mean you have used it properly. AustinArticle: 118321
Ed, We designed the IO pins so that they are not asserted (i.e. they are kept tristate) while the part is powering ON, and while it is going through its configuration. Only after "DONE" goes high are the outputs now under the control of the bitstream that the customer has loaded. For those who want a 'defined' power ON condition, we provide the HSWAPEN pin, so that instead of IO being tristate, we enable the weak pullup for all IOs. Grounding this pin enables the weak pullups on all IO. Tying this pin high disables the weak pullups while configuring. A 'kludge' (temporary fix) would be to take and add 1K to 10K resistors on the pins that are critical to ground. The IO standard used on these pins would have to be strong enough to drive the resistor loads, and still provide the voltages required. The value of the resistor needs to be determined by the other drive sources at this node (perhaps there is another weak pullup somewhere else?). AustinArticle: 118322
I think the OP said his board is already designed and thus it might not be a choice to reverse the logic. Also, dead bugging IC's onto a board may be more troublesome than just using pull-downs. CMOS inverters need power and ground, in addition to the signals that you desire to invert, which can make the re-work a bit ugly. I guess it depends on how many signals are affected. If it just a couple then using the resistors is probably the best way to go; but if you're talking about dozens of signals then perhaps octal inverters would be the better choice. "Peter Alfke" <peter@xilinx.com> wrote in message news:1177364886.992772.12130@p77g2000hsh.googlegroups.com... > It seems to me that all these problems are eliminated when there is an > external pull-up resistor, and the external logic is active Low. i.e. > a High output coming from the FPGA disables external logic, or forces > it idle or otherwise into a safe condition. > Peter Alfke > > On Apr 23, 1:04 pm, Newman <newman5...@yahoo.com> wrote: >> On Apr 23, 4:31 am, "david.oriot" <david.or...@rftronic.com> wrote: >> >> >> >> > Hello, >> >> > One other solution is to use the HSWAP_EN pin of your FPGA... >> >> > This pin control the behavior of the user I/O pins (i.e internal >> > pull-ups activated or not) when the FPGA configures itself... >> >> > You may apply a high level on the HSWAP pin to disable pull ups, and, >> > on >> > the other hand, connect pull-down resistors on the PWM outputs. >> >> > Hope this helps. >> >> > With best regards >> >> > David Oriot >> >> > Peter Alfke wrote: >> > > The cleanest solution is to change the external logic from active >> > > High >> > > to active Low. >> > > Or to insert simple CMOS inverters to achieve the same result. >> > > Peter Alfke >> >> > > On Apr 21, 7:42 am, "Rob" <robns...@frontiernet.net> wrote: >> > >> You should have more thoroughly read the datasheet. Yes, you will >> > >> need >> > >> external pull-down resistors. I'm sure the V4 uses a weak-pull up >> > >> (specified in the datasheet) during this time so you won't need a >> > >> strong >> > >> pull-down. I think you'll have to re-work your board. >> >> > >> "Ed" <RobotBuil...@charter.net> wrote in message >> >> > >>news:1177111861.217085.11500@e65g2000hsc.googlegroups.com... >> >> > >>> Hi, >> > >>> I have designed a motor controller with the Virtex 4 FX-12 >> > >>> Mini-Module >> > >>> and I of course would like the PWM output pins to never go high >> > >>> during >> > >>> startup or programming. They do go high during this time like I >> > >>> don't >> > >>> have control over this. Do I need external circuitry to prevent >> > >>> this? I have already fabricated a board and it would be nice if >> > >>> this >> > >>> could be handled without doing something like that. I am using >> > >>> ISE/ >> > >>> EDK 8.2. In my system.ucf file I specify the pins to be outputs. >> > >>> Run >> > >>> away motors are not acceptable at startup or during programming. >> > >>> Thanks for any help. >> > >>> -Ed- Hide quoted text - >> >> > - Show quoted text - >> >From Xilinx Answer Record 18277 >> >> Virtex, Spartan I/O - I/O outputs might transition during >> configuration >> >> http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountry... >> >> Within the Answer Record is : >> >> "Xilinx strongly recommends designing systems in such a way that >> outputs from the device are ignored during configuration." >> >> You might want to read this Answer Record. >> >> Newman > >Article: 118323
On Apr 23, 10:15 pm, "MM" <m...@yahoo.com> wrote: > And how do you think it should work? VHDL is a hardware description > language, not a programming language. Well, it could work exactly as for integers. Alle the real operators have well defined single cycle implementations that could be instantiated by the high level synthesis. This would be very easy to support as a synthesis tool vendor. The reason why it is not implemented is, that single cycle floating point operations are rarely a good design point. If next to all users want a different implementation anyway there is not much point in supporting it. OTOH chips are getting bigger and multi cycle floating point with a throughput of one result per cycle are not uncommon. High level synthesis could try to gather enough flip-flops by retiming to instantiate an operator with a higher latency. I at least find it strange that so much progress is happening in SystemC and other high level synthesis languages while at the same time the VHDL synthesis vendors stick to the same language subset that synopsis defined eons ago. XST even discourages the use of arrays and records, for gods sake. This is not the 90s anymore. Kolja SulimmaArticle: 118324
Ed wrote: > Hi, > > I have designed a motor controller with the Virtex 4 FX-12 Mini-Module > and I of course would like the PWM output pins to never go high during > startup or programming. They do go high during this time like I don't > have control over this. Do I need external circuitry to prevent > this? I have already fabricated a board and it would be nice if this > could be handled without doing something like that. I am using ISE/ > EDK 8.2. In my system.ucf file I specify the pins to be outputs. Run > away motors are not acceptable at startup or during programming. > Thanks for any help. How many PWM pins are involved, and what is their load ? - some MOSFET drivers have enable pins, and most have internal pulldowns, to give a defined state when the master IC floats. In that case, you would choose the Float-during-config option. General 'good design' would be to have a separate 'OK to GO" flag, into the driver chips, and that inhibits on many signals, besides FPGA Config Done, you might want to include Low Vcc, wdog, and POST Pass ready signals, before you fire up the 'Big Iron' -jg
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