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Messages from 97775

Article: 97775
Subject: communication b/w ethernet and fpga
From: "aayush" <aayush_v2@rediffmail.com>
Date: 27 Feb 2006 10:16:32 -0800
Links: << >>  << T >>  << A >>
hi
i am using spartan2 XC2S50.i am trying to communicate fpga with a
computer , using a lan card. i found out that the voltages levels arent
the same. can anyone tell me how i should go about it ....i have read
about level translaters. but dont know where to find one and which one
to use.......help me please .......anyone 
thankyou all


Article: 97776
Subject: Re: XC9500 JTAG Initialize problem
From: "Benjamin Todd" <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPITALS.ch>
Date: Mon, 27 Feb 2006 19:21:25 +0100
Links: << >>  << T >>  << A >>
Whereabouts are you using the HC125 devices? Are you sure you haven't 
inadvertantly inverted the signals?
A schematic or pinout would be helpful... (post it online somewhere and link 
to it)

Like Antii says, a quick solution is potentially an RC to remove the 
glitches, but it would nice to know exactly what's going on.

BTW: You should try moving away from the old foundation software... but I 
guess your cable isn't supported for newer versions... In any event I use a 
Parallel Cable IV with the XC9500, still using ISE7.1, will upgrade to 8 
when it settles down. It works very well.

Ben

"Chelam" <scpadala@gmail.com> wrote in message 
news:cOednX_YcKEqlJzZnZ2dnUVZ_sOdnZ2d@giganews.com...
> Hai
>
> XC9500 is not initialized and .log file directing me to look for hardware
> config problems.
> I have Connected Parallel cable and using JTAG interface(assembled).  All
> of JTAG Connections and VCC, GND connections were made properly
> The Part Iam tring to use :PLCC84-15.
> The software ( ISE3.3i)  has been  tried on both win-98 and
> Win-2000.Hardware
> working with Pentium IV processor.
>
> When observed on scope, I have seen glitches on TDI TDO and TCk pins.As
> suggested in Parallel III cable, I am using HC125 ICs. How to kill them.
>
> Any suggestions!
>
> Thanks
> Chelam
>
> 



Article: 97777
Subject: Re: The 95108 cpld is getting heated when connected by CRO
From: Jim Granville <no.spam@designtools.co.nz>
Date: Tue, 28 Feb 2006 07:25:49 +1300
Links: << >>  << T >>  << A >>
Augast15 wrote:
> hi,
> There is 4.5 V supply for entire circuit throughout the board.
> 
> I am testing with schmitt trigger today 
> thanx guies

Can you give the full part number ?
You do realise the 95108 will get warm, anyway, because of
the high Icc - have you measured just how much current it
draws ?
'Getting heated' is not quite good enough...
-jg


Article: 97778
Subject: Re: fpga to 5v ttl logic
From: Jim Granville <no.spam@designtools.co.nz>
Date: Tue, 28 Feb 2006 07:30:43 +1300
Links: << >>  << T >>  << A >>
John_H wrote:

> "Jim Granville" <no.spam@designtools.co.nz> wrote in message 
> news:44016131$1@clear.net.nz...
> <snip>
> 
>>Why ? - noise immunity, ease of interface : have you ever tried to
>>find a power MOSFET that can be driven from 3.3V ?
>>
>>-jg
> 
> 
> Have you ever tried to find a 5V MOSFET that wants to be driven by a 24mA 
> logic drive?  It seems that FET drivers (standalone parts with 2A or more 
> drive) are better done outside the FPGA. 

That depends very much on the application: FET drivers are used where
fast gate dV/dT is essential - commonly in fast SMPS designs.

  If you are driving a relay, or a motor on your wing mirror, or door 
lock, then ns edges are actually a liability.
  We sometimes use Series Gate resistors, to deliberately slow down the
edges. In those cases, you would not use 24mA option, but 8mA instead.

-jg


Article: 97779
Subject: Re: tricks to make large PLAs fast?
From: Eric Smith <eric@brouhaha.com>
Date: 27 Feb 2006 11:02:18 -0800
Links: << >>  << T >>  << A >>
John Adair wrote:
> Is the 12nS a result of the a build with a timing constraint set or run 
> without?

I put registers on the inputs and outputs, and set a timing constraint
for the cycle time at 8 ns.

Last night I tried synthesizing the same source for a Virtex 4 LX in
the -12 speed grade, with timing-based mapping turned on and the map
and par efforts set to high, and a 5 ns constraint.  It got it down
to 10 levels of logic, but still took a hair under 10 ns.  I'll try
this again on the Spartan 3E.

It takes a very long time to run that, so most of the time during
development I'll use the default settings and live with a lower
clock speed.

Eric

Article: 97780
Subject: Re: tricks to make large PLAs fast?
From: Eric Smith <eric@brouhaha.com>
Date: 27 Feb 2006 11:03:34 -0800
Links: << >>  << T >>  << A >>
Brian Drummond wrote:
> Have you tried simply comparing "optimize for area" versus "optimize for
> delay" settings in the synthesis tool?

I think I was using optimize for delay, but I didn't save the report files
so I'll have to run it again to be sure.

> That can make a big difference,
> at least with Leonardo Spectrum; you don't say which synth tool you are
> using.

I'm just using the ISE synthesis.

Thanks,
Eric

Article: 97781
Subject: Re: FPGA: Model-SIm XE problem
From: Mike Treseler <mike_treseler@comcast.net>
Date: Mon, 27 Feb 2006 11:17:32 -0800
Links: << >>  << T >>  << A >>
bijoy wrote:
> Object 'aw' cannot be used within the same interface as it is declared.

You could pass the generics as natural
and do the vector conversions elsewhere
as shown below.

          -- Mike Treseler
--____________________________
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.numeric_std.all;

entity fifo is
    generic(AW             : natural := 16;
            PROG_EMPTY_THD : natural := 255;
            PROG_FULL_THD  : natural := 22222);
    port (rst           : in  std_logic;
          write_address : out unsigned(AW-1 downto 0);
          read_address  : out unsigned(AW-1 downto 0);
          wr_clk        : in  std_logic);
end entity fifo;

architecture synth of fifo is
    subtype  vec is unsigned (aw downto 0);
    constant empty_c : vec := to_unsigned(PROG_EMPTY_THD, AW);
    constant full_c  : vec := to_unsigned(PROG_FULL_THD, AW);
begin  -- architecture synth
end architecture synth;

-- vcom -93 -quiet -work work /evtfs/home/tres/vhdl/play/fifo.vhd
-- Compilation finished at Mon Feb 27 11:12:45

Article: 97782
Subject: PCI configuration for ML310
From: "igelado@gmail.com" <igelado@gmail.com>
Date: 27 Feb 2006 12:08:23 -0800
Links: << >>  << T >>  << A >>
Hello All,
 I'm trying to get Linux working on the Xilinx ML310 using a PCI
hardware configuration, other than the one provided by Xilinx. I have a
base configuration which I created using the EDK 7.1sp1.

 I've been able to compile a 2.4.30pre-1 linuxppc kernel, after making
little modifications to the source due to some values (like the device
ID of the OPB-PCI bridge) were hardcoded into it. Right now I have the
kernel more or less working (there are sporadic kernel panics) if I use
no PCI devices but the IDE controller. In order to get the IDE working
I had to use as interrupt the 31. In the hardware configuration this
interrupt is connected to the PCI-SBR pin (by the way, what is this pin
for?).

 If I include other PCI device into the kernel configuration, the
driver is able to read the registers and memory from the device. The
problem is related to the interrupts, it seems that only the "SBR
interrupt" is being received.  At this point, I have some questions
about how interrupts are delivered from the PCI devices to the
interrupt controller.

 Looking at the system.vhd I see that the SBR pin is connected to the
interrupt 0, lines PCI<n>_INT are connected to interrupts 1 to 6, and
the IP2INTC line is connected to interrupt 12. The problem is that I
don't know which line is actually used to deliver the interrupts coming
from the PCI devices. I've tried using all of them, but all attempts
were failed.

 On the PCI base configuration provided by Xilinx I see that they use a
IPcore called misc_logic, which seems to merge all interrupts lines
(some of them are even inverted) into a single one, but I do not
understand why should I do it. Could anybody explain me the actual
reason?

 It would be great if somebody could explain me how does the whole
thing related to the interrupts from PCI devices works. At least I
would like to know which interrupt line is supposed to be asserted when
the ethernet card, the USB bridge (or whatever PCI device you prefer)
launches an interrupt, so then I can try looking into the linux kernel
code to fix the problem knowing that the interrupt line is being
asserted.

Thanks in advance and best regards,
 Isaac


Article: 97783
Subject: Re: tricks to make large PLAs fast?
From: Jim Granville <no.spam@designtools.co.nz>
Date: Tue, 28 Feb 2006 09:18:29 +1300
Links: << >>  << T >>  << A >>
Eric Smith wrote:
> I have a design with a large PLA, and I'm trying to make it run fast in
> a Spartan-3.  It's too big for block RAM, since it has 25 inputs,
> slightly fewer than 512 product terms, and 32 outputs.

That's a large array - does it really cover 2^25 combinations,
or can you compress the inputs, so that the remainder can fit into
Block Ram(s) ?

-jg


Article: 97784
Subject: Re: A dev board supporting partial/dynamic reconf.
From: "jenze" <jenze@et.upb.de>
Date: 27 Feb 2006 12:56:17 -0800
Links: << >>  << T >>  << A >>
> Hello,
> Could U please suggest me a development board which really supports
> partial/dynamic reconfiguration, satisfying one crucial requirement:
>
> ** being shipped with one or more reference designs exploiting
> partial/dynamic reconf **
>
> It would also be nice if the board:
> - exploited FPGA self-reconf capabilities (e.g., the Xilinx ICAP
> component)
> - cost less than 1000 $
> - had an embedded OS ported on it
>
> I of course know not all these requirements can be satisfied at the
> same time!! :)
> the OS is not really important for now...
>
> Many many thanks for your help
>
> pablo

Hi pablo,

we have developed a rapid prototyping system with partial
reconfiguration in mind (and currently working on another one...). For
more information visit
http://www.raptor2000.de
http://www.raptor2000.de/sct/extern/raptor2000/module/
http://www.raptor2000.de/sct/extern/raptor2000/hauptplatine/
(mostly in german...sorry for that). Feel free to contact us for more
information, we are also working on partial reconfiguration.

Regards

Jens


Article: 97785
Subject: Re: Combinatorial Division?
From: "logjam" <grant@cmosxray.com>
Date: 27 Feb 2006 13:12:21 -0800
Links: << >>  << T >>  << A >>
I soldered a PQFP144 package with one of those dull pointed radio shack
irons.  Used a lot of solder flux and dragged the tip along the 4 sides
of the chip.  Worked great.  Out of the two chips I soldered I had one
bridge.  (which I found before the smoke test ;) )  I haven't had to do
one of those in a few years, but now I have a much better solder statio
so hopefully I could do better this time.  :)

I was thinking about a transistor based computer last night.  What kind
of memory can I use in a transistor computer without cheating?  Core
memory?  Should I just have a goal of "transistor CPU" and consider the
ram a peripheral?

One guy built a relay computer but used a 62256 for ram.  :)


Article: 97786
Subject: Re: NGCBUILD .. MDT error on Virtex 4
From: Paul Hartke <phartke@Stanford.EDU>
Date: Mon, 27 Feb 2006 13:24:55 -0800
Links: << >>  << T >>  << A >>
Are you running this on Linux or Windows?  
What is the EDK project directory?  Windows sometimes doesn't like
spaces in the paths to the EDK project directory.  

Paul

Cog_Rad_link wrote:
> 
> Hi,
> 
> I have been facing the following errors when I tried to generate a
> bitstream for the Microblaze softcore to be ported on to Virtex 4 FPGA
> board.
> 
> Running NGCBUILD ...
> ERROR:MDT - microblaze_0_wrapper (microblaze_0) - xyz.mhs:46 - failed
> to copy to implementation
> ERROR:MDT - mb_opb_wrapper (mb_opb) - xyz.mhs:66 -failed to copy to
> implementation
> ERROR:MDT - debug_module_wrapper (debug_module) - xyz.mhs:74 - failed
> to copy to implementation
> ERROR:MDT - ilmb_wrapper (ilmb) - xyz.mhs:92 - failed to copy to
> implementation
> ERROR:MDT - dlmb_wrapper (dlmb) - xyz.mhs:100 -failed to copy to
> implementation
> ERROR:MDT - dlmb_cntlr_wrapper (dlmb_cntlr) - xyz.mhs:108 - failed to
> copy to implementation
> ERROR:MDT - ilmb_cntlr_wrapper (ilmb_cntlr) - xyz.mhs:117 - failed to
> copy to implementation
> ERROR:MDT - lmb_bram_wrapper (lmb_bram) - xyz.mhs:126 - failed to copy
> to implementation
> ERROR:MDT - rs232_wrapper (rs232) - xyz.mhs:133 -failed to copy to
> implementation
> ERROR:MDT - rs232_usb_wrapper (rs232_usb) - xyz.mhs:149 - failed to
> copy to implementation
> ERROR:MDT - leds_4bit_wrapper (leds_4bit) - xyz.mhs:165 - failed to
> copy to implementation
> ERROR:MDT - push_buttons_3bit_wrapper (push_buttons_3bit) - xyz.mhs:179
> - failed to copy to implementation
> ERROR:MDT - dip_switches_8bit_wrapper (dip_switches_8bit) - xyz.mhs:193
> - failed to copy to implementation
> ERROR:MDT - flash_ready_wrapper (flash_ready) - xyz.mhs:207 - failed to
> copy to implementation
> ERROR:MDT - sysace_compactflash_wrapper (sysace_compactflash) -
> xyz.mhs:221 - failed to copy to implementation
> ERROR:MDT - platgen failed with errors!
> make: *** [implementation/microblaze_0_wrapper.ngc] Error 2
> Done.
> 
> Earlier when I was using the older version, I never got these errors
> and everything was working perfectly. But when the licenses got
> expired, and when I installed the 7.1i versions of EDK and ISE these
> errors started occuring. Can anyone please throw some light on this
> issue. I have been stuck with this for the past 4 weeks and am not able
> to find any resources on the internet for this. It would be great if
> anyone can let me know about this.
> 
> Thanks a lot.
> 
> A.

Article: 97787
Subject: Re: Combinatorial Division?
From: "Isaac Bosompem" <x86asm@gmail.com>
Date: 27 Feb 2006 13:52:19 -0800
Links: << >>  << T >>  << A >>

Jan Panteltje wrote:
> On a sunny day (26 Feb 2006 15:33:20 -0800) it happened "Isaac Bosompem"
> <x86asm@gmail.com> wrote in
> <1140996800.146251.277360@e56g2000cwe.googlegroups.com>:
> >
> >For myself, I hand-built a Z80 SBC about 2 yrs ago, it still works
> >today :) :
> >I clocked the CPU @ 2.45Mhz (same clock into USART), have 2KB of flash
> >and 32KB of RAM and a single 8-bit output port. It is a nice
> >development system. I wrote some IEEE754 FP library in Z80 assembly. It
> >was relatively painless since I am fairly comfortable with the x86 and
> >scores other CPU's instruction set.
>
> Hey, Z80 cool.
> I build a Z80 system in the eighties, needed an OS too, so I wrote a CP/M
> emulator for it, disassembler, practically any application soft you can think
> of, has even audio audio editor, and then wrote a multitasking kernel for the
> z80 that ran text windows and mouse... then the 64 kByte was full.
>  http://panteltje.com/panteltje/z80/index.html
> diagrams are there too, the thing is in the attic, 2 euro card backplanes
> with CPU, IO (EPROM programmer), serial IO, DRAM RAM disk, VDU,
> more, cannot remember.... lots of plug-in Euro cards.
> But honestly I would not want to go back to Z80 today.
> Should take some pictures some day, probably the EPROMS are duff by now...
> For 1 M$ you can buy it and the rights to the CP/M emulator for embedded ;-)
> However the multitasker is still on 5 inch flop, and I have no way these days
> to make a copy..
> That dz80 disassembler was actually one of my first C programs, and it shows....
> People seem to be using it though.

Neat site, your system is far more complex than mine, from the
schematics I can see you are using some form of memory banking? I opted
out of using banking and DMA to make it easy for me to build. I will
take a look at your source, thanks for sharing ! :)

-Isaac


Article: 97788
Subject: Re: Combinatorial Division?
From: Jan Panteltje <pNaonStpealmtje@yahoo.com>
Date: Mon, 27 Feb 2006 21:56:46 GMT
Links: << >>  << T >>  << A >>
On a sunny day (27 Feb 2006 13:12:21 -0800) it happened "logjam"
<grant@cmosxray.com> wrote in
<1141074741.277115.149960@i40g2000cwc.googlegroups.com>:

>I was thinking about a transistor based computer last night.  What kind
>of memory can I use in a transistor computer without cheating?  Core
>memory?  Should I just have a goal of "transistor CPU" and consider the
>ram a peripheral?
Normally you could use flip flops as static memory, it would lose state
when power goes down.
I have seen a very nice memory device (analog at that), it consisted of
a small poly cap, on the gate of a CMOS transistor.

It was charged via a neon and resistor (70 V needed to conduct the neon) from
a + 100V or -100V via a switch.
Believe it or not, it held state for month.
This was used in a color tv set to adjust the brightness / contrast / etc.. think it was Siemens,
and likely patented (the switches were up-down buttons).
So, maybe you can switch with CMOS transistors from normal + and ground.
Depends on the leakage, else some neons and some HV transistors should give you
this.
You can then use a window discriminator to store say 4 bits or more at the time in
one poly cap.
 
               up                               +12
               ---                              |
+100 ----------0 0-------                       |
                         |                 |----
              down       |----------------||     MOSFET         
               ---       |         |       |----
-100 ----------0 0-------          |            |---------0 out
                                  === poly     [ ] R  
                                   |  cap       |
                                  /// gnd      /// 



Article: 97789
Subject: Re: Combinatorial Division?
From: Jan Panteltje <pNaonStpealmtje@yahoo.com>
Date: Mon, 27 Feb 2006 22:08:34 GMT
Links: << >>  << T >>  << A >>
On a sunny day (27 Feb 2006 13:52:19 -0800) it happened "Isaac Bosompem"
<x86asm@gmail.com> wrote in
<1141077139.844754.322250@i40g2000cwc.googlegroups.com>:

>
>Jan Panteltje wrote:
>> On a sunny day (26 Feb 2006 15:33:20 -0800) it happened "Isaac Bosompem"
>> <x86asm@gmail.com> wrote in
>> <1140996800.146251.277360@e56g2000cwe.googlegroups.com>:
>> >
>> >For myself, I hand-built a Z80 SBC about 2 yrs ago, it still works
>> >today :) :
>> >I clocked the CPU @ 2.45Mhz (same clock into USART), have 2KB of flash
>> >and 32KB of RAM and a single 8-bit output port. It is a nice
>> >development system. I wrote some IEEE754 FP library in Z80 assembly. It
>> >was relatively painless since I am fairly comfortable with the x86 and
>> >scores other CPU's instruction set.
>>
>> Hey, Z80 cool.
>> I build a Z80 system in the eighties, needed an OS too, so I wrote a CP/M
>> emulator for it, disassembler, practically any application soft you can think
>> of, has even audio audio editor, and then wrote a multitasking kernel for the
>> z80 that ran text windows and mouse... then the 64 kByte was full.
>>  http://panteltje.com/panteltje/z80/index.html
>> diagrams are there too, the thing is in the attic, 2 euro card backplanes
>> with CPU, IO (EPROM programmer), serial IO, DRAM RAM disk, VDU,
>> more, cannot remember.... lots of plug-in Euro cards.
>> But honestly I would not want to go back to Z80 today.
>> Should take some pictures some day, probably the EPROMS are duff by now...
>> For 1 M$ you can buy it and the rights to the CP/M emulator for embedded ;-)
>> However the multitasker is still on 5 inch flop, and I have no way these days
>> to make a copy..
>> That dz80 disassembler was actually one of my first C programs, and it shows....
>> People seem to be using it though.
>
>Neat site, your system is far more complex than mine, from the
>schematics I can see you are using some form of memory banking?
It is the 265 kB dynamic RAMdisk.
It is addressed as floppy drive B
It has its own refresh, the Z80 main memory was originally 64k dynamic ram,
but as soon as I could get 32 kB static I replaced the main memory by 2 of those.

> I opted
>out of using banking and DMA to make it easy for me to build. I will
>take a look at your source, thanks for sharing ! :)

Right, no DMA needed for the floppy, but the floppy controller used a FDC8072A
(as in IBM PC) and an analog PLL :-)
In polling!
There is a DMA, but never used it for floppy transfers.
The other oddity is the display, i t is IO mapped, has its own memory.
The processor has to write a display address and data for each byte via IO.
Exactly the same mechanism as the RAM disk, but now with static RAM.
I also used the display memory (the invisible part) to store the CCP for warm boot....
Faster :-)

Article: 97790
Subject: Re: Combinatorial Division?
From: Jan Panteltje <pNaonStpealmtje@yahoo.com>
Date: Mon, 27 Feb 2006 22:17:10 GMT
Links: << >>  << T >>  << A >>
On a sunny day (27 Feb 2006 13:12:21 -0800) it happened "logjam"
<grant@cmosxray.com> wrote in
<1141074741.277115.149960@i40g2000cwc.googlegroups.com>:

Forgot the resistor and neon,
100V - Vburn_neon should be below gate breakdown of MSOFET.
Use fixed font.
 
               up                                  +12
               ---                                  |
+100 ----------0 0--                                |
                    |        neon               |----
              down  |-- R--- -)(---------------||     MOSFET         
               ---  |               |           |----
-100 ----------0 0--                |                |---------0 out
                                   === poly         [ ] R  
                                    |  cap           |
                                   /// gnd          /// 



Article: 97791
Subject: Re: miniuart
From: zhangweidai@gmail.com
Date: 27 Feb 2006 14:21:45 -0800
Links: << >>  << T >>  << A >>
Thank you John. You've provided me with much help so far!
Ive found some great tutorial/start programs to try on my fpga
picoblaze or something.


Article: 97792
Subject: Re: Combinatorial Division?
From: "Michael Hennebry" <hennebry@web.cs.ndsu.nodak.edu>
Date: 27 Feb 2006 15:20:38 -0800
Links: << >>  << T >>  << A >>
fpga_toys@yahoo.com wrote:
> Josh Rosen wrote:
> > > I suspect, but didn't figure it out, that there is a Booth Recoding
> > > analog for such a divider design. You can use the top bits of the
> > > remainer to select the shift amount, which cuts the cycles in half for
> > > a serial design, so I didn't worry it that hard.
> > This is the two bit at a time algorithm that I was talking about. Back in
> > the 70s this was the most cost effective way to implement division.
>
> Is the two bit at a time algorithm a Booth Recoding analog, or variable
> shifter algorithm?
>
> > Modern machines, and FPGAs, have fast multipliers so convergence division is the
> > best choice today.
>
> Except for the fact that logjam is "I'm building a 64bit ALU using
> standard TTL devices."

As noted earlier, there are sub-quadratic combinitorial designs for
both multiplication and division even when working with basic gates.
"Sub-quadratic" refers to the amount of hardware.
They are at worst linear in terms of delay.

Note that in two dimensions, quadratic in the amount of hardware
implies at least linear in the amount of delay.


Article: 97793
Subject: System crashes when configuring altera stratix pci board
From: "MT" <mohit.tiwari@gmail.com>
Date: 27 Feb 2006 16:35:52 -0800
Links: << >>  << T >>  << A >>
Hi,

I have been trying to get Altera's Stratix PCI Development Kit to work.
The device on the board is EP1s25f1020c5.
My design has a 32 bit PCI target core, alongwith a simple backend
design that
- sends a ready signal back to the PCI core following a framen signal
from the core
- and then reads in data (in case of a target write)

When I try to use the sof file to configure the device, the whole
system hangs. The configuration LED shows that the device is
configured.

The Altera documentation says a system hang is expected whenever the
PCI board is programmed when plugged into the PCI slot of the device,
and says a reset (without shutting down the power) should get the board
going. However, in my case, the system crashes so badly that even the
reset button has no effect.

I had found a reference to a similar problem, where they had found that
their backend was not responding to signals from the core in an
expected manner, thus crashing the system. I have gone through the
reference design and the Altera pdf, and kept my backend simple and
hopefully correct.

Has somebody ever faced this system hang situation while configuring an
Altera pci board? Where can the problem be? Help and comments are
wholeheartedly appreciated. 

Mohit


Article: 97794
Subject: Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit
From: Jerry Coffin <jcoffin@taeus.com>
Date: Mon, 27 Feb 2006 17:45:10 -0700
Links: << >>  << T >>  << A >>
In article <1140882498.644680.13880
@e56g2000cwe.googlegroups.com>, brimdavis@aol.com says...

[ ... ]

>  I had hopes of doing some wide LVDS testing (14-16 bit) using
> the S3E board when I first saw the schematics, given the new
> well-grounded expansion connector, and the soft-touch and
> unloaded terminators indicating some differential pair routing.
> 
>  Unfortunately, after reviewing the {mirrored} gerbers and schematics,
> many of  the "high speed" I/O connector signals are shared with
> other LED's and connectors, resulting in huge stubs on those lines,
> which are routed FPGA -> Hirose Connector -> other stuff, mostly on
> inner layers ( i.e. can't cut the stub off at the Hirose pad ).
>
>  There's maybe 7 unencumbered differential pair pins routed to the
> connector, of which four are input-only pins without LVDS output
> drivers.
> 
>  Oh well; it's still a good value for the price, I just wish they'd
> manage to include provisions for high speed I/O one of these years.

I'm a bit surprised that John Adair didn't reply to this.

Take a look at paged 13 and 14 of:

http://www.enterpoint.co.uk/moelbryn/RaggedStone_User_Man
ual_Issue_1_03.zip

It looks like their RaggedStone1 board should let you use 
28 LVDS pairs quite easily. They indicate that they've 
routed the traces to minimize skew on those pairs too.

-- 
    Later,
    Jerry.

The universe is a figment of its own imagination.

Article: 97795
Subject: Re: ironic Xcell journal 1Q2006 cover art, S3E Starter Kit
From: Jerry Coffin <jcoffin@taeus.com>
Date: Mon, 27 Feb 2006 18:14:55 -0700
Links: << >>  << T >>  << A >>
In article <MPG.1e6d4ae5ad903e029896b8@news.sunsite.dk>, 
jcoffin@taeus.com says...

[ ... ]

> It looks like their RaggedStone1 board should let you use 
> 28 LVDS pairs quite easily. They indicate that they've 
> routed the traces to minimize skew on those pairs too.

Oops -- that's 28 pairs per DIL, so the total's actually 
56, not 28.

-- 
    Later,
    Jerry.

The universe is a figment of its own imagination.

Article: 97796
Subject: Re: How to use Gigabit transciever
From: gregs@altera.com
Date: 27 Feb 2006 17:19:45 -0800
Links: << >>  << T >>  << A >>

pinku wrote:
> Hello Groups,
> I am planning to use gigabit transceiver (Stratix GX), so wanted to
> know what additional glue logic i have to design around it. I think i
> need some glue for transmit part like synchronization, Packetization
> and idle data generation as i cannot feed raw data to the SERDES.
> Please let me know your suggestion. Any pointers to application note
> will also be great.
>
> Thanks and regards
> Praveen

Hi Praveen,
Altera has developed a MegaCore called SerialLite just for this reason.
It is designed to handle the 8b10b encoding, crc error detection,
packetization, and so forth.
These web pages have the application note and also the information on
dowloading it.
http://www.altera.com/products/ip/iup/seriallite/m-alt-seriallite2.html

Sincerely,
Greg Steinke
gregs@altera.com


Article: 97797
Subject: Moreover, the fpga hangs even when I configure a very simple design too...
From: "MT" <mohit.tiwari@gmail.com>
Date: 27 Feb 2006 17:56:22 -0800
Links: << >>  << T >>  << A >>
Sorry, I forgot to add that configuring even a simple design on the
board, that just assigns constant values to USER_LEDs, also
successfully hangs the entire system, so that it cannot be reset
softly.

Although if the system is hanging waiting for a response from the PCI
design, that might explain the above case too.



MT wrote:
> Hi,
>
> I have been trying to get Altera's Stratix PCI Development Kit to work.
> The device on the board is EP1s25f1020c5.
> My design has a 32 bit PCI target core, alongwith a simple backend
> design that
> - sends a ready signal back to the PCI core following a framen signal
> from the core
> - and then reads in data (in case of a target write)
>
> When I try to use the sof file to configure the device, the whole
> system hangs. The configuration LED shows that the device is
> configured.
>
> The Altera documentation says a system hang is expected whenever the
> PCI board is programmed when plugged into the PCI slot of the device,
> and says a reset (without shutting down the power) should get the board
> going. However, in my case, the system crashes so badly that even the
> reset button has no effect.
>
> I had found a reference to a similar problem, where they had found that
> their backend was not responding to signals from the core in an
> expected manner, thus crashing the system. I have gone through the
> reference design and the Altera pdf, and kept my backend simple and
> hopefully correct.
>
> Has somebody ever faced this system hang situation while configuring an
> Altera pci board? Where can the problem be? Help and comments are
> wholeheartedly appreciated. 
> 
> Mohit


Article: 97798
Subject: Re: tricks to make large PLAs fast?
From: Eric Smith <eric@brouhaha.com>
Date: 27 Feb 2006 17:58:25 -0800
Links: << >>  << T >>  << A >>
Jim Granville <no.spam@designtools.co.nz> writes:
> That's a large array - does it really cover 2^25 combinations,
> or can you compress the inputs, so that the remainder can fit into
> Block Ram(s) ?

Not really.  It was a design originally implemented in custom CMOS in
the early 1980s, and I don't really want to redesign it any more than
necessary.  There are lots of don't cares scattered throughout the
AND matrix of the PLA, so it won't fit in any reasonable-sized ROM
or RAM.  Also, the 25-bit input words don't uniquely map to outputs;
a given input word may (and often does) match multiple product terms.

I've now tried putting a "keep" attribute on the product terms, and
that made the timing worse.  I thought it would result in better
(separate) optimization of the product terms and OR terms, rather
than mashing them together and trying to optimize the result.

By default, ISE *is* using the carry chain, and in fact it seems to
be using it for some 95-input gates, which end up being much slower
than an equivalent tree would be.  I'm doing a run now with the
"USE_CARRY_CHAIN" attribute set to "no" for all the sum terms.

I might try having hacking my Python tool that translates the PLA
so that it directly instantiates trees of four-input gates for all
of the product terms and sum terms, with a "keep" attribute on each
gate output, and see what kind of timing that gets me.  I think that
should result in the fewest possible levels of logic, which would
be around eight.

For the first attempt, I'll just brute-force it, so that none of
the terms have any shared sub-terms.  If the results look reasonable,
I'll try to optimize it for use of common sub-terms to reduce the
total number of LUTs, while keeping the levels constant.

Eric

Article: 97799
Subject: Why wouldn't this infer a flop with async reset and sync enable
From: "fpgabuilder" <fpgabuilder-news@yahoo.com>
Date: 27 Feb 2006 19:10:10 -0800
Links: << >>  << T >>  << A >>
Hi Folks,

Both Precision Synthesis and Altera Quartus 2.0 cannot infer flops with
async reset and enable in the following code.  I have checked that the
nclk and nrst_n are properly connected to the module.

What am I missing?

TIA,
Sanjay

-------

reg [23:0] irq_event_reg [0:1];

always@(posedge nclk or negedge nrst_n)
	begin : irq_event_reg_sync
		if(!nrst_n)
			begin
			irq_event_reg[0] <= 24'd0;
			irq_event_reg[1] <= 24'd0;
			end
		else
			begin
			irq_event_reg[0] <= nwd;
			irq_event_reg[1] <= irq_event_reg[0][23:0];
			end
	end

assign irq_event[23:0] = irq_event_reg[1][23:0];




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