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Messages from 97700

Article: 97700
Subject: Re: Combinatorial Division?
From: "Isaac Bosompem" <x86asm@gmail.com>
Date: 26 Feb 2006 09:41:06 -0800
Links: << >>  << T >>  << A >>

Philip Freidin wrote:
> On Sat, 25 Feb 2006 19:45:47 -0500, Josh Rosen <bjrosen@polybusPleaseDontSPAMme.com> wrote:
> >> t (and see if I remember correctly) in this PDF file:

> Another source of info on these multistep algorithms would be the AM29000
> RISC processor documentation, that had both multiply and divide step
> instructions.
>
> Philip Freidin

The SuperH series of CPU's also have a divide step instruction.


Article: 97701
Subject: Re: VGA specification
From: cs_posting@hotmail.com
Date: 26 Feb 2006 10:22:27 -0800
Links: << >>  << T >>  << A >>
Are you sure you actually want the VGA specification (pretty plain and
limited) or do you want the specs for what it evolved into?

Also, what are you looking for - timing, electrical, programming?


Article: 97702
Subject: Re: Virtex 4 Multiplier RPM Constraints?
From: "Love Singhal" <lovesinghal@gmail.com>
Date: 26 Feb 2006 10:27:14 -0800
Links: << >>  << T >>  << A >>
Hi,
Thanks for replying.
I want to design 32 bit to 64 bit multipliers, so I can not use just
one 18x18 bit XtremeDSP slice.

In my experiments, I am looking at how the shape of multipliers affect
their partial reconfiguration. This is when we do difference based
partial reconfiguration of the multiplier. If these multipliers do not
mix with other components and routing remains same, then when they are
reconfigured to new multiplier of same shape, lots of reconfiguration
bits can be saved.

Dsp slices based multiplier will be location-constrained which I do not
want, as I want the multiplier to be placed anywhere in the area.

I know that ISE 8.1 is now supporting module-based partial
reconfiguration using PlanAhead 8.1. But I am looking at saving the
reconfiguration bits inside the PRM part (which may internally consists
of multipliers and other components) of the design using
difference-based scheme.

Hence, I need to specify to Xilinx floorplanner to not to mix the logic
of multiplier with other logic. Is there a way to specify such
constraint in UCF file without explicitly specifying location
constraints?
For getting similar shapes of multiplier, I wanted to specify RPM
constraints for the multipliers but I could not do it for Virtex 4. So
I was curious if this is a known limitation.

Thanks,
Love Singhal
http://www.ics.uci.edu/~lsinghal


Article: 97703
Subject: Re: ERROR:MapLib:482
From: "John McGrath" <tails4e@gmail.com>
Date: 26 Feb 2006 10:32:13 -0800
Links: << >>  << T >>  << A >>
Are you inferring a memory in your user logic? maybe that is the ram
which is not being connected correctly, as your user logic may be
considered to be memory mapped. This is just a wild guess!


Article: 97704
Subject: Re: ERROR:MapLib:482
From: "Mich" <michiel.vanderlinden@gmail.com>
Date: 26 Feb 2006 10:34:53 -0800
Links: << >>  << T >>  << A >>
Hi again

can anyone tell me where and how I can connect the outputpins of BRAM
in XPS7.1

Thanks
Mich


Article: 97705
Subject: Coregen ISE 6.1
From: foag@iti.uni-luebeck.de
Date: 26 Feb 2006 10:45:34 -0800
Links: << >>  << T >>  << A >>
Hello,
after starting Coregen 6.1i, no IP core is sohwn although I have done
Get models under the Tools button.
Do I have to set another PATH variable or anything similar ?

Thanks for any ideas
J=FCrgen


Article: 97706
Subject: Re: V4 FIFO16 and SRAM
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Sun, 26 Feb 2006 10:47:32 -0800
Links: << >>  << T >>  << A >>
>          1   2   3
>          |   |   |
>       _   _   _   _   _   _   _   _
> rdclk / \_/ \_/ \_/ \_/ \_/ \_/ \_/
>      _____         ________________
> empty      \_______/
>                ___
> rden  _________/   \________________

This diagram is correct except for the fact that if your RDEN logic
comes from the EMPTY flag, then RDEN will be two pulses long
as well.  That could be trouble is you only have one datum.

By the way, how do you set up Outlook Express to give Courier
fonts? Whenever I get a diagram like this, I have to cut and paste
it into Notepad to see it.

Thanks,

Brad Smallridge
Ai Vision




Article: 97707
Subject: Re: ERROR:MapLib:482
From: "Mich" <michiel.vanderlinden@gmail.com>
Date: 26 Feb 2006 10:49:18 -0800
Links: << >>  << T >>  << A >>
I have made my project with the wizzard and there I have added 2
BRAM-controllers with BRAM on the PLB bus
thenI have used the importe/create wizzard to add an IP who is
master/slave on the PLB bus

When I want to download this there is no problem with the connections
of the BRAM
but when I change the IP there are bath connections

Do you know how this is possible and how I can fix this?

Greets
Mich


Article: 97708
Subject: Re: V4 FIFO16 and SRAM
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Sun, 26 Feb 2006 10:53:12 -0800
Links: << >>  << T >>  << A >>
>> My issue is that in my simulations I see the EMPTY go on for two RDCLKs,
>> whereas I have only written one datum into the FIFO16.

> Yes, I expected that, and, depending on the phase between read and
> write clocks, it might even be three.

How does three happen?  As far as I know, the effect I have described
depends only on the synchronous rising edge of EMPTY flag, so either
you don't understand what I'm trying to relate, or I don't understand some
other issue in the FIFO16 EMPTY flag behavior.

Brad Smallridge
Ai Vision



Article: 97709
Subject: Re: VGA specification
From: Jerry Coffin <jcoffin@taeus.com>
Date: Sun, 26 Feb 2006 12:06:26 -0700
Links: << >>  << T >>  << A >>
In article <1140961290.326814.5060
@j33g2000cwa.googlegroups.com>, me_2003@walla.co.il 
says...
> Hi all,
> Does any of you knows where can I obtain the VGA specification (I
> believes it is IBM's)  ?

For quite a while now, most video standards have been 
handled by VESA. To support plain-Jane VGA, they have a 
set of "fallback" timings to run a monitor at 640x480 or 
720x480 at:

http://www.vesa.org/Public/SMT/SMT640_720x480V1.pdf

If you want to support other resolutions, they have a 
spreadsheet at:

http://www.vesa.org/Public/CVT/CVTd6r1.xls

that allows you to enter resolution, refresh rate, etc., 
and it calculates timing parameters for you (and verifies 
whether what you're asking for will be supported by a 
typical display).

VESA has quite a few more standards as well, but without 
more information about what you're doing, it's hard to 
guess which would apply. You can look through the others 
starting from:

http://www.vesa.org/Public/

to find what applies to what you're doing.

-- 
    Later,
    Jerry.

The universe is a figment of its own imagination.

Article: 97710
Subject: Re: about Xilinx Chipscope
From: Mike Treseler <mike_treseler@comcast.net>
Date: Sun, 26 Feb 2006 11:06:40 -0800
Links: << >>  << T >>  << A >>
yyqonline wrote:

> I want to do a presentation about the introduction about Xilinx
> Chipscope on the meeting of my lab. Since I have used this software for
> not a long time, I need some comments, tips, and other information
> about Chipscope from you, the veteran designers of Fpga.
> Any advice would be appreciated very much.

I would suggest learning HDL simulation also.
Chipscope is a good troubleshooter in some cases,
but not a good regression tester.

          -- Mike Treseler

Article: 97711
Subject: Re: V4 FIFO16 and SRAM
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Sun, 26 Feb 2006 11:30:45 -0800
Links: << >>  << T >>  << A >>

>>My issue is that in my simulations I see the EMPTY go on for two RDCLKs,
>>whereas I have only written one datum into the FIFO16.
>
> That's a reasonably common problem with FIFOs.  There is a
> pipeline delay in deciding to read the FIFO and/or in updating
> the empty flag after you do the read.

Thanks, Hal.  You might be the only one that understood my question.

> You can probably patch your code to ignore the EMPTY flag until
> it has had time to get the right answer.  The disadvantage with
> that is that you can only read at half speed.  (Or slower if your
> pipeline is longer.)

I'm not following you. The EMPTY flag is actually working OK.
It's the extra cycle of geting the RDEN on that I suspect must be
worked on.  So I guess, because you mentioned pipeline, and I've
been thinking that an extra register needs to be added to the data
output, that there is some circuit that will be robust and will handle
one input data burst or multiple-input data burst.  Right now I can't
wrap my head around what that circuit might be.  If you can give me
any clues I would be most appreciative.

Presently, I am working on driving the RDEN with combinatorial
logic, directly from the two EMPTY flags to get it off faster. I
think this should work, since both EMPTY flags are synched to
the same RDCLK.  There seems to be some flickers, though, on
the output.

Brad Smallridge
Ai Vision



Article: 97712
Subject: Re: V4 FIFO16 and SRAM
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 26 Feb 2006 11:42:08 -0800
Links: << >>  << T >>  << A >>

Brad Smallridge wrote:
>  so either
> you don't understand what I'm trying to relate, or I don't understand some
> other issue in the FIFO16 EMPTY flag behavior.
>
Brad, I really do not understand what you are doing with the FIFOs.
I was just (poorly) describing the naturally synchronous rising edge of
EMPTY, and its artificially re-synchronized trailing edge. That's all
in the inards of FIFO16.
I know the FIFO16 inside out (and have designed FIFOs over the past 30
years), so I should be able to understand what you do. But I don't.
Send me an e-mail or call me at work, and we can get to the bottom of
it. Then I can also explain in detail what Ray was referring to.
Peter


Article: 97713
Subject: Re: V4 FIFO16 and SRAM
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Sun, 26 Feb 2006 11:48:22 -0800
Links: << >>  << T >>  << A >>

Thanks Ray,

> The Virtex4 FIFO16 flag logic has a design flaw that renders them 
> unreliable for asynch operation.

I was aware of this issue.  However I thought that I was "safe" since I am 
not using the ALMOSTEMPTY flag, nor should the two FIFO16s ever be in a 
situation where the ALMOSTEMPTY flag would ever be in transition. It should 
always be on. My circuit is fairly straightforward, as soon as the EMPTY 
flag comes on, address information is passed from the FIFO output to the 
SRAM address lines.  There are two FIFOs competing for the address lines 
with one FIFO having priority for the situation when both EMPTY flags come 
on at the same time.  The data is spread out so presently I would never 
expect to see more than one data in either FIFO at any time.

Since the ALMOSTEMPTY flag is always on, I was hoping that it's metastable 
effect on the EMPTY flag was circumvented.  I guess that's a question for 
Xilinx to answer.

> You can, however use it synchronously and cascade it with a small async 
> coregen fifo implemented in the fabric so that the net effect is an async 
> fifo.

And the coregen fifo is OK?

Brad Smallridge
Ai Vision




Article: 97714
Subject: Re: Virtex 4 Multiplier RPM Constraints?
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 26 Feb 2006 11:50:48 -0800
Links: << >>  << T >>  << A >>
Interesting...
You know of course that 32 x 32 bits generates 1024 partial products,
and 64 x 64 generates 4096 partial products that have to be added
together. Looks like a formidable (and inevitably slow) job to me,
unless you somehow do this sequentially. In which case you could use
the 18 x 19 multipliers as building blocks. Is one of your factors a
constant?
You somehow lost me. I don't think I can help.
Peter


Article: 97715
Subject: Re: VGA specification
From: cs_posting@hotmail.com
Date: 26 Feb 2006 12:02:41 -0800
Links: << >>  << T >>  << A >>
Jerry Coffin wrote:

> VESA has quite a few more standards as well, but without
> more information about what you're doing, it's hard to
> guess which would apply.

Yes, knowing the application is the key.

Depending on what you need to do, you can treat a VGA monitor is either
an analog, or a nearly digital device.

For just getting something on monitor, several of the FPGA intro boards
(spartan 3 kit, etc) have VGA connectors and sample projects that
demonstrate a state machine producing the timings.  These typicall
drive the sync signals directly with LVCMOS outputs and the three color
lines either through a single resistor (270 ohms on the s3kit) or a
2-bit resistor ladder dac per channel, to give a few more digital
colors.  A real DAC gives even more.

Trying to use an FPGA to make a "VGA card" for a pc would be a more
complicated project, in which case a lot of the register-level detail
of the basic VGA card would need to be known.


Article: 97716
Subject: Re: C Manual for Microblaze Software
From: "Karel" <karel@gemidis.be>
Date: Sun, 26 Feb 2006 14:11:54 -0600
Links: << >>  << T >>  << A >>
>I should develop a program for my embedded system based on microblaze.
>
>Where I can find a good manual with also Xilinx types?
>
>Thanks Marco
>

Marco,

you can find a good and short manual about C programming on
(based on embedded programming)

http://www.ece.utexas.edu/~valvano/embed/toc1.htm

Regards

Karel

Article: 97717
Subject: Re: V4 FIFO16 and SRAM
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 26 Feb 2006 12:13:34 -0800
Links: << >>  << T >>  << A >>
Brad
If you program the ALMOST EMPTY flag to a high enough offset above
EMPTY, such that ALMOST EMPTY never (never!) gets deactivated, then the
FIFO16 will always operate perfectly, and you can ignore all
work-arounds. Absolutely, no question...

The problem with the ALMOST flags has nothing to do with metastability,
(we understand that pretty well, and would not be fooled by that), but
is caused by simultaneous read and write clock edges. It's a simple
logic error, hidden and covered up in a piece of "hard logic".

Regarding EMPTY, you must understand that it is obviously started by
the read clock, obviously terminated by the write clock, but then
internally re-synchronized to the read clock. That's where the
ambiguities come from.
Peter


Article: 97718
Subject: Re: fpga to 5v ttl logic
From: Jim Granville <no.spam@designtools.co.nz>
Date: Mon, 27 Feb 2006 09:18:08 +1300
Links: << >>  << T >>  << A >>
cs_posting@hotmail.com wrote:
> Jim Granville wrote:
> 
> 
>>Sorry Peter, but much as the FPGA sector wants 5V to go away,
>>it's still here. In fact, the newest devices from Infineon and Freescale
>>have 5V ports !
> 
> <snip>
> 
>>Why ? - noise immunity, ease of interface : have you ever tried to
>>find a power MOSFET that can be driven from 3.3V ?
> 
> 
> If building in 5v tolerance for that reason, why not build for say 9
> volt or 15 volt?

  4000 series logic had higher voltage operation, and is still widely used.
  We still use 4000 series gates in new designs, but choose to operate 
at 5V, not higher.

  One of the driving forces :) in the 5V standard is Automotive.
Here, 9 and 15V regulated rails are clearly too high, as the
canking voltage would cause dropout.

> 
> Even 5v gate drive is marginal for power MOSFETs, in that it's only
> enough for some parts.

A strange argument for removing it, if that is what you are saying ?

  There are a raft of TTL compatible MOSFET driver chips, typically SO8,
if you really need 10V drive - but a large portion of MOSFETS in use
are for relay/Solenoid/Small motor control, where 5V gate drive is fine.
  Last time I checked, it was really only the "final milliohm" that
needed 10V gate drive -
  eg a Philips PH2625L is 4.5 milliOhms at 4.5V Vgs, and 2.7 MilliOhms
at 10V Vgs

  White and Blue LEDS are another common (and growing) load, that
struggles with 3.3V and lower supply rails.

  You CAN get 3.3V relays (I have a design now that will use 3V relays)
but they are not common, and restricted to smaller models.

-jg


Article: 97719
Subject: Re: fpga to 5v ttl logic
From: fpga_toys@yahoo.com
Date: 26 Feb 2006 13:12:28 -0800
Links: << >>  << T >>  << A >>

Peter Alfke wrote:

> But the high Vcc and thick oxide in the I/O circuits severely reduces
> their speed. And we see far more of our customers clamoring for high
> performance than for 5-V compatibility.

It's a relatively small market comparted to new designs, but 5V legacy
designs in the field will be around for another decade or so, where
speed
has never been the issue.

The original posters history shows interest in Apple II development,
and
may be hobby only. On the other hand, there remains 5V industrial
development around ISA and PC104, which isn't likely to go completely
3.3V for a while.


Article: 97720
Subject: Re: fpga to 5v ttl logic
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 26 Feb 2006 13:37:22 -0800
Links: << >>  << T >>  << A >>
All engineering decisions, and also all business decisions are a
trade-off between conflicting goals and requirements.
While the two big gorillas in FPGA-land emphasize performance, density,
and low cost, perhaps the little guys (used to be affectionally called
the "seven dwarfs" but they are fewer than seven now) can populate the
niches left empty by the big guys. Might be their one chance...
Peter Alfke


Article: 97721
Subject: Re: realize pci in fpga
From: Thomas Rudloff <thomasREMOVE_rudloffREMOVE@gmx.net>
Date: Sun, 26 Feb 2006 22:54:20 +0100
Links: << >>  << T >>  << A >>
eehinjor wrote:
> Thank you for your response so soon.
> 250ps is about 3inches,but the length of clk can not be longer than
> 2.5+0.1inches.
> how can that meet the spec?
> 

There is _no_ 250ps delay! The switch is equal to a 5Ohm resistor what 
computes with 50pF load to a tau of 250ps. I do not know Altera parts in 
detail but assume aprox 5pF on a dedicated clock input. Maybe 7pF.

So you are at 25ps to 35ps.

Be aware that your I/Os have more capacitive load than a dedicated input 
and make sure that these do not violate their length.

Article: 97722
Subject: Re: Combinatorial Division?
From: "logjam" <grant@cmosxray.com>
Date: 26 Feb 2006 14:43:57 -0800
Links: << >>  << T >>  << A >>
fpga_toys@yahoo.com wrote:
> logjam wrote:
> > I want to do all sorts of things.  After this I want to build an 8bit
> > computer using transistors.  I saw one on the internet, but it didn't
> > look like it ran any decent software.
>
> Way to go :)  Excellent way to gain grounding experience, as nobody
> will pay you to build one today!!  The oldie moldies here are likely to
> enjoy gabbing about the past too.

Thats right.  I've learned a lot about microcode and processor
instruction sets from trying to design my own ALU.  For example, a
compare instruction is usually a subtract without store.

Probably the coolest thing I've done yet is add FFFFFFFFFFFFFFFF to 0,
apply the carry input, and watch the Altera simulator propagate the
carries.  :)

One thing I have that 1975 didn't, is a P4 3.2GHz PCB autorouter, and a
way to test the design to pretty much guarantee it will work. :)

> My home project has been taking a few thousand older FPGA's to build a
> home super computer into a desktop sized box (with water cooling, and a
> lot of memory, fibre channel disks, etc) .... :)  It takes a lot of
> current too .... a few thousand amps for even a "small" super computer.

That sounds very interesting.  Do you have a project web page journal
or anything like that?

An interesting thing to think about...how long do you think it will be
before through hole devices are discontinued?  What will the electronic
hobby look like?  Computer programming classes today are in Java and
visual basic.  I don't think the local university even has C.

One last note, I live in Alaska.  Its cold and snowing right now.  What
elese am I supposed to do?  :)


Article: 97723
Subject: Re: Combinatorial Division?
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 26 Feb 2006 15:08:43 -0800
Links: << >>  << T >>  << A >>

logjam wrote:
> > An interesting thing to think about...how long do you think it will be
> before through hole devices are discontinued?

For high-pincount and/or high-performance circuits, through-hole has
been dead for more than a decade.
Through-hole means 100 mi (~2.5 mm) pin spacing, which becomes hopeless
above 200 pins.
Add to that the bondwire and lead-frame inductance, and it just cannot
support today's top requirements of speed and signal integrity.
The trend is to flip-chip, bonding the chip surface directly to the
package, without any bondwires.
That then also means ball grid arrays, and is great for professional
assembly, but a killer for the hobbyist.
I am really feeling sorry for this, for I grew up designing and
soldering (ham) radio gear. The combined smell of hot solder and burned
fingertips is still in my nose. But it is not for the future.
Just like carburetors, generators, breaker points and grease nipples on
cars. 
Fond memories, some not so fond...
Peter Alfke


Article: 97724
Subject: Re: Combinatorial Division?
From: "Isaac Bosompem" <x86asm@gmail.com>
Date: 26 Feb 2006 15:33:20 -0800
Links: << >>  << T >>  << A >>

logjam wrote:
> fpga_toys@yahoo.com wrote:
> > logjam wrote:
> > > I want to do all sorts of things.  After this I want to build an 8bit
> > > computer using transistors.  I saw one on the internet, but it didn't
> > > look like it ran any decent software.
> >
> > Way to go :)  Excellent way to gain grounding experience, as nobody
> > will pay you to build one today!!  The oldie moldies here are likely to
> > enjoy gabbing about the past too.
>
> Thats right.  I've learned a lot about microcode and processor
> instruction sets from trying to design my own ALU.  For example, a
> compare instruction is usually a subtract without store.
>
> Probably the coolest thing I've done yet is add FFFFFFFFFFFFFFFF to 0,
> apply the carry input, and watch the Altera simulator propagate the
> carries.  :)
>
> One thing I have that 1975 didn't, is a P4 3.2GHz PCB autorouter, and a
> way to test the design to pretty much guarantee it will work. :)
>
> > My home project has been taking a few thousand older FPGA's to build a
> > home super computer into a desktop sized box (with water cooling, and a
> > lot of memory, fibre channel disks, etc) .... :)  It takes a lot of
> > current too .... a few thousand amps for even a "small" super computer.
>
> That sounds very interesting.  Do you have a project web page journal
> or anything like that?
>
> An interesting thing to think about...how long do you think it will be
> before through hole devices are discontinued?  What will the electronic
> hobby look like?  Computer programming classes today are in Java and
> visual basic.  I don't think the local university even has C.
>
> One last note, I live in Alaska.  Its cold and snowing right now.  What
> elese am I supposed to do?  :)

I read a site somewhere that had a couple of students build a full
32-bit CPU out of standard 74 parts. Obviously it was a huge power
guzzler but it worked nonetheless!

For myself, I hand-built a Z80 SBC about 2 yrs ago, it still works
today :) :
I clocked the CPU @ 2.45Mhz (same clock into USART), have 2KB of flash
and 32KB of RAM and a single 8-bit output port. It is a nice
development system. I wrote some IEEE754 FP library in Z80 assembly. It
was relatively painless since I am fairly comfortable with the x86 and
scores other CPU's instruction set.

I just dont have the cash to purchase all the TTL components to do it
your way (broke student syndrome, it is well documented :) ). But I did
design a 16-bit CPU in VHDL and used the 200K gate Spartan3 to
implement it, it is working fine too, just tested it last night in the
FPGA. The thing is that the CPU I designed is relatively complex (its
ISA definitely has some CISC elements to it) and only took about 30-40%
of the space in my FPGA. So I have a TON of space to implement
peripherals and the like. I plan on writing an assembler and C compiler
for it. I definitely need to learn how those work.
Also I used BlockRAM to implement the registers (banked) and the stack
space so I took a speed hit (in terms of clks/instruction), but that is
no problem, it was my first CPU design. Also let me make it clear that
I DO NOT work for Xilinx. The Spartan3 devkit I bought was very
affordable, I am very happy with the amount of features you get for the
price.

Forge on, and show us pics, lots of juicy pics :)




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Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

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