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"Peter Alfke" <alfke@sbcglobal.net> wrote in message news:1135982584.857664.176920@g43g2000cwa.googlegroups.com... > > Why all this commotion? > It does not take a genius to interpret the graph: > > Dynamic power is very similar for the two competing devices, although > Xilinx has still an edge, even after the Altera improvements. On this one design selected by Xilinx marketing, your graph shows similar dynamic power between Stratix II and Virtex4. See http://www.altera.com/products/devices/cyclone2/features/power/cy2-power-compare.html for power results across a large suite of designs. Hardware measurements over designs of various types show that Stratix II has lower dynamic power on 80% of the designs, with *Quartus 5.0*. Quartus 5.1 reduces dynamic power by an average of 20% when you turn on extra effort power-driven compilation, and have a testbench, so that further widens the advantage here. See http://www.altera.com/education/net_seminars/all/ns-power-optimize.html for a netseminar detailing the power optimization features in Quartus 5.1, and a dynamic power comparison between Stratix II and Virtex4 using Quartus 5.1. Hardware measurments in the white paper listed above also show Stratix II has lower I/O power than Virtex4. Virtex4 has lower static power, but the advantage here is not huge, once you include the significant Vccaux power that Xilinx marketing literature neglects, and use worst-case process static power numbers. Since total power is the sum of these three components, there is a variation in which device has the lower total power depending on your device utilization and clock frequency. At moderate to high utilization, and the clock frequencies typical for a 90 nm FPGA, Stratix II generally has lower total power. At sufficiently low clock frequencies and low device utilization, Virtex4 will have lower total power. All of these hardware measurments can be reproduced at the customer site with a board that has both a Stratix II and Virtex4 device on it, with identical board design parameters for both. The source code for the designs can be inspected by the customers to ensure we aren't biasing the results to favour Stratix II. Contact your FAE if you'd like a demo -- so far we haven't had any customer who hasn't found the demo both fair and compelling. > The dramatic (>2:1) difference is in static power consumption, which of > course is ugliest at 85 degrees. Here Xilinx benefits from its use of > three different gate oxide thicknesses (Altera uses only two). > And, to camouflage their weakness, Altera conveniently published those > meaningless 25 degree total power numbers. The white paper above, and all data on Stratix II and Cyclone II power at http://www.altera.com/products/devices/stratix2/features/st2-power.html and http://www.altera.com/products/devices/cyclone2/features/power/cy2-power.html respectively, compare static power at 85 C, worst-case process. It is totally unclear how the white paper you reference computes static power. It appears to be a single-unit measurement at 25 C, scaled using an unknown methodology to 85 C. I also suspect that once again it does not include Vccaux static power for Virtex4, since the graph shows the V4 unit measured as having ~600 mW of static power, while the Virtex4 web power tool shows that typical static power for Virtex4 (including Vccaux) is 868 mW, and worst-case is 1.53 W. > That's what I mean by Marketing BS, for most devices in the Virtex-4 or > Stratix-II class are operated at high clock rates, which makes them run > hot, close to and sometimes even above 85 degrees. To brag about > allegedly low power at 25 degrees misses the point, is Marketing BS. As I stated above, all the Altera power comparisons include and highlight the 85 C, worst-case silicon static power comparison. The Xilinx white paper, by comparison, uses an unknown methodology to compute static power, and produces a number that is below both the typical and worst-case specification for Virtex4. I'll let the readers of the newsgroup decide which comparison has more engineering validity. Vaughn Betz Altera [v b e t z (at) altera.com]Article: 93901
Hi,
Does anyone happen to know what will the following (software) code will look
like after going through a synthesis tool? I was told, back in the school,
that never use *HDL as a software language and should have a block diagram or
data path before coding. But it seams that more and more people trust the
synthesis tool rather.
// Verilog version
reg [5:0] offset; // input
reg [15:0] we; // input
reg [15:0] data_in[127:0]; // input
reg [7:0] data_out [63:0]; // output
wire [5:0] offset0; // internal logic
wire [5:0] offset1; // internal logic
...
wire [5:0] offset15; // internal logic
assign offset0 = offset;
assign offset1 = offset + 1;
...
assign offset15 = offset + 15;
always @ (posedge clk) begin
if (reset) begin
// initial code here
...
end begin
if (we[0]) data[offset0] <= data_in[7:0];
if (we[1]) data[offset1] <= data_in[15:8];
...
if (we[15]) data[offset15] <= data_in[127:120];
end
end
-- VHDL version
type data_type is array (63 downto 0) of std_logic_vector(7 downto 0);
signal offset : std_logic_vector(5 downto 0); -- input
signal we : std_logic_vector (15 downto 0); -- input
signal data_in : std_logic_vector (127 downto 0); -- input
signal data_out : data_type; -- output
signal offset0 : std_logic_vector(5 downto 0); -- internal logic
signal offset1 : std_logic_vector(5 downto 0); -- internal logic
...
signal offset15 : std_logic_vector(5 downto 0); -- internal logic
offset0 <= offset;
offset1 <= offset + 1;
...
offset15 <= offset + 15;
process (clk, reset)
if rising_edge(clk) then
if (reset = '1') then
-- initial code here
...
else
if (we(0)='1') then data(offset0) <= data_in(7 downto 0); end if;
if (we(1)='1') then data(offset0) <= data_in(15 downto 8); end if;
...
if (we(15)='1') then data(offset0) <= data_in(127 downto 120); end if;
end if;
end if;
end process;
If I was to implement the above circuit, I will not write the above codes. I
will first draw a data path diagram which show me that I can have have a
barrel shifter to map the 16-bit 'we' to 64-bit 'data_we' based on the
'offset' input. Than I will use another shifter to "expand" the data and
assign each of the 64 slots based on the 'data_we'. I may even write a simple
Perl script to generate this 64 statement.
Does anyone know any better implementation scheme or any synthesis tools that
will generate a better result base on the above code? I tried Xilinx XST and
the above code failed (out of memory ?!) I know some other synthesis tool can
generated a valid circuit with terrible performance.
The most important question is, "Should I worry about this?" Someone told me
that the code failed to compile just because XST is not good enough. But I
wonder. My teammates and me have a different point of view in CAD tools. They
believe the logic optimization (e.g. from behavioral description to netlist)
and don't trust the physical optimization (e.g. they do hand placement and
timing on every net). I believe the opposite.
There are too many *information* available when running the placement and
routing process which is NOT suitable for a human brain. But the tools can
handle this well. There some *knowledge* in the design which is hard to be
captured in the tools. And we engineerings are trained to use this knowledge
to optimize our design. So I believe that we should code more careful rather
than pumping constraints to the tools.
But the current trend is (at least observed by myself), to encourages users
code more like in a software environment. Is this the design flow for tomorrow
or I misunderstand something?
--
Regards,
Tsoi Kuen Hung (Brittle)
CSE CUHK
Article: 93902"Austin Lesea" <austin@xilinx.com> wrote in message news:dov29l$h854@xco-news.xilinx.com... > Recently posted on our website: > > http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex4/resources/Virtex-4_Power_Case_Study.pdf > > Is a case study in which the latest claims of power savings by the > competitor's software are debunked. > > I had intended to post this as part of the earlier thread, but I couldn't > find the link to the above white paper. > > If you ignore the superiority of Virtex 4, and just concentrate on the > improvement in power from the tool, going from ~ 2.8 watts to ~ 2.6 watts, > or an improvement of 200 mW, is roughly an improvement of 7% less power. The power optimization features in Quartus II 5.1 target dynamic power. The reduction in dynamic power shown on your graph is 19%, which is definitely of interest to most of our customers. The white paper above does not appear to have included a testbench for the Quartus II compilation -- that reduces the effectiveness of power-driven compilation somewhat. So with a testbench, I would expect some further power reduction. As this design is relatively small (~40% logic utilization, less than 20% overall RAM utilization for Stratix II), the dynamic power consumed is lower than typical. Customer designs are almost always more full than this, and often operate at clock frequencies above 200 MHz. In such cases dynamic power obviously goes up, while static power doesn't, so dynamic power becomes a larger part of total power and you would see more than the 7% total power reduction seen here. > Or should one say that Virtex 4 uses so much less power, that talking > about how much is 'saved' by the software tool is just a distraction to > fool the unwary? See my reply to Peter later in this thread for a complete summary of the competitive power picture between Stratix II and Virtex4, and an analysis of the weaknesses of this white paper. Vaughn Betz Altera [v b e t z (at) altera.com]Article: 93903
You can make the design fit. Change your BlockRAMs to use x18 width instead of x36. The multipliers can share the resources with a BlockRAM unless the BlockRAM uses the wide 36-bit bus. Since you're only using 4 BlockRAMs, it would be easy from a resource perspective to use half of 8 BlockRAMs at 18-bit width to give you the same memory sizes you have now. You may be able to reoptimize for 18-bit width and use just 4 of the BlockRAM and avoid the troubles altogether. Another thought might be to access the BlockRAMs at twice the base clock speed to provide 36-bit operation over 2 18-bit cycles making it look to the system like it's a 36-bit BlockRAM at the normal clock rate. This approach is more complex but often the BlockRAMs aren't pushed to their maximum speed and time-multiplexing produces cleaner resource usage. Casio wrote: > When I try to generate a programming file for my FPGA project I get the > following error: > > > > > > ERROR:Place:419 - The design contains 4 BRAM components that are configured > as > > 512x36 BRAMs and 9 multiplier components. The multiplier site adjacent to > the > > location of a 512x36 BRAM component must remain free because of ressource > > sharing. Therefore a device must have at least 13 multiplier sites for > this > > design to fit. The currently chosen device has only 12 multiplier sites. > Phase 1.1 (Checksum:98d993) REAL time: 3 secs > > > > > > I use XILINX ISE 6.3.03i. Is there a way to make my design fit inside the > FPGA without reducing the number of multipliers?Article: 93904
You must do timing simulation,also if you don't add the timing constraints,this will mostly result in problem!Article: 93905
"drg" <drgenio@gmail.com> wrote in message news:1136132274.589797.17970@f14g2000cwb.googlegroups.com... > yes, that's my problem, the maths. I'm still in college (systems > engineering), but I have yet to learn all that advanced math to > understand even the most basic DSP text. These are all full of huge > formulas and complex numbers... I'm not trying to sound lazy but I > don't think it has to be that complicated. > Hi Hernan, Maybe you should stop using your time on your Spectrum Analyser project and spend it learning the maths? Just a thought? ;-) Cheers, Syms.Article: 93906
bill wrote: > > Is the signal cnt always initiated to "00000000" at start up (or some random > value)? Or do I have to include a reset signal? What is best, an a > asynchronous reset or a synchronous reset? > The best is to have an asynchronous reset that is released synchronous. This works even if the clock is not running. Eg with a broken crystal. There are app notes how to do this. Basicly it is a shift register stage resetted asynchronously with an inactive signal at the data input. After release of reset the inactive reset will clock towards the output. With this you can even build up a tree for large FPGAs to prevent slowing down clock rate because of large routes.Article: 93907
<ALuPin@web.de> schrieb im Newsbeitrag news:1136294247.789067.18020@g14g2000cwa.googlegroups.com... >Did you set the "Clock Mode Register" corresponding to your >single-edge/dual edge clocking ? And the "DVI PLL Filter Register" >corresponding to your frequency ? > >Rgds >André Hi Andre, that was it! I should really to the RTFM thing more often, I had looked at those regs but they had 'use default' value for them so I assumed they have some good default at powerup but they dont - thats actually written in the datasheet as well so after writing the proper defaults the DVI TFT monitor did come alive, no issues! Thank you! AnttiArticle: 93908
Thank you very much, it solved my problem. I had a RAM entity that was 50 bits wide and a total of 64 words. Now I split the 50-bit words into 18, 18 and 14 bits. Thanks :-) "John_H" <johnhandwork@mail.com> wrote in message news:32wuf.16$Pe6.10@trnddc08... > You can make the design fit. > > Change your BlockRAMs to use x18 width instead of x36. The multipliers > can share the resources with a BlockRAM unless the BlockRAM uses the > wide 36-bit bus. Since you're only using 4 BlockRAMs, it would be easy > from a resource perspective to use half of 8 BlockRAMs at 18-bit width > to give you the same memory sizes you have now. You may be able to > reoptimize for 18-bit width and use just 4 of the BlockRAM and avoid the > troubles altogether. > > Another thought might be to access the BlockRAMs at twice the base clock > speed to provide 36-bit operation over 2 18-bit cycles making it look to > the system like it's a 36-bit BlockRAM at the normal clock rate. This > approach is more complex but often the BlockRAMs aren't pushed to their > maximum speed and time-multiplexing produces cleaner resource usage. > > > Casio wrote: > > When I try to generate a programming file for my FPGA project I get the > > following error: > > > > > > > > > > > > ERROR:Place:419 - The design contains 4 BRAM components that are configured > > as > > > > 512x36 BRAMs and 9 multiplier components. The multiplier site adjacent to > > the > > > > location of a 512x36 BRAM component must remain free because of ressource > > > > sharing. Therefore a device must have at least 13 multiplier sites for > > this > > > > design to fit. The currently chosen device has only 12 multiplier sites. > > Phase 1.1 (Checksum:98d993) REAL time: 3 secs > > > > > > > > > > > > I use XILINX ISE 6.3.03i. Is there a way to make my design fit inside the > > FPGA without reducing the number of multipliers?Article: 93909
Urban, The CLKDV output of the DCM provides a divided version output of the clock going in. DV values of up to 15 are possible. So, for 4 MHz out, you could have 60 MHz in (and divide by 15). Or, 4 MHz out, 40 MHz in, DV=10, and so on. Austin u_stadler@yahoo.de wrote: > hi > > I have a question: what is the proper way to generate c slow clock. I > have a spartan 3 development board with a 50 MHz external clock. What i > need is a 4MHz clock for an SPI interface. Since the DCM's can only > deliver 18 MHz output with the frequency synthesiser (CLKFX) I need to > devide this clock some more. how is this done properly? a counter? Or > is ther any other sollution? > > Thanks > Urban >Article: 93910
Just a comment: And the latest quote we have is for less than $10,000 you can have the key value. Non-volatile fuses are nice, but be aware that they represent not much real security. Rather, they are a deterrent, as you have to destroy a device to obtain the key. However, once destroyed, the eprom is still intact, and not you have the bitstream (for all the good that will do you). AustinArticle: 93911
Unfortunately we in europe are not able to play with the kit... I assume guys at Xilinx think there are not enough potential customers there :-((Article: 93912
Thomas Rudloff wrote: > The best is to have an asynchronous reset that is released synchronous. > This works even if the clock is not running. Eg with a broken crystal. > There are app notes how to do this. Basicly it is a shift register > stage resetted asynchronously with an inactive signal at the data input. > After release of reset the inactive reset will clock towards the output. > With this you can even build up a tree for large FPGAs to prevent > slowing down clock rate because of large routes. Actually, with Xilinx FPGA's you are better off using a strictly synchronous reset, and only on the flip-flops that need it. If you need the behavior of an async reset, meaning the pins all go to a safe state, pull the program pin low. That immediately puts the FPGA into the programming state, which will look like it has been reset.Article: 93913
"Austin Lesea" <austin@xilinx.com> schrieb im Newsbeitrag news:dpe7mv$2pi3@xco-news.xilinx.com... > Just a comment: > > And the latest quote we have is for less than $10,000 you can have the key > value. > > Non-volatile fuses are nice, but be aware that they represent not much > real security. Rather, they are a deterrent, as you have to destroy a > device to obtain the key. > > However, once destroyed, the eprom is still intact, and not you have the > bitstream (for all the good that will do you). > > Austin > WAU! Xilinx is collecting quotes how to crack Stratix security ;) amazing what 10,000$ can do! either the guys quoting that are bullshitting or then the Altera has obvious design issues implementing the key storage I think Coolrunner-II claims for special security featueres, interesting what did those same guys quote for breaking it? Ok, that is full config readback so more bits to collect. Even though it should be possible to hide the nonvolatile key accross the die in a way that 10,000$ is not sufficent to crack it. For heavens sake - 10,000 is just a little more then price of one single Stratix device!! (online price for one piece the largest is about 8000 USD) interesting... AnttiArticle: 93914
"Ralph" <ralphw69@gmail.com> schrieb im Newsbeitrag news:ee93669.0@webx.sUN8CHnE... > Unfortunately we in europe are not able to play with the kit... > > I assume guys at Xilinx think there are not enough potential customers > there :-(( Well give them a few days, the new year has just begun, I feel hard to belive that the Sample Pack boards will not be available in Europe at all. So wait for the next week and starting asking your distributor and FAE if they can arrange the Sample Pack for you. AnttiArticle: 93915
Hi Weng, What have you been smoking over the New-Year :-) Thanks for your kind words but this is totally unjustified. The core is like any free core on the web, "hacked" together during virtual free time and in my opinion not particular special. But I do appreciate your comments, thanks! Regards, Hans www.ht-lab.com PS Thanks Antti for your time and effort on this. <wtxwtx@gmail.com> wrote in message news:1136243041.134288.208780@g44g2000cwa.googlegroups.com... > Hi Antti, > There is popular saying in China that if you visited the U.S., but have > never been in Las Vegas, you would be counted as one who has not > visited the U.S. Because Las Vegas is its crown. I have never been in > Las Vegas, but no sorry for it. > > I would like to say if you want to be a real ASIC/FPGA engineer, you > must read CPU86. Because it is the Bible in ASIC. It is the birth place > of full CPU industry. > > Thank you, Antti, for the excellent gift for new 2006. > > Weng >Article: 93916
Isaac Newton said something like "If I can see further than other people it is because I am standing on giants' shoulders." LeonArticle: 93917
Antti, It isn't rocket science: the keys may be read back by observing them under polarized light. There is an IEEE paper that describes the technique. If there is further obscurity in their placement, use, logic, all that means is that it takes more time (and money) to break. Certainly not an issue for any large company. Altera has yet to publish exactly how their efuse system works: evidently its use is covered by NDA. So no one who has knowledge of how it is programmed, or tested, is allowed to discuss it. And, to their credit, everyone who has signed the NDA has been honest, as we have no details on it at all (other than what is available on line). Great. Violates the first rule: "there is no security in obscurity." "The key is under the mat. That I have placed it there is a secret." So, until they publish the details, I suggest that for anyone interested in serious (or even moderate) security to just keep looking. I am not saying that efuses are a bad thing: they are very good. And, if they just said "here is how you program them, and here is how they are used, and this is the level of security provided" then I think that is very fair. Let the customer decide once they have all the facts. Efuse does not meet the US federal governement standard (FIPS-41), and that for those who are really serious about security, that 'pesky' battery backed key just can't be beaten (you know, the one that lasts more than 25 years on a $1.50 lithium coin cell...). And, Antti, here in Silicon Valley there are at least a half dozen labs out there who do failure analysis work. In fact, almost every semi company (fabless or not), has their own inspection equipment capable of reading these fuses. I know we do. Reading the fuses after they are blown is required for failure analysis, and yield analysis work. So anyone making these chips, knows how they work, and how to see if the fuses are blown properly. Now that the foundries offer this as a standard cell, it is pretty common. AustinArticle: 93918
"Leon" <leon_heller@hotmail.com> wrote in message news:1136307397.832406.161240@g14g2000cwa.googlegroups.com... > Isaac Newton said something like "If I can see further than other > people it is because I am standing on giants' shoulders." > > Leon > Hi Leon, I think you're right, but apparently Newton wasn't the first to say it. Check out :- http://en.wikipedia.org/wiki/On_the_shoulders_of_giants One should remember that the quote from Newton was written in a letter to Robert Hooke. Newton and Hooke didn't see eye to eye. Hooke was of short stature! Cheers, Syms.Article: 93919
drg wrote: > yes, that's my problem, the maths. I'm still in college (systems > engineering), but I have yet to learn all that advanced math to > understand even the most basic DSP text. These are all full of huge > formulas and complex numbers... I'm not trying to sound lazy but I > don't think it has to be that complicated. > > I just need a routine, and to learn how to use it (I seem to have found > it at opencores > (http://www.opencores.org/projects.cgi/web/biquad/overview) along with > DSPlay to generate the coefficients. > > Regards, > hjf > All of the folks that I've ever met with the title "systems engineer" are people who are very good at math* _and_ at applying it to the real world. I'm not sure what systems engineering one could do without that capability. * Regrettably the 's' fell overboard somewhere in the Atlantic. -- Tim Wescott Wescott Design Services http://www.wescottdesign.comArticle: 93920
Antti, We made a whole bunch of them. I know because the Spartan folks were all excited and running around giving them to selected folks here in San Jose. I expect it is like the snake swallowing the elephant: there is a big bump of boards working their way through the system! As an aside, I had my 15 month old twin grandchildren from Scottsdale over for the Christmas holidays (with their parents). The twins certainly were too young for the Spartan 3E sample pack, but they were fascinated with anything with blinking lights, sounds, and buttons. In fact the little boy (they are fraternal twins), was 'helping' me conduct an emergency services net during the height of the downpours we had (I volunteer for Santa Cruz County ARES, which supports the Red Cross, County Sheriff, and County OES). He sat with me as I kept track of things over the radios... Oh, and they liked chasing the cats. Austin Antti Lukats wrote: > "Ralph" <ralphw69@gmail.com> schrieb im Newsbeitrag > news:ee93669.0@webx.sUN8CHnE... > >>Unfortunately we in europe are not able to play with the kit... >> >>I assume guys at Xilinx think there are not enough potential customers >>there :-(( > > > Well give them a few days, the new year has just begun, I feel hard to > belive that the Sample Pack > boards will not be available in Europe at all. So wait for the next week and > starting asking your > distributor and FAE if they can arrange the Sample Pack for you. > > Antti > >Article: 93921
Comment: If I had been able to use MatLab, MatchCad, or Mathematica when I was in school, I would be even further along than I am today. With these math tools avaialble, get one, and master it. The idea of hand cranking any of the DSP math is so paiful (I did it!) that now I can not even imagine doing it by hand today. You learn the concepts, and the theory faster if you have something that allows you to get through the math bits. As a good friend of mine once said "the faster I can make mistakes, the fatser I can learn." With a good math program, you can make mistakes faster than ever. And the development of the DSP code is now aligned with the math simulation tools: http://www.xilinx.com/products/software/sysgen/mathworks_system.htm so you can not only see if your maths are working, but then download it, and see if it works in reality! Austin Tim Wescott wrote: > drg wrote: > >> yes, that's my problem, the maths. I'm still in college (systems >> engineering), but I have yet to learn all that advanced math to >> understand even the most basic DSP text. These are all full of huge >> formulas and complex numbers... I'm not trying to sound lazy but I >> don't think it has to be that complicated. >> >> I just need a routine, and to learn how to use it (I seem to have found >> it at opencores >> (http://www.opencores.org/projects.cgi/web/biquad/overview) along with >> DSPlay to generate the coefficients. >> Regards, >> hjf >> > All of the folks that I've ever met with the title "systems engineer" > are people who are very good at math* _and_ at applying it to the real > world. I'm not sure what systems engineering one could do without that > capability. > > * Regrettably the 's' fell overboard somewhere in the Atlantic. >Article: 93922
u_stadler@yahoo.de wrote: > hi > > I have a question: what is the proper way to generate c slow clock. I > have a spartan 3 development board with a 50 MHz external clock. What i > need is a 4MHz clock for an SPI interface. Since the DCM's can only > deliver 18 MHz output with the frequency synthesiser (CLKFX) I need to > devide this clock some more. how is this done properly? a counter? Or > is ther any other sollution? > > Thanks > Urban > The DCM has a clkdv output which will allow you to get 4 MHz directly out of the DCM without violating the minimum frequency constraints.Article: 93923
Read the EDID information off the monitor. You'll need a PC with a DVI port and the utility found here: http://www.viewsonic.com/support/drivers/driver_information.cfm?product=all&formName=product&key=87 Make sure the FPGA is generating timings supported by the monitor you are using. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian eCinema Systems, Inc. To send private email: x@y where x = "martineu" y = "pacbell.net" "Antti Lukats" <antti@openchip.org> wrote in message news:dpbj0l$6ea$00$1@news.t-online.com... > <ALuPin@web.de> schrieb im Newsbeitrag > news:1136217553.293210.133940@g43g2000cwa.googlegroups.com... > > What frequency / resolution are you working with ? > > Rgds > André > > basic VGA, 25MHz XCLK > > after some more testing > > 1) if I turn monitor off then on again, it remains ON (no auto power off) > and does not display loss of signal > 2) when I then write 0x00 to 0x49 shutting down the DVI output then > monitor does respond with 'loss of signal' > > so I assume my sync/de signals are messed up - will be fighting again > tomorrow > > Antti > > >Article: 93924
Urban, Here's another idea to add to your thread! Divide the 50MHz by 16 with a 4 bit counter and run the SPI interface at 3.125MHz. Cheers, Syms.
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